stats: Update to reflect changes to PCI handling

155 files changed, 41941 insertions, 42710 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
index db58f5ad6..2c8d05298 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/work/gem5/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/work/gem5/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -26,9 +26,10 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/work/gem5/dist/binaries/ts_osfpal
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -146,6 +147,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -162,6 +164,7 @@ system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
@@ -569,6 +572,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -585,6 +589,7 @@ system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
@@ -618,6 +623,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -634,6 +640,7 @@ system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
@@ -649,12 +656,13 @@ size=4194304
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_latency=0
 frontend_latency=1
 response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
 system=system
 use_default_range=false
@@ -662,6 +670,13 @@ width=32
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
 [system.cpu.tracer]
 type=ExeTracer
 eventq_index=0
@@ -694,7 +709,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -717,7 +732,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -740,10 +755,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.tsunami.pciconfig.pio
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
@@ -752,6 +766,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
@@ -768,7 +783,8 @@ system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
-cpu_side=system.iobus.master[29]
+writeback_clean=false
+cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[2]
 
 [system.iocache.tags]
@@ -903,7 +919,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -916,7 +932,7 @@ port=3456
 
 [system.tsunami]
 type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -1029,12 +1045,12 @@ dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
 hardware_address=00:90:00:00:00:01
+host=system.tsunami.pchip
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 rss=false
 rx_delay=1000000
 rx_fifo_size=524288
@@ -1044,9 +1060,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.master[28]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[27]
+pio=system.iobus.master[26]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1479,14 +1494,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
 eventq_index=0
+host=system.tsunami.pchip
 io_shift=0
 pci_bus=0
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 system=system
-config=system.iobus.master[26]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[25]
 
@@ -1506,25 +1520,20 @@ pio=system.iobus.master[22]
 [system.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=system.clk_domain
+conf_base=8804649402368
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
+pci_dma_base=0
+pci_mem_base=8796093022208
+pci_pio_base=8804615847936
 pio_addr=8802535473152
 pio_latency=100000
+platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.master[1]
 
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
 [system.tsunami.uart]
 type=Uart8250
 clk_domain=system.clk_domain
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr
index 518507880..518507880 100644..100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
index cc37eeb13..f8b3a5e40 100644..100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
@@ -1,12 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 29 2014 09:12:51
-gem5 started Oct 29 2014 09:20:31
-gem5 executing on u200540-lin
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor
+gem5 compiled Dec  4 2015 10:28:58
+gem5 started Dec  4 2015 10:29:11
+gem5 executing on e104799-lin, pid 21295
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor
+
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/binaries/vmlinux
+info: kernel located at: /work/gem5/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1883224346500 because m5_exit instruction encountered
+Exiting @ tick 1906048606500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
index a07783bfc..c02ff892c 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.906049                       # Nu
 sim_ticks                                1906048606500                       # Number of ticks simulated
 final_tick                               1906048606500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 269376                       # Simulator instruction rate (inst/s)
-host_op_rate                                   269376                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9144869235                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 376080                       # Number of bytes of host memory used
-host_seconds                                   208.43                       # Real time elapsed on the host
+host_inst_rate                                 268534                       # Simulator instruction rate (inst/s)
+host_op_rate                                   268534                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9116285517                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 332204                       # Number of bytes of host memory used
+host_seconds                                   209.08                       # Real time elapsed on the host
 sim_insts                                    56145568                       # Number of instructions simulated
 sim_ops                                      56145568                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -150,10 +150,10 @@ system.physmem.wrQLenPdf::13                        1                       # Wh
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::15                     1565                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::16                     1858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5601                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5600                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                     5604                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                     6269                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6565                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::21                     5995                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                     6437                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     7880                       # What write queue length does an incoming req see
@@ -197,20 +197,20 @@ system.physmem.wrQLenPdf::60                       53                       # Wh
 system.physmem.wrQLenPdf::61                       67                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                       24                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                       70                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64393                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      519.603311                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     318.318586                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     407.156918                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14830     23.03%     23.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11097     17.23%     40.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4950      7.69%     47.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3246      5.04%     52.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2531      3.93%     56.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1970      3.06%     59.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4174      6.48%     66.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1358      2.11%     68.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20237     31.43%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64393                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        64400                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      519.546832                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     318.268868                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     407.153797                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14837     23.04%     23.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11098     17.23%     40.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4944      7.68%     47.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3257      5.06%     53.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2526      3.92%     56.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1968      3.06%     59.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4176      6.48%     66.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1357      2.11%     68.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20237     31.42%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64400                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          5302                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::mean        76.317050                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::stdev     2899.726540                       # Reads before turning the bus around for writes
@@ -260,12 +260,12 @@ system.physmem.wrPerTurnAround::208-211             1      0.02%     99.96% # Wr
 system.physmem.wrPerTurnAround::212-215             1      0.02%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::228-231             1      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5302                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2636864500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10223958250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     2637486000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10224579750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                   2023225000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6516.49                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6518.02                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25266.49                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25268.02                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.59                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.97                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.59                       # Average system read bandwidth in MiByte/s
@@ -276,39 +276,39 @@ system.physmem.busUtilRead                       0.11                       # Da
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        26.35                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     362818                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95583                       # Number of row buffer hits during writes
+system.physmem.readRowHits                     362820                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     95574                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   89.66                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  80.88                       # Row buffer hit rate for writes
 system.physmem.avgGap                      3644923.65                       # Average gap between requests
 system.physmem.pageHitRate                      87.68                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  237542760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  129611625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy                  237573000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  129628125                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                1576816800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                380077920                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           124493453760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            67952834145                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1084018111500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1278788448510                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.912661                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1803102997000                       # Time in different power states
+system.physmem_0.actBackEnergy            67955758245                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1084015546500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1278788854350                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.912874                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1803098707000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     63646960000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     39293158000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     39297448000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  249268320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  136009500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  249291000                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  136021875                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                1579414200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                385527600                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           124493453760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            68401366290                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1083624670500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1278869710170                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.955290                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1802449451000                       # Time in different power states
+system.physmem_1.actBackEnergy            68412640320                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1083614781000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1278871129755                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.956034                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1802432810250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     63646960000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     39946717750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     39963358500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                15009028                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          13018563                       # Number of conditional branches predicted
@@ -375,10 +375,10 @@ system.cpu.kern.ipl_good::21                      133      0.09%     49.41% # nu
 system.cpu.kern.ipl_good::22                     1904      1.28%     50.68% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73439     49.32%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                148914                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1837271257000     96.39%     96.39% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1837271633000     96.39%     96.39% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::21                83690500      0.00%     96.40% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::22               707098000      0.04%     96.43% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             67985555000      3.57%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             67985179000      3.57%    100.00% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::total         1906047600500                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981726                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
@@ -447,8 +447,8 @@ system.cpu.kern.mode_ticks::kernel        38721238500      2.03%      2.03% # nu
 system.cpu.kern.mode_ticks::user           4530290000      0.24%      2.27% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks::idle         1862796062000     97.73%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
-system.cpu.tickCycles                        84511190                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       137195507                       # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles                        84511215                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       137195482                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements           1395430                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.976766                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            13774781                       # Total number of references to valid blocks.
@@ -487,16 +487,16 @@ system.cpu.dcache.demand_misses::cpu.data      1776836                       # n
 system.cpu.dcache.demand_misses::total        1776836                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1776836                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1776836                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  46974936500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  46974936500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  33956179000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  33956179000                       # number of WriteReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  46974912500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  46974912500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  33956321000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  33956321000                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    234952500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total    234952500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  80931115500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  80931115500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  80931115500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  80931115500                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  80931233500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  80931233500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  80931233500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  80931233500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data      9017676                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total      9017676                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6152051                       # number of WriteReq accesses(hits+misses)
@@ -519,16 +519,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.117130
 system.cpu.dcache.demand_miss_rate::total     0.117130                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.117130                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.117130                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.646994                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.646994                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.177737                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.177737                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.627021                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.627021                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.424605                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.424605                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.881459                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45547.881459                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.881459                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45547.881459                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.947869                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45547.947869                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.947869                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45547.947869                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -565,22 +565,22 @@ system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9624
 system.cpu.dcache.WriteReq_mshr_uncacheable::total         9624                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16558                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        16558                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43817588500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43817588500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17272399000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17272399000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43817391500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43817391500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17272477000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  17272477000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    217466000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    217466000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61089987500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  61089987500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61089987500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  61089987500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1530266500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1530266500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61089868500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  61089868500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61089868500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  61089868500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1529366500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1529366500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2162508500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2162508500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3692775000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3692775000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3691875000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3691875000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119139                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119139                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049480                       # mshr miss rate for WriteReq accesses
@@ -591,28 +591,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090889
 system.cpu.dcache.demand_mshr_miss_rate::total     0.090889                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090889                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.090889                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40785.018453                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40785.018453                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.508845                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.508845                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40784.835087                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40784.835087                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.765083                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.765083                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12627.954242                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12627.954242                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.919797                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.919797                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.919797                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.919797                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220690.294202                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220690.294202                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.833488                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.833488                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.833488                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.833488                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.498990                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.498990                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224699.553200                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224699.553200                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223020.594275                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223020.594275                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222966.239884                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222966.239884                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements           1460396                       # number of replacements
 system.cpu.icache.tags.tagsinuse           508.105648                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            18947784                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs            18947783                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs           1460907                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             12.969877                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs             12.969876                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       50119711500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   508.105648                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.992394                       # Average percentage of cache occupancy
@@ -622,44 +622,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0          103
 system.cpu.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          406                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          21869953                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         21869953                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     18947787                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        18947787                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      18947787                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         18947787                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     18947787                       # number of overall hits
-system.cpu.icache.overall_hits::total        18947787                       # number of overall hits
+system.cpu.icache.tags.tag_accesses          21869952                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         21869952                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     18947786                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        18947786                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      18947786                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         18947786                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     18947786                       # number of overall hits
+system.cpu.icache.overall_hits::total        18947786                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst      1461083                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total       1461083                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst      1461083                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total        1461083                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst      1461083                       # number of overall misses
 system.cpu.icache.overall_misses::total       1461083                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  21009217000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  21009217000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  21009217000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  21009217000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  21009217000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  21009217000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     20408870                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     20408870                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     20408870                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     20408870                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     20408870                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     20408870                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  21009954000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  21009954000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  21009954000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  21009954000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  21009954000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  21009954000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     20408869                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     20408869                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     20408869                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     20408869                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     20408869                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     20408869                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.071591                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.071591                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.071591                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.071591                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.071591                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.071591                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.208436                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14379.208436                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.208436                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14379.208436                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.208436                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14379.208436                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.712857                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14379.712857                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.712857                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14379.712857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.712857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14379.712857                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -676,34 +676,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst      1461083
 system.cpu.icache.demand_mshr_misses::total      1461083                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst      1461083                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total      1461083                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19548134000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  19548134000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19548134000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  19548134000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19548134000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  19548134000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  19548871000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  19548871000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  19548871000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  19548871000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  19548871000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  19548871000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.071591                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.071591                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.071591                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.071591                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.071591                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.071591                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.208436                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.208436                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.208436                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.208436                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.208436                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.208436                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.712857                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.712857                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.712857                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.712857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.712857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.712857                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           339568                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65260.797469                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        65260.797416                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4999517                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           404730                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs            12.352722                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle       9687465000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251550                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5724.395782                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5490.150137                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251440                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5724.395876                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5490.150100                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.824680                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087347                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.083773                       # Average percentage of cache occupancy
@@ -751,18 +751,18 @@ system.cpu.l2cache.overall_misses::cpu.data       388866                       #
 system.cpu.l2cache.overall_misses::total       405190                       # number of overall misses
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       404000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       404000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14837528000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  14837528000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2141943000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2141943000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33680651000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  33680651000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2141943000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  48518179000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  50660122000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2141943000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  48518179000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  50660122000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14837606000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14837606000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2142680000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2142680000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33680454000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  33680454000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   2142680000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  48518060000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  50660740000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   2142680000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  48518060000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  50660740000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       838232                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       838232                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks      1459802                       # number of WritebackClean accesses(hits+misses)
@@ -797,18 +797,18 @@ system.cpu.l2cache.overall_miss_rate::cpu.data     0.278565
 system.cpu.l2cache.overall_miss_rate::total     0.141825                       # miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22444.444444                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22444.444444                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.169443                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.169443                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131214.346974                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131214.346974                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.759286                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.759286                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131214.346974                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.375224                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 125028.065846                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131214.346974                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.375224                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 125028.065846                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.838058                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.838058                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131259.495222                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131259.495222                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.035572                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.035572                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131259.495222                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.069206                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 125029.591056                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131259.495222                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.069206                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 125029.591056                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -841,24 +841,24 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16558
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16558                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1285500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1285500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13670938000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13670938000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1978703000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1978703000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  30960659500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  30960659500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1978703000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44631597500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  46610300500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1978703000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44631597500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  46610300500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1443571000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1443571000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13671016000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13671016000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1979440000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1979440000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  30960462500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  30960462500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1979440000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44631478500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  46610918500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1979440000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44631478500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  46610918500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1442671000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1442671000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2051831500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2051831500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3495402500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3495402500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3494502500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3494502500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.818182                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.818182                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383225                       # mshr miss rate for ReadExReq accesses
@@ -875,24 +875,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.278565
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.141825                       # mshr miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.169443                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.169443                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121214.346974                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121214.346974                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113739.395019                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113739.395019                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121214.346974                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.720253                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115033.195538                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121214.346974                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.720253                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115033.195538                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208187.337756                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208187.337756                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.838058                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.838058                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121259.495222                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121259.495222                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113738.671305                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113738.671305                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121259.495222                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.414235                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115034.720748                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121259.495222                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.414235                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115034.720748                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.542544                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.542544                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211100.525426                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211100.525426                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211046.171035                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211046.171035                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5712890                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2856017                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -958,40 +958,34 @@ system.iobus.trans_dist::ReadResp                7107                       # Tr
 system.iobus.trans_dist::WriteReq               51176                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              51176                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5110                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total        33116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  116566                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20440                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total        44381                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2705989                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy              5423500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               386000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               784500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1005,16 +999,10 @@ system.iobus.reqLayer24.occupancy             2308500                       # La
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy             5938000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              224500                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               98500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               98500                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           215092991                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              142500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           215092991                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               31500                       # Layer occupancy (ticks)
-system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23492000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
@@ -1161,7 +1149,7 @@ system.membus.reqLayer1.occupancy          1319381154                       # La
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy               22500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2160247074                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2160244574                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy           69858432                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
index 455709c02..2c979b67f 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 08ac5b1cf..c1955556a 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/work/gem5/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/work/gem5/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -26,9 +26,10 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/work/gem5/dist/binaries/ts_osfpal
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -171,6 +172,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -187,6 +189,7 @@ system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
@@ -518,6 +521,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -534,6 +538,7 @@ system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
@@ -676,6 +681,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -692,6 +698,7 @@ system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
@@ -1023,6 +1030,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -1039,6 +1047,7 @@ system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
@@ -1098,7 +1107,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -1121,7 +1130,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -1144,10 +1153,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.tsunami.pciconfig.pio
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
@@ -1156,6 +1164,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
@@ -1172,7 +1181,8 @@ system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
-cpu_side=system.iobus.master[29]
+writeback_clean=false
+cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[2]
 
 [system.iocache.tags]
@@ -1191,6 +1201,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -1207,6 +1218,7 @@ system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
@@ -1342,7 +1354,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -1355,12 +1367,13 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_latency=0
 frontend_latency=1
 response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
 snoop_response_latency=1
 system=system
 use_default_range=false
@@ -1368,9 +1381,16 @@ width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
 
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
 [system.tsunami]
 type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -1483,12 +1503,12 @@ dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
 hardware_address=00:90:00:00:00:01
+host=system.tsunami.pchip
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 rss=false
 rx_delay=1000000
 rx_fifo_size=524288
@@ -1498,9 +1518,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.master[28]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[27]
+pio=system.iobus.master[26]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1933,14 +1952,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
 eventq_index=0
+host=system.tsunami.pchip
 io_shift=0
 pci_bus=0
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 system=system
-config=system.iobus.master[26]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[25]
 
@@ -1960,25 +1978,20 @@ pio=system.iobus.master[22]
 [system.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=system.clk_domain
+conf_base=8804649402368
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
+pci_dma_base=0
+pci_mem_base=8796093022208
+pci_pio_base=8804615847936
 pio_addr=8802535473152
 pio_latency=100000
+platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.master[1]
 
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
 [system.tsunami.uart]
 type=Uart8250
 clk_domain=system.clk_domain
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index 7f9e2b29d..f71ac7b91 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -1,14 +1,14 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 07:55:25
-gem5 started Apr 22 2015 09:01:06
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+gem5 compiled Dec  4 2015 10:28:58
+gem5 started Dec  4 2015 10:42:11
+gem5 executing on e104799-lin, pid 22878
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /work/gem5/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 133655000
-Exiting @ tick 1904437574000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 179187500
+Exiting @ tick 1922761887500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 091040252..123211008 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.922762                       # Nu
 sim_ticks                                1922761887500                       # Number of ticks simulated
 final_tick                               1922761887500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 132982                       # Simulator instruction rate (inst/s)
-host_op_rate                                   132982                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4507220686                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384024                       # Number of bytes of host memory used
-host_seconds                                   426.60                       # Real time elapsed on the host
+host_inst_rate                                 136693                       # Simulator instruction rate (inst/s)
+host_op_rate                                   136693                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4632993573                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 339884                       # Number of bytes of host memory used
+host_seconds                                   415.02                       # Real time elapsed on the host
 sim_insts                                    56729467                       # Number of instructions simulated
 sim_ops                                      56729467                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -111,8 +111,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                 123171                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    317968                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     37909                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    317967                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     37910                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                     29466                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                     24871                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        87                       # What read queue length does an incoming req see
@@ -168,14 +168,14 @@ system.physmem.wrQLenPdf::21                     6400                       # Wh
 system.physmem.wrQLenPdf::22                     6805                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     8203                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                     8579                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9709                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9707                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8953                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                     9138                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::28                     8272                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::29                     8747                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     6829                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6928                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6099                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                      325                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                      196                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                      232                       # What write queue length does an incoming req see
@@ -207,20 +207,20 @@ system.physmem.wrQLenPdf::60                       52                       # Wh
 system.physmem.wrQLenPdf::61                       69                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                       45                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65327                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      522.630582                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     319.337054                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     410.684018                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14917     22.83%     22.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11339     17.36%     40.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5448      8.34%     48.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        65324                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      522.654583                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     319.374945                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     410.670236                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14914     22.83%     22.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11338     17.36%     40.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5449      8.34%     48.53% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::384-511         2879      4.41%     52.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2603      3.98%     56.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1650      2.53%     59.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3828      5.86%     65.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2604      3.99%     56.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1649      2.52%     59.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3829      5.86%     65.31% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023         1203      1.84%     67.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21460     32.85%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65327                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21459     32.85%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65324                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          5559                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::mean        73.810757                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::stdev     2831.423020                       # Reads before turning the bus around for writes
@@ -271,12 +271,12 @@ system.physmem.wrPerTurnAround::220-223             1      0.02%     99.96% # Wr
 system.physmem.wrPerTurnAround::228-231             1      0.02%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::252-255             1      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5559                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4492977750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               12186571500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     4493146250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               12186740000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                   2051625000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10949.80                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       10950.21                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29699.80                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29700.21                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.66                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.10                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.66                       # Average system read bandwidth in MiByte/s
@@ -287,39 +287,39 @@ system.physmem.busUtilRead                       0.11                       # Da
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         2.26                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        25.48                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     369433                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     98707                       # Number of row buffer hits during writes
+system.physmem.readRowHits                     369435                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     98708                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   90.03                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  80.14                       # Row buffer hit rate for writes
 system.physmem.avgGap                      3603301.16                       # Average gap between requests
 system.physmem.pageHitRate                      87.75                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  247242240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  134904000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy                  247227120                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  134895750                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                1602939000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                400671360                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           125585332080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            63449600445                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1097998572000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1289419261125                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.608464                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1826410636250                       # Time in different power states
+system.physmem_0.actBackEnergy            63448746300                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1097999321250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1289419132860                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.608398                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1826411929500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     64205180000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32144391250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32143098000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  246629880                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  134569875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  246622320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  134565750                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                1597596000                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                397288800                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           125585332080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            62800369875                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1098568064250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1289329850760                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.561968                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1827364141250                       # Time in different power states
+system.physmem_1.actBackEnergy            62799950070                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1098568432500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1289329787520                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.561935                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1827364757000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     64205180000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     31190872500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     31190256750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu0.branchPred.lookups               16164803                       # Number of BP lookups
 system.cpu0.branchPred.condPredicted         14134057                       # Number of conditional branches predicted
@@ -366,11 +366,11 @@ system.cpu0.itb.data_accesses                       0                       # DT
 system.cpu0.numCycles                       147492353                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          26474453                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.icacheStallCycles          26474452                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu0.fetch.Insts                      70295181                       # Number of instructions fetch has processed
 system.cpu0.fetch.Branches                   16164803                       # Number of branches that fetch encountered
 system.cpu0.fetch.predictedBranches           6131250                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    112661982                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.Cycles                    112660359                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu0.fetch.SquashCycles                1056864                       # Number of cycles fetch has spent squashing
 system.cpu0.fetch.TlbCycles                       660                       # Number of cycles fetch has spent waiting for tlb
 system.cpu0.fetch.MiscStallCycles               29689                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
@@ -378,12 +378,12 @@ system.cpu0.fetch.PendingTrapStallCycles       929577                       # Nu
 system.cpu0.fetch.PendingQuiesceStallCycles       461648                       # Number of stall cycles due to pending quiesce instructions
 system.cpu0.fetch.IcacheWaitRetryStallCycles          350                       # Number of stall cycles due to full MSHR
 system.cpu0.fetch.CacheLines                  8123308                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               229144                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples         141086791                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.498241                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.734215                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.IcacheSquashes               229143                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples         141085167                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.498246                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.734224                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               127943316     90.68%     90.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               127941692     90.68%     90.68% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::1                  834789      0.59%     91.28% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::2                 1813592      1.29%     92.56% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::3                  779670      0.55%     93.11% # Number of instructions fetched each cycle (Total)
@@ -395,35 +395,35 @@ system.cpu0.fetch.rateDist::8                 5070041      3.59%    100.00% # Nu
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           141086791                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::total           141085167                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.branchRate                 0.109598                       # Number of branch fetches per cycle
 system.cpu0.fetch.rate                       0.476602                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                21397284                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            108971969                       # Number of cycles decode is blocked
+system.cpu0.decode.IdleCycles                21397283                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            108970346                       # Number of cycles decode is blocked
 system.cpu0.decode.RunCycles                  8457985                       # Number of cycles decode is running
 system.cpu0.decode.UnblockCycles              1766417                       # Number of cycles decode is unblocking
 system.cpu0.decode.SquashCycles                493135                       # Number of cycles decode is squashing
 system.cpu0.decode.BranchResolved              516601                       # Number of times decode resolved a branch
 system.cpu0.decode.BranchMispred                35757                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              61523411                       # Number of instructions handled by decode
+system.cpu0.decode.DecodedInsts              61523415                       # Number of instructions handled by decode
 system.cpu0.decode.SquashedInsts               108836                       # Number of squashed instructions handled by decode
 system.cpu0.rename.SquashCycles                493135                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                22231623                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               77943277                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      19950150                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.IdleCycles                22231622                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               77943613                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      19948481                       # count of cycles rename stalled for serializing inst
 system.cpu0.rename.RunCycles                  9304003                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             11164601                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              59421423                       # Number of instructions processed by rename
+system.cpu0.rename.UnblockCycles             11164311                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              59421431                       # Number of instructions processed by rename
 system.cpu0.rename.ROBFullEvents               199471                       # Number of times rename has blocked due to ROB full
 system.cpu0.rename.IQFullEvents               2023547                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                224739                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               7186522                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           39708138                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             72284773                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        72145342                       # Number of integer rename lookups
+system.cpu0.rename.LQFullEvents                224227                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               7186744                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           39708144                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             72284783                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        72145352                       # Number of integer rename lookups
 system.cpu0.rename.fp_rename_lookups           129802                       # Number of floating rename lookups
 system.cpu0.rename.CommittedMaps             34979364                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 4728766                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.UndoneMaps                 4728772                       # Number of HB maps that are undone due to squashing
 system.cpu0.rename.serializingInsts           1463848                       # count of serializing insts renamed
 system.cpu0.rename.tempSerializingInsts        211077                       # count of temporary serializing insts renamed
 system.cpu0.rename.skidInsts                 12544775                       # count of insts added to the skid buffer
@@ -431,30 +431,30 @@ system.cpu0.memDep0.insertedLoads             9257817                       # Nu
 system.cpu0.memDep0.insertedStores            6153108                       # Number of stores inserted to the mem dependence unit.
 system.cpu0.memDep0.conflictingLoads          1360057                       # Number of conflicting loads.
 system.cpu0.memDep0.conflictingStores         1005705                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  53010072                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsAdded                  53010076                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu0.iq.iqNonSpecInstsAdded            1876155                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 52220775                       # Number of instructions issued
+system.cpu0.iq.iqInstsIssued                 52220777                       # Number of instructions issued
 system.cpu0.iq.iqSquashedInstsIssued            51551                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        6501427                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      2875305                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedInstsExamined        6501431                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      2875308                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu0.iq.iqSquashedNonSpecRemoved       1291728                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    141086791                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.370132                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.087511                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::samples    141085167                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.370137                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.087516                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          119618317     84.78%     84.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            9300566      6.59%     91.38% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3865351      2.74%     94.12% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          119616695     84.78%     84.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            9300562      6.59%     91.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3865352      2.74%     94.12% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::3            2730572      1.94%     96.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2821391      2.00%     98.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1375833      0.98%     99.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             902269      0.64%     99.67% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2821393      2.00%     98.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1375831      0.98%     99.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             902270      0.64%     99.67% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7             360488      0.26%     99.92% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8             112004      0.08%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      141086791                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      141085167                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IntAlu                 182068     18.38%     18.38% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IntMult                     2      0.00%     18.38% # attempts to use FU when none available
@@ -490,7 +490,7 @@ system.cpu0.iq.fu_full::MemWrite               337015     34.02%    100.00% # at
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             3780      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             35835166     68.62%     68.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             35835168     68.62%     68.63% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntMult               56519      0.11%     68.74% # Type of FU issued
 system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.74% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatAdd              28571      0.05%     68.79% # Type of FU issued
@@ -523,17 +523,17 @@ system.cpu0.iq.FU_type_0::MemRead             9523186     18.24%     87.03% # Ty
 system.cpu0.iq.FU_type_0::MemWrite            5952100     11.40%     98.43% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess            819570      1.57%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              52220775                       # Type of FU issued
+system.cpu0.iq.FU_type_0::total              52220777                       # Type of FU issued
 system.cpu0.iq.rate                          0.354058                       # Inst issue rate
 system.cpu0.iq.fu_busy_cnt                     990706                       # FU busy when requested
 system.cpu0.iq.fu_busy_rate                  0.018971                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         245999962                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         61137242                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_reads         245998342                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         61137250                       # Number of integer instruction queue writes
 system.cpu0.iq.int_inst_queue_wakeup_accesses     50831283                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads             570635                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes            267757                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses       262095                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              52900144                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses              52900146                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                 307557                       # Number of floating point alu accesses
 system.cpu0.iew.lsq.thread0.forwLoads          581308                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
@@ -544,13 +544,13 @@ system.cpu0.iew.lsq.thread0.squashedStores       500436                       #
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads        18736                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       408208                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked       408207                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
 system.cpu0.iew.iewSquashCycles                493135                       # Number of cycles IEW is squashing
 system.cpu0.iew.iewBlockCycles               74418027                       # Number of cycles IEW is blocking
 system.cpu0.iew.iewUnblockCycles              1058724                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           58259516                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           116557                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispatchedInsts           58259520                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           116565                       # Number of squashed instructions skipped by dispatch
 system.cpu0.iew.iewDispLoadInsts              9257817                       # Number of dispatched load instructions
 system.cpu0.iew.iewDispStoreInsts             6153108                       # Number of dispatched store instructions
 system.cpu0.iew.iewDispNonSpecInsts           1657861                       # Number of dispatched non-speculative instructions
@@ -562,7 +562,7 @@ system.cpu0.iew.predictedNotTakenIncorrect       351909                       #
 system.cpu0.iew.branchMispredicts              505215                       # Number of branch mispredicts detected at execute
 system.cpu0.iew.iewExecutedInsts             51717296                       # Number of executed instructions
 system.cpu0.iew.iewExecLoadInsts              9230924                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           503478                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecSquashedInsts           503480                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu0.iew.exec_nop                      3373289                       # number of nop insts executed
 system.cpu0.iew.exec_refs                    15132335                       # number of memory reference insts executed
@@ -571,22 +571,22 @@ system.cpu0.iew.exec_stores                   5901411                       # Nu
 system.cpu0.iew.exec_rate                    0.350644                       # Inst execution rate
 system.cpu0.iew.wb_sent                      51207379                       # cumulative count of insts sent to commit
 system.cpu0.iew.wb_count                     51093378                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 26334207                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 36473944                       # num instructions consuming a value
+system.cpu0.iew.wb_producers                 26334208                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 36473947                       # num instructions consuming a value
 system.cpu0.iew.wb_rate                      0.346414                       # insts written-back per cycle
 system.cpu0.iew.wb_fanout                    0.722001                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts        6824839                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitSquashedInsts        6824843                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls         584427                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu0.commit.branchMispredicts           463110                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    139882457                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.366962                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.256012                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::samples    139880833                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.366966                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.256019                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    121750983     87.04%     87.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7187616      5.14%     92.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    121749360     87.04%     87.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7187615      5.14%     92.18% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::2      3944064      2.82%     95.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2051217      1.47%     96.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1611428      1.15%     97.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2051216      1.47%     96.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1611429      1.15%     97.61% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::5       577022      0.41%     98.03% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::6       437359      0.31%     98.34% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::7       434985      0.31%     98.65% # Number of insts commited each cycle
@@ -594,7 +594,7 @@ system.cpu0.commit.committed_per_cycle::8      1887783      1.35%    100.00% # N
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    139882457                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::total    139880833                       # Number of insts commited each cycle
 system.cpu0.commit.committedInsts            51331530                       # Number of instructions committed
 system.cpu0.commit.committedOps              51331530                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
@@ -641,10 +641,10 @@ system.cpu0.commit.op_class_0::IprAccess       819569      1.60%    100.00% # Cl
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::total         51331530                       # Class of committed instruction
 system.cpu0.commit.bw_lim_events              1887783                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   195950193                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  117511428                       # The number of ROB writes
+system.cpu0.rob.rob_reads                   195948573                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  117511436                       # The number of ROB writes
 system.cpu0.timesIdled                         525574                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        6405562                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.idleCycles                        6407186                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu0.quiesceCycles                  3698031423                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu0.committedInsts                   48384795                       # Number of Instructions Simulated
 system.cpu0.committedOps                     48384795                       # Number of Ops (including micro ops) Simulated
@@ -659,12 +659,12 @@ system.cpu0.fp_regfile_writes                  130249                       # nu
 system.cpu0.misc_regfile_reads                1711265                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                819270                       # number of misc regfile writes
 system.cpu0.dcache.tags.replacements          1282737                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.160384                       # Cycle average of tags in use
+system.cpu0.dcache.tags.tagsinuse          506.160385                       # Cycle average of tags in use
 system.cpu0.dcache.tags.total_refs           10524244                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs          1283249                       # Sample count of references to valid blocks.
 system.cpu0.dcache.tags.avg_refs             8.201249                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         36569500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.160384                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.160385                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988595                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.988595                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -698,18 +698,18 @@ system.cpu0.dcache.demand_misses::cpu0.data      3363608                       #
 system.cpu0.dcache.demand_misses::total       3363608                       # number of demand (read+write) misses
 system.cpu0.dcache.overall_misses::cpu0.data      3363608                       # number of overall misses
 system.cpu0.dcache.overall_misses::total      3363608                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  54837998000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  54837998000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114303059042                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 114303059042                       # number of WriteReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  54836064000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  54836064000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114300477543                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 114300477543                       # number of WriteReq miss cycles
 system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    389087500                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.LoadLockedReq_miss_latency::total    389087500                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     45510000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total     45510000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 169141057042                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 169141057042                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 169141057042                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 169141057042                       # number of overall miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 169136541543                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 169136541543                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 169136541543                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 169136541543                       # number of overall miss cycles
 system.cpu0.dcache.ReadReq_accesses::cpu0.data      8078505                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total      8078505                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data      5447584                       # number of WriteReq accesses(hits+misses)
@@ -734,23 +734,23 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data     0.248676
 system.cpu0.dcache.demand_miss_rate::total     0.248676                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.248676                       # miss rate for overall accesses
 system.cpu0.dcache.overall_miss_rate::total     0.248676                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34387.118782                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 34387.118782                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64618.778654                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 64618.778654                       # average WriteReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34385.906034                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 34385.906034                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64617.319259                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 64617.319259                       # average WriteReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18489.236837                       # average LoadLockedReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18489.236837                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15934.873950                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15934.873950                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50285.603151                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 50285.603151                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50285.603151                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 50285.603151                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      6995611                       # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50284.260694                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 50284.260694                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50284.260694                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 50284.260694                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      6995201                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets        14546                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           119540                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           119539                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets            103                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    58.521089                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    58.518149                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets   141.223301                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
@@ -784,24 +784,24 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10126
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10126                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17171                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17171                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43466083500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  43466083500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  18236016784                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18236016784                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43465523500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  43465523500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  18235926784                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18235926784                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    187455000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    187455000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     42654000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     42654000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61702100284                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  61702100284                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  61702100284                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  61702100284                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1563410000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1563410000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  61701450284                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  61701450284                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  61701450284                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  61701450284                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1562510000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1562510000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2299016000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2299016000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3862426000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3862426000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3861526000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3861526000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.125677                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.125677                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.048825                       # mshr miss rate for WriteReq accesses
@@ -814,24 +814,24 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.094725
 system.cpu0.dcache.demand_mshr_miss_rate::total     0.094725                       # mshr miss rate for demand accesses
 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.094725                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total     0.094725                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.790900                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.790900                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.382401                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.382401                       # average WriteReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.239329                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.239329                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.044026                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.044026                       # average WriteReq mshr miss latency
 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.017051                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.017051                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14934.873950                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14934.873950                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48157.360945                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48157.360945                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48157.360945                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48157.360945                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221917.672108                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221917.672108                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48156.853632                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48156.853632                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48156.853632                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48156.853632                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221789.921930                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221789.921930                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227040.884851                       # average WriteReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227040.884851                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224938.908625                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224938.908625                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224886.494671                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224886.494671                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.icache.tags.replacements           908501                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          508.069795                       # Cycle average of tags in use
@@ -861,12 +861,12 @@ system.cpu0.icache.demand_misses::cpu0.inst       954611                       #
 system.cpu0.icache.demand_misses::total        954611                       # number of demand (read+write) misses
 system.cpu0.icache.overall_misses::cpu0.inst       954611                       # number of overall misses
 system.cpu0.icache.overall_misses::total       954611                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14636609987                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  14636609987                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14636609987                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  14636609987                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14636609987                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  14636609987                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14637521487                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14637521487                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14637521487                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14637521487                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14637521487                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14637521487                       # number of overall miss cycles
 system.cpu0.icache.ReadReq_accesses::cpu0.inst      8123307                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::total      8123307                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.demand_accesses::cpu0.inst      8123307                       # number of demand (read+write) accesses
@@ -879,12 +879,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst     0.117515
 system.cpu0.icache.demand_miss_rate::total     0.117515                       # miss rate for demand accesses
 system.cpu0.icache.overall_miss_rate::cpu0.inst     0.117515                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     0.117515                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15332.538581                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 15332.538581                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15332.538581                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 15332.538581                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15332.538581                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 15332.538581                       # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15333.493420                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 15333.493420                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15333.493420                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 15333.493420                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15333.493420                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 15333.493420                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs         8572                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs              278                       # number of cycles access was blocked
@@ -907,24 +907,24 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst       909320
 system.cpu0.icache.demand_mshr_misses::total       909320                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses::cpu0.inst       909320                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_misses::total       909320                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12934939493                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  12934939493                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12934939493                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  12934939493                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12934939493                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  12934939493                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12935759993                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  12935759993                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12935759993                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  12935759993                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12935759993                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  12935759993                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.111940                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.111940                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.111940                       # mshr miss rate for demand accesses
 system.cpu0.icache.demand_mshr_miss_rate::total     0.111940                       # mshr miss rate for demand accesses
 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.111940                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total     0.111940                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14224.848780                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14224.848780                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14224.848780                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 14224.848780                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14224.848780                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 14224.848780                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14225.751103                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14225.751103                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14225.751103                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 14225.751103                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14225.751103                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 14225.751103                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.branchPred.lookups                3578846                       # Number of BP lookups
 system.cpu1.branchPred.condPredicted          3133511                       # Number of conditional branches predicted
@@ -1263,12 +1263,12 @@ system.cpu1.fp_regfile_writes                   51516                       # nu
 system.cpu1.misc_regfile_reads                 503472                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                210349                       # number of misc regfile writes
 system.cpu1.dcache.tags.replacements            98962                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          486.970751                       # Cycle average of tags in use
+system.cpu1.dcache.tags.tagsinuse          486.970752                       # Cycle average of tags in use
 system.cpu1.dcache.tags.total_refs            2466427                       # Total number of references to valid blocks.
 system.cpu1.dcache.tags.sampled_refs            99271                       # Sample count of references to valid blocks.
 system.cpu1.dcache.tags.avg_refs            24.845393                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     1048837181500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.970751                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.970752                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.951115                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.951115                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          309                       # Occupied blocks per task id
@@ -1543,40 +1543,34 @@ system.iobus.trans_dist::ReadResp                7371                       # Tr
 system.iobus.trans_dist::WriteReq               54609                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              54609                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1010                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total        40504                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83456                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83456                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  123960                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        47616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2733                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total        73842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661632                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661632                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2735474                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy             12353500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               448000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               827500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1590,16 +1584,10 @@ system.iobus.reqLayer24.occupancy             2829000                       # La
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy             5954500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              217500                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               87000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               87000                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           215061495                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              131500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           215061495                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               30500                       # Layer occupancy (ticks)
-system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            27447000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41952000                       # Layer occupancy (ticks)
@@ -1702,14 +1690,14 @@ system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75882.857955
 system.iocache.overall_avg_mshr_miss_latency::total 75882.857955                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.l2c.tags.replacements                   345304                       # number of replacements
-system.l2c.tags.tagsinuse                65190.216948                       # Cycle average of tags in use
+system.l2c.tags.tagsinuse                65190.216881                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    3990482                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                   410468                       # Sample count of references to valid blocks.
 system.l2c.tags.avg_refs                     9.721786                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle              11177481000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53120.456427                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5260.305215                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     6531.960123                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   53120.456317                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5260.305264                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6531.960119                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.inst      208.754945                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.data       68.740237                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.810554                       # Average percentage of cache occupancy
@@ -1787,25 +1775,25 @@ system.l2c.UpgradeReq_miss_latency::total     21371000                       # n
 system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2842500                       # number of SCUpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::cpu1.data       568500                       # number of SCUpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::total      3411000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  16040827500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  16040737500                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data   1166717500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  17207545000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1816563500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  17207455000                       # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1817383500                       # number of ReadCleanReq miss cycles
 system.l2c.ReadCleanReq_miss_latency::cpu1.inst    219865000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   2036428500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  33893464500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total   2037248500                       # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  33892904500                       # number of ReadSharedReq miss cycles
 system.l2c.ReadSharedReq_miss_latency::cpu1.data    116817000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  34010281500                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   1816563500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  49934292000                       # number of demand (read+write) miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  34009721500                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   1817383500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  49933642000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.inst    219865000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.data   1283534500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     53254255000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   1816563500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  49934292000                       # number of overall miss cycles
+system.l2c.demand_miss_latency::total     53254425000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   1817383500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  49933642000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.inst    219865000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.data   1283534500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    53254255000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    53254425000                       # number of overall miss cycles
 system.l2c.WritebackDirty_accesses::writebacks       820126                       # number of WritebackDirty accesses(hits+misses)
 system.l2c.WritebackDirty_accesses::total       820126                       # number of WritebackDirty accesses(hits+misses)
 system.l2c.WritebackClean_accesses::writebacks       859282                       # number of WritebackClean accesses(hits+misses)
@@ -1866,25 +1854,25 @@ system.l2c.UpgradeReq_avg_miss_latency::total  5500.900901
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6767.857143                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1289.115646                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total  3961.672474                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139638.451695                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139637.668228                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 159170.190996                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 140809.998036                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133649.462919                       # average ReadCleanReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 140809.261563                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133709.792525                       # average ReadCleanReq miss latency
 system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135052.211302                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 133799.507227                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124162.800026                       # average ReadSharedReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 133853.383706                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124160.748564                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140913.148372                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 124213.515093                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 133649.462919                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 128746.401960                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 124211.469842                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 133709.792525                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 128744.726054                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.inst 135052.211302                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data 157315.173428                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 129500.241958                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 133649.462919                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 128746.401960                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 129500.655353                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 133709.792525                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 128744.726054                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.inst 135052.211302                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data 157315.173428                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 129500.241958                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 129500.655353                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1946,34 +1934,34 @@ system.l2c.UpgradeReq_mshr_miss_latency::total    278688500
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     29951500                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     31656500                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total     61608000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  14892087500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  14891997500                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1093417500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  15985505000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1680522000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  15985415000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1681342000                       # number of ReadCleanReq MSHR miss cycles
 system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    201578500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   1882100500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  31173569000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1882920500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  31173009000                       # number of ReadSharedReq MSHR miss cycles
 system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    108527000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  31282096000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   1680522000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  46065656500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  31281536000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1681342000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  46065006500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.inst    201578500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.data   1201944500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  49149701500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   1680522000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  46065656500                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  49149871500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1681342000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  46065006500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.inst    201578500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.data   1201944500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  49149701500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1475287500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency::total  49149871500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1474387500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     28274500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1503562000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1502662000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2182363000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    649671500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.WriteReq_mshr_uncacheable_latency::total   2832034500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3657650500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3656750500                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.data    677946000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4335596500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4334696500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941457                       # mshr miss rate for UpgradeReq accesses
@@ -2007,34 +1995,34 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71734.491634
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71313.095238                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71783.446712                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71554.006969                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129638.451695                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129637.668228                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 149170.190996                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.998036                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123649.621073                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.261563                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123709.955117                       # average ReadCleanReq mshr miss latency
 system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125204.037267                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123814.255641                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114198.936903                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123868.199461                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114196.885440                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130913.148372                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114249.542558                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123649.621073                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118771.835761                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114247.497306                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123709.955117                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118770.159856                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125204.037267                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 147315.173428                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 119524.577467                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123649.621073                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118771.835761                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 119524.990881                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123709.955117                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118770.159856                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125204.037267                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 147315.173428                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 119524.577467                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209409.155429                       # average ReadReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_miss_latency::total 119524.990881                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209281.405252                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188496.666667                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208973.175817                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208848.088951                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215520.738692                       # average WriteReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221655.237120                       # average WriteReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216897.794287                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213013.249083                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212960.835129                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 220040.895813                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 214082.386925                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 214037.946869                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq                7195                       # Transaction distribution
 system.membus.trans_dist::ReadResp             296301                       # Transaction distribution
@@ -2082,7 +2070,7 @@ system.membus.reqLayer1.occupancy          1357207403                       # La
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy               98500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2187694355                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2187691105                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy           69834733                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
@@ -2190,11 +2178,11 @@ system.cpu0.kern.ipl_good::22                    1928      1.48%     50.79% # nu
 system.cpu0.kern.ipl_good::30                     186      0.14%     50.93% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::31                   63870     49.07%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::total               130171                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1865607975500     97.03%     97.03% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0            1865608787500     97.03%     97.03% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::21               63996500      0.00%     97.03% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::22              577908500      0.03%     97.06% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::30               88293000      0.00%     97.07% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            56422873000      2.93%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            56422061000      2.93%    100.00% # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_ticks::total        1922761046500                       # number of cycles we spent at this ipl
 system.cpu0.kern.ipl_used::0                 0.984568                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
index 1425d639e..195c1d872 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
@@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
 
SMP: 2 CPUs probed -- cpu_present_mask = 3
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 2be1ffca4..aa0a7c43b 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/work/gem5/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/work/gem5/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -26,9 +26,10 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/work/gem5/dist/binaries/ts_osfpal
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -171,6 +172,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -187,6 +189,7 @@ system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
@@ -518,6 +521,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -534,6 +538,7 @@ system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
@@ -567,6 +572,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -583,6 +589,7 @@ system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
@@ -598,12 +605,13 @@ size=4194304
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_latency=0
 frontend_latency=1
 response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
 system=system
 use_default_range=false
@@ -611,6 +619,13 @@ width=32
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
 [system.cpu.tracer]
 type=ExeTracer
 eventq_index=0
@@ -643,7 +658,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -666,7 +681,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -689,10 +704,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.tsunami.pciconfig.pio
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
@@ -701,6 +715,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
@@ -717,7 +732,8 @@ system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
-cpu_side=system.iobus.master[29]
+writeback_clean=false
+cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[2]
 
 [system.iocache.tags]
@@ -852,7 +868,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -865,7 +881,7 @@ port=3456
 
 [system.tsunami]
 type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -978,12 +994,12 @@ dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
 hardware_address=00:90:00:00:00:01
+host=system.tsunami.pchip
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 rss=false
 rx_delay=1000000
 rx_fifo_size=524288
@@ -993,9 +1009,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.master[28]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[27]
+pio=system.iobus.master[26]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1428,14 +1443,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
 eventq_index=0
+host=system.tsunami.pchip
 io_shift=0
 pci_bus=0
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 system=system
-config=system.iobus.master[26]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[25]
 
@@ -1455,25 +1469,20 @@ pio=system.iobus.master[22]
 [system.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=system.clk_domain
+conf_base=8804649402368
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
+pci_dma_base=0
+pci_mem_base=8796093022208
+pci_pio_base=8804615847936
 pio_addr=8802535473152
 pio_latency=100000
+platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.master[1]
 
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
 [system.tsunami.uart]
 type=Uart8250
 clk_domain=system.clk_domain
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index 25160cf8e..a50933284 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -1,13 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2015 07:55:25
-gem5 started Apr 22 2015 08:27:15
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
+gem5 compiled Dec  4 2015 10:28:58
+gem5 started Dec  4 2015 10:48:09
+gem5 executing on e104799-lin, pid 23716
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /work/gem5/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1861005569500 because m5_exit instruction encountered
+Exiting @ tick 1875760362000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index a3cafb881..f6eb98841 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.875760                       # Nu
 sim_ticks                                1875760362000                       # Number of ticks simulated
 final_tick                               1875760362000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 133605                       # Simulator instruction rate (inst/s)
-host_op_rate                                   133605                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4730094094                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 378388                       # Number of bytes of host memory used
-host_seconds                                   396.56                       # Real time elapsed on the host
+host_inst_rate                                 137394                       # Simulator instruction rate (inst/s)
+host_op_rate                                   137394                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4864266040                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 335280                       # Number of bytes of host memory used
+host_seconds                                   385.62                       # Real time elapsed on the host
 sim_insts                                    52982087                       # Number of instructions simulated
 sim_ops                                      52982087                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -101,10 +101,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                 117574                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    315453                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    315451                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                     35937                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     28173                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     23971                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     28174                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     23972                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        71                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
@@ -154,16 +154,16 @@ system.physmem.wrQLenPdf::17                     3242                       # Wh
 system.physmem.wrQLenPdf::18                     4193                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                     5460                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::20                     6573                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6002                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6433                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6003                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7856                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                     8316                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                     9450                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                     8577                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                     8739                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::28                     7869                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8334                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6429                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6430                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                     6478                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::32                     5661                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                      396                       # What write queue length does an incoming req see
@@ -197,23 +197,23 @@ system.physmem.wrQLenPdf::60                       43                       # Wh
 system.physmem.wrQLenPdf::61                       51                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                       27                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                       78                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62202                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      536.237934                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     330.496904                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     411.905259                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          13738     22.09%     22.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10541     16.95%     39.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        62200                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      536.255177                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     330.514254                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     411.900658                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13736     22.08%     22.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10542     16.95%     39.03% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383         4957      7.97%     47.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2730      4.39%     51.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2467      3.97%     55.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1593      2.56%     57.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3726      5.99%     63.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1160      1.86%     65.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        21290     34.23%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62202                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2726      4.38%     51.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2468      3.97%     55.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1593      2.56%     57.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3731      6.00%     63.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1159      1.86%     65.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21288     34.23%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          62200                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          5203                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::mean        77.574092                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2240.859567                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2240.859569                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-4095           5198     99.90%     99.90% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-8191            1      0.02%     99.92% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-45055            1      0.02%     99.94% # Reads before turning the bus around for writes
@@ -262,12 +262,12 @@ system.physmem.wrPerTurnAround::192-195             1      0.02%     99.90% # Wr
 system.physmem.wrPerTurnAround::196-199             2      0.04%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::228-231             3      0.06%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5203                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4177241750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11745266750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     4177261250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11745286250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                   2018140000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10349.24                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       10349.29                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29099.24                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29099.29                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.77                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.01                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.78                       # Average system read bandwidth in MiByte/s
@@ -279,44 +279,44 @@ system.physmem.busUtilWrite                      0.03                       # Da
 system.physmem.avgRdQLen                         2.11                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        25.14                       # Average write queue length when enqueuing
 system.physmem.readRowHits                     363742                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95234                       # Number of row buffer hits during writes
+system.physmem.writeRowHits                     95236                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   90.12                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  81.00                       # Row buffer hit rate for writes
 system.physmem.avgGap                      3598032.64                       # Average gap between requests
 system.physmem.pageHitRate                      88.06                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  232553160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  126889125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy                  232485120                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  126852000                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                1577284800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                378496800                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           122515155360                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            61473435525                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1071528687000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1257832501770                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              670.574130                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1782381530500                       # Time in different power states
+system.physmem_0.actBackEnergy            61464969315                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1071536113500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1257831356895                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              670.573520                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1782393910500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     62635560000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     30737512000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     30725132000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  237693960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  129694125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  237746880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  129723000                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                1570966800                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                383233680                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           122515155360                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            61441070355                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1071557085750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1257834900030                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.575404                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1782427454500                       # Time in different power states
+system.physmem_1.actBackEnergy            61443954270                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1071554556000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1257835335990                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.575636                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1782423204750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     62635560000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30691601750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30695851500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17943789                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          15652252                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                17943792                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          15652255                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            367731                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11526734                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5853564                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups             11526736                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5853565                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             50.782503                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                  912127                       # Number of times the RAS was used to get a target.
@@ -357,98 +357,98 @@ system.cpu.itb.data_accesses                        0                       # DT
 system.cpu.numCycles                        154312476                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29589684                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       78040473                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17943789                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6765691                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     115537778                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.icacheStallCycles           29589797                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       78040481                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17943792                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6765692                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     115536731                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                 1228012                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.TlbCycles                       1868                       # Number of cycles fetch has spent waiting for tlb
 system.cpu.fetch.MiscStallCycles                28793                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles       1263154                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles       470523                       # Number of stall cycles due to pending quiesce instructions
 system.cpu.fetch.IcacheWaitRetryStallCycles          558                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8990852                       # Number of cache lines fetched
+system.cpu.fetch.CacheLines                   8990853                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                270749                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          147506364                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.529065                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.785295                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples          147505430                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.529069                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.785300                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                132982346     90.15%     90.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                132981412     90.15%     90.15% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::1                   927735      0.63%     90.78% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::2                  1956667      1.33%     92.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   905254      0.61%     92.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2772061      1.88%     94.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   613974      0.42%     95.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   905252      0.61%     92.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2772062      1.88%     94.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   613973      0.42%     95.02% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::6                   725766      0.49%     95.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1009556      0.68%     96.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  5613005      3.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1009557      0.68%     96.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  5613006      3.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            147506364                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total            147505430                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.branchRate                  0.116282                       # Number of branch fetches per cycle
 system.cpu.fetch.rate                        0.505730                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 23997501                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             111590886                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                   9436404                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1909016                       # Number of cycles decode is unblocking
+system.cpu.decode.IdleCycles                 23997616                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             111589834                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                   9436408                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1909015                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                 572556                       # Number of cycles decode is squashing
 system.cpu.decode.BranchResolved               581578                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                 41802                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               68051611                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts               68051619                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                132447                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                 572556                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 24921357                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                78408678                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       21682628                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  10334897                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              11586246                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               65629261                       # Number of instructions processed by rename
+system.cpu.rename.IdleCycles                 24921470                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                78409233                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       21681516                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  10334902                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              11585751                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               65629269                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                204540                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2094496                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 230878                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                7314004                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            43742271                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              79592757                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         79412100                       # Number of integer rename lookups
+system.cpu.rename.IQFullEvents                2094492                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 230558                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                7313834                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            43742274                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              79592762                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         79412105                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups            168205                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              38181578                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  5560685                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                  5560688                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts            1689598                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts         239417                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13566674                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                  13566650                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads             10375081                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores             6952014                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads           1510108                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores          1095838                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58467931                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2138048                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57495227                       # Number of instructions issued
+system.cpu.iq.iqInstsAdded                   58467936                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2138049                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57495232                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued             57340                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7623887                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined         7623893                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined      3407756                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1476848                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     147506364                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.389781                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.113625                       # Number of insts issued each cycle
+system.cpu.iq.iqSquashedNonSpecRemoved        1476849                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     147505430                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.389784                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.113628                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           123908569     84.00%     84.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10178941      6.90%     90.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             4283785      2.90%     93.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3020720      2.05%     95.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             3080791      2.09%     97.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1492273      1.01%     98.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1011784      0.69%     99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              404685      0.27%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              124816      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           123907632     84.00%     84.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10178942      6.90%     90.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             4283791      2.90%     93.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3020718      2.05%     95.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             3080788      2.09%     97.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1492274      1.01%     98.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1011781      0.69%     99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              404686      0.27%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              124818      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       147506364                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       147505430                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  210138     18.65%     18.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  210139     18.65%     18.65% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     18.65% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.65% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.65% # attempts to use FU when none available
@@ -477,12 +477,12 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.65% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.65% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.65% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 541379     48.04%     66.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                375311     33.31%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 541380     48.04%     66.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                375310     33.31%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7282      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39050505     67.92%     67.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39050510     67.92%     67.93% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                61871      0.11%     68.04% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.04% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd               38553      0.07%     68.11% # Type of FU issued
@@ -515,17 +515,17 @@ system.cpu.iq.FU_type_0::MemRead             10660993     18.54%     86.66% # Ty
 system.cpu.iq.FU_type_0::MemWrite             6723341     11.69%     98.35% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess             949046      1.65%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57495227                       # Type of FU issued
+system.cpu.iq.FU_type_0::total               57495232                       # Type of FU issued
 system.cpu.iq.rate                           0.372590                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1126828                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt                     1126829                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.019599                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          262968198                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          67912529                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55849103                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_reads          262967275                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          67912541                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55849108                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads              712787                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes             336322                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses       328951                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               58232052                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses               58232058                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                  382721                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads           635480                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
@@ -536,57 +536,57 @@ system.cpu.iew.lsq.thread0.squashedStores       573763                       # N
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads        18204                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        460620                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked        460617                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                 572556                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                74664170                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1189821                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64295080                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewBlockCycles                74664181                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1190404                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            64295088                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts            139940                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts              10375081                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts              6952014                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1890560                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  43853                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                943025                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewDispNonSpecInsts            1890561                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  43857                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                943603                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents          19413                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect         177030                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect       409389                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts               586419                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56909008                       # Number of executed instructions
+system.cpu.iew.iewExecutedInsts              56909013                       # Number of executed instructions
 system.cpu.iew.iewExecLoadInsts              10319700                       # Number of load instructions executed
 system.cpu.iew.iewExecSquashedInsts            586218                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3689101                       # number of nop insts executed
+system.cpu.iew.exec_nop                       3689103                       # number of nop insts executed
 system.cpu.iew.exec_refs                     16987647                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8974026                       # Number of branches executed
+system.cpu.iew.exec_branches                  8974028                       # Number of branches executed
 system.cpu.iew.exec_stores                    6667947                       # Number of stores executed
 system.cpu.iew.exec_rate                     0.368791                       # Inst execution rate
-system.cpu.iew.wb_sent                       56315336                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56178054                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  28756989                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  39942344                       # num instructions consuming a value
+system.cpu.iew.wb_sent                       56315341                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56178059                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  28756993                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  39942343                       # num instructions consuming a value
 system.cpu.iew.wb_rate                       0.364054                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.719962                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         8005033                       # The number of squashed insts skipped by commit
+system.cpu.iew.wb_fanout                     0.719963                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         8005041                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls          661200                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts            537292                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    146103821                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.384473                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.286210                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples    146102886                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.384475                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.286214                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    126321778     86.46%     86.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7855301      5.38%     91.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4275066      2.93%     94.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2236699      1.53%     96.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1745226      1.19%     97.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       615725      0.42%     97.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       478401      0.33%     98.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       477554      0.33%     98.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2098071      1.44%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    126320849     86.46%     86.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7855297      5.38%     91.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4275062      2.93%     94.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2236701      1.53%     96.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1745224      1.19%     97.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       615726      0.42%     97.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       478400      0.33%     98.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       477555      0.33%     98.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2098072      1.44%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    146103821                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    146102886                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             56172911                       # Number of instructions committed
 system.cpu.commit.committedOps               56172911                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -632,11 +632,11 @@ system.cpu.commit.op_class_0::MemWrite        6384206     11.37%     98.31% # Cl
 system.cpu.commit.op_class_0::IprAccess        949045      1.69%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          56172911                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               2098071                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    207934044                       # The number of ROB reads
-system.cpu.rob.rob_writes                   129754094                       # The number of ROB writes
-system.cpu.timesIdled                          581359                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         6806112                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               2098072                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    207933116                       # The number of ROB reads
+system.cpu.rob.rob_writes                   129754111                       # The number of ROB writes
+system.cpu.timesIdled                          581360                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6807046                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.quiesceCycles                   3597208249                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu.committedInsts                    52982087                       # Number of Instructions Simulated
 system.cpu.committedOps                      52982087                       # Number of Ops (including micro ops) Simulated
@@ -644,8 +644,8 @@ system.cpu.cpi                               2.912541                       # CP
 system.cpu.cpi_total                         2.912541                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.343343                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.343343                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74569026                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40527111                       # number of integer regfile writes
+system.cpu.int_regfile_reads                 74569031                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40527114                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                    166982                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                   167538                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                 1985520                       # number of misc regfile reads
@@ -690,18 +690,18 @@ system.cpu.dcache.demand_misses::cpu.data      3754990                       # n
 system.cpu.dcache.demand_misses::total        3754990                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      3754990                       # number of overall misses
 system.cpu.dcache.overall_misses::total       3754990                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  57215692000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  57215692000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 116805325608                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 116805325608                       # number of WriteReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  57215969500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  57215969500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 116801916611                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 116801916611                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    447608000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total    447608000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       892500                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       892500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 174021017608                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 174021017608                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 174021017608                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 174021017608                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 174017886111                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 174017886111                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 174017886111                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 174017886111                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data      9036240                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total      9036240                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6147794                       # number of WriteReq accesses(hits+misses)
@@ -726,23 +726,23 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.247299
 system.cpu.dcache.demand_miss_rate::total     0.247299                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.247299                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.247299                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31831.802822                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 31831.802822                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59669.079344                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59669.079344                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31831.957208                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 31831.957208                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59667.337885                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59667.337885                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19251.956989                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19251.956989                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30775.862069                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30775.862069                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.936364                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46343.936364                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.936364                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46343.936364                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      7142845                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.102408                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46343.102408                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.102408                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46343.102408                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      7142391                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets         5288                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            134029                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            134027                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              28                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    53.293280                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    53.290688                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   188.857143                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -776,24 +776,24 @@ system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9598
 system.cpu.dcache.WriteReq_mshr_uncacheable::total         9598                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16528                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        16528                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  44560858000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  44560858000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18438060220                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  18438060220                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  44560579000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  44560579000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18438109720                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  18438109720                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    229318500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    229318500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       863500                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       863500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  62998918220                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  62998918220                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  62998918220                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  62998918220                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1529906000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1529906000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  62998688720                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  62998688720                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  62998688720                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  62998688720                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1529006000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1529006000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2154205500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2154205500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3684111500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3684111500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3683211500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3683211500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.121050                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.121050                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047283                       # mshr miss rate for WriteReq accesses
@@ -806,30 +806,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091183
 system.cpu.dcache.demand_mshr_miss_rate::total     0.091183                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091183                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.091183                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40738.264433                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40738.264433                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63428.819873                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63428.819873                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40738.009367                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40738.009367                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63428.990158                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63428.990158                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12727.895876                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12727.895876                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29775.862069                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29775.862069                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45502.287591                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45502.287591                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45502.287591                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45502.287591                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220765.656566                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220765.656566                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45502.121830                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45502.121830                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45502.121830                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45502.121830                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220635.786436                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220635.786436                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224443.165243                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224443.165243                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222901.228219                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222901.228219                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222846.775169                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222846.775169                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1036098                       # number of replacements
+system.cpu.icache.tags.replacements           1036100                       # number of replacements
 system.cpu.icache.tags.tagsinuse           507.835115                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7900594                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1036606                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.621598                       # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs             7900592                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1036608                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.621581                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       42318910500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   507.835115                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.991865                       # Average percentage of cache occupancy
@@ -839,44 +839,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           72
 system.cpu.icache.tags.age_task_id_blocks_1024::1           82                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          354                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          10027828                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         10027828                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7900595                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7900595                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7900595                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7900595                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7900595                       # number of overall hits
-system.cpu.icache.overall_hits::total         7900595                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1090254                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1090254                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1090254                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1090254                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1090254                       # number of overall misses
-system.cpu.icache.overall_misses::total       1090254                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16373491482                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16373491482                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16373491482                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16373491482                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16373491482                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16373491482                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8990849                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8990849                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8990849                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8990849                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8990849                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8990849                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          10027831                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         10027831                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7900593                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7900593                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7900593                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7900593                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7900593                       # number of overall hits
+system.cpu.icache.overall_hits::total         7900593                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1090257                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1090257                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1090257                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1090257                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1090257                       # number of overall misses
+system.cpu.icache.overall_misses::total       1090257                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16373914482                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16373914482                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16373914482                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16373914482                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16373914482                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16373914482                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8990850                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8990850                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8990850                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8990850                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8990850                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8990850                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121263                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.121263                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.121263                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.121263                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.121263                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.121263                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.052199                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15018.052199                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.052199                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15018.052199                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.052199                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15018.052199                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.398856                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15018.398856                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.398856                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15018.398856                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.398856                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15018.398856                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs        11165                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs               304                       # number of cycles access was blocked
@@ -885,48 +885,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs    36.726974
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1036098                       # number of writebacks
-system.cpu.icache.writebacks::total           1036098                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53275                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        53275                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        53275                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        53275                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        53275                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        53275                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1036979                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1036979                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1036979                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1036979                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1036979                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1036979                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14441674990                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  14441674990                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14441674990                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  14441674990                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14441674990                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  14441674990                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks      1036100                       # number of writebacks
+system.cpu.icache.writebacks::total           1036100                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53276                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        53276                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        53276                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        53276                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        53276                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        53276                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1036981                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1036981                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1036981                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1036981                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1036981                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1036981                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14441953990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  14441953990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14441953990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  14441953990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14441953990                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  14441953990                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115337                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115337                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115337                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.115337                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115337                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.115337                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13926.680280                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13926.680280                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13926.680280                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13926.680280                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13926.680280                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13926.680280                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13926.922470                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13926.922470                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13926.922470                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13926.922470                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13926.922470                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13926.922470                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           338547                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65279.196063                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4167773                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        65279.195987                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4167777                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           403714                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.323578                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.323588                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle       9186443000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53290.316378                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5240.255410                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6748.624275                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 53290.316261                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5240.255495                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6748.624231                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.813146                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.079960                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.102976                       # Average percentage of cache occupancy
@@ -938,28 +938,28 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3334
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2423                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55435                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         39707239                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        39707239                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses         39707271                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        39707271                       # Number of data accesses
 system.cpu.l2cache.WritebackDirty_hits::writebacks       841132                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       841132                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1035547                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1035547                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1035549                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1035549                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           29                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           29                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           22                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total           22                       # number of SCUpgradeReq hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data       185951                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total       185951                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1021689                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1021689                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1021691                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1021691                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data       827089                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total       827089                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      1021689                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      1021691                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data      1013040                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2034729                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      1021689                       # number of overall hits
+system.cpu.l2cache.demand_hits::total         2034731                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      1021691                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data      1013040                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2034729                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2034731                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data          101                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total          101                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            7                       # number of SCUpgradeReq misses
@@ -980,38 +980,38 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       815500
 system.cpu.l2cache.UpgradeReq_miss_latency::total       815500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       243500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       243500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16101364500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16101364500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2016473000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2016473000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  34005457500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  34005457500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2016473000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  50106822000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  52123295000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2016473000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  50106822000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  52123295000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16101413500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16101413500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2016727500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2016727500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  34005178500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  34005178500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   2016727500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  50106592000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  52123319500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   2016727500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  50106592000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  52123319500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       841132                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       841132                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1035547                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1035547                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1035549                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1035549                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data          130                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total          130                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           29                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total           29                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       301462                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       301462                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1036663                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1036663                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1036665                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1036665                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1100949                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total      1100949                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1036663                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      1036665                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data      1402411                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2439074                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1036663                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2439076                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1036665                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      1402411                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2439074                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2439076                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.776923                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.776923                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.241379                       # miss rate for SCUpgradeReq accesses
@@ -1032,18 +1032,18 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  8074.257426
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  8074.257426                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 34785.714286                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 34785.714286                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139392.477773                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139392.477773                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134664.952584                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134664.952584                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124170.954137                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124170.954137                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134664.952584                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128686.579124                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 128907.974626                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134664.952584                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128686.579124                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 128907.974626                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139392.901975                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139392.901975                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134681.948711                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134681.948711                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 124169.935368                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 124169.935368                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134681.948711                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128685.988427                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 128908.035217                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134681.948711                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128685.988427                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 128908.035217                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1086,24 +1086,24 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      7246500
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      7246500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       500000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       500000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14946254500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14946254500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1866612000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1866612000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31277372000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31277372000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1866612000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46223626500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  48090238500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1866612000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46223626500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  48090238500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1443206500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1443206500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14946303500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14946303500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1866866500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1866866500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31277093000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31277093000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1866866500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46223396500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  48090263000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1866866500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46223396500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  48090263000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1442306500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1442306500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2043789000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2043789000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3486995500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3486995500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3486095500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3486095500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.776923                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.776923                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.241379                       # mshr miss rate for SCUpgradeReq accesses
@@ -1124,72 +1124,72 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71747.524752
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71747.524752                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71428.571429                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71428.571429                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129392.477773                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.477773                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124665.197355                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124665.197355                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114209.347842                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114209.347842                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124665.197355                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118713.582932                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118933.973300                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124665.197355                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118713.582932                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118933.973300                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208254.906205                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208254.906205                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129392.901975                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.901975                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124682.194617                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124682.194617                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114208.329073                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114208.329073                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124682.194617                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118712.992236                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118934.033892                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124682.194617                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118712.992236                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118934.033892                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208125.036075                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208125.036075                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212939.049802                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212939.049802                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210975.042352                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210975.042352                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210920.589303                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210920.589303                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4877464                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2438379                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      4877468                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2438381                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2185                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1198                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1198                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq           6930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2144933                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2144935                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9598                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9598                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       958726                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1035547                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1035549                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict       821965                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq          130                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq           29                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp          159                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       301462                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       301462                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1036979                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1036981                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq      1101122                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::BadAddressError           81                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3109189                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3109195                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4238791                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7347980                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    132621440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7347986                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    132621696                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143635700                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          276257140                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          276257396                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                      422449                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2878054                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      2878056                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.001305                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.036107                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2874297     99.87%     99.87% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2874299     99.87%     99.87% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1               3757      0.13%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2878054                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4329025000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2878056                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4329029000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       291883                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1556715501                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1556718501                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2115441305                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2115441804                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1208,40 +1208,34 @@ system.iobus.trans_dist::ReadResp                7103                       # Tr
 system.iobus.trans_dist::WriteReq               51150                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              51150                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5052                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total        33056                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  116506                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20208                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total        44148                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2705756                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy              5360000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               444000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               826000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1255,16 +1249,10 @@ system.iobus.reqLayer24.occupancy             2178000                       # La
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy             5944500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              219000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               88000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               88000                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           215036503                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              132500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           215036503                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               30500                       # Layer occupancy (ticks)
-system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23458000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
@@ -1408,11 +1396,11 @@ system.membus.snoop_fanout::max_value               1                       # Re
 system.membus.snoop_fanout::total              842165                       # Request fanout histogram
 system.membus.reqLayer0.occupancy            28939500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1314315898                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1314314398                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy              106000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2139099889                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2139101639                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy           69817453                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
@@ -1460,10 +1448,10 @@ system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # nu
 system.cpu.kern.ipl_good::22                     1880      1.27%     50.68% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73297     49.32%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                148605                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1818035067000     96.92%     96.92% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1818035845500     96.92%     96.92% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::21                64907500      0.00%     96.93% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::22               561478000      0.03%     96.96% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             57098083500      3.04%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             57097305000      3.04%    100.00% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::total         1875759536000                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
index 455709c02..2c979b67f 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
index df18f1206..a2fe4ebe1 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/work/gem5/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/work/gem5/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -26,9 +26,10 @@ mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/work/gem5/dist/binaries/ts_osfpal
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -103,6 +104,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -119,6 +121,7 @@ system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
@@ -143,6 +146,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -159,6 +163,7 @@ system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
@@ -204,7 +209,7 @@ dtb=system.cpu1.dtb
 eventq_index=0
 function_trace=false
 function_trace_start=0
-interrupts=Null
+interrupts=
 isa=system.cpu1.isa
 itb=system.cpu1.itb
 max_insts_all_threads=0
@@ -283,7 +288,7 @@ iewToCommitDelay=1
 iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
-interrupts=Null
+interrupts=
 isa=system.cpu2.isa
 issueToExecuteDelay=1
 issueWidth=8
@@ -697,7 +702,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -720,7 +725,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -743,10 +748,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.tsunami.pciconfig.pio
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
@@ -755,6 +759,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
@@ -771,7 +776,8 @@ system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
-cpu_side=system.iobus.master[29]
+writeback_clean=false
+cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[2]
 
 [system.iocache.tags]
@@ -790,6 +796,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -806,6 +813,7 @@ system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
@@ -941,7 +949,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -954,12 +962,13 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_latency=0
 frontend_latency=1
 response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
 snoop_response_latency=1
 system=system
 use_default_range=false
@@ -967,9 +976,16 @@ width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
 
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
 [system.tsunami]
 type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -1082,12 +1098,12 @@ dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
 hardware_address=00:90:00:00:00:01
+host=system.tsunami.pchip
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 rss=false
 rx_delay=1000000
 rx_fifo_size=524288
@@ -1097,9 +1113,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.master[28]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[27]
+pio=system.iobus.master[26]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1532,14 +1547,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
 eventq_index=0
+host=system.tsunami.pchip
 io_shift=0
 pci_bus=0
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 system=system
-config=system.iobus.master[26]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[25]
 
@@ -1559,25 +1573,20 @@ pio=system.iobus.master[22]
 [system.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=system.clk_domain
+conf_base=8804649402368
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
+pci_dma_base=0
+pci_mem_base=8796093022208
+pci_pio_base=8804615847936
 pio_addr=8802535473152
 pio_latency=100000
+platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.master[1]
 
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
 [system.tsunami.uart]
 type=Uart8250
 clk_domain=system.clk_domain
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
index 1b889d7a1..52d4acaec 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
@@ -43,11 +43,3 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11394, Bank: 3
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
index 930df34c1..001ba9e0a 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 14 2015 20:54:01
-gem5 started Sep 14 2015 20:54:31
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
+gem5 compiled Dec  4 2015 10:28:58
+gem5 started Dec  4 2015 10:29:24
+gem5 executing on e104799-lin, pid 21387
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
 
 Global frequency set at 1000000000000 ticks per second
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index 771db86aa..190a0b7d0 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.843590                       # Nu
 sim_ticks                                1843589966000                       # Number of ticks simulated
 final_tick                               1843589966000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 220463                       # Simulator instruction rate (inst/s)
-host_op_rate                                   220463                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5656183181                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 378132                       # Number of bytes of host memory used
-host_seconds                                   325.94                       # Real time elapsed on the host
+host_inst_rate                                 221527                       # Simulator instruction rate (inst/s)
+host_op_rate                                   221527                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5683484333                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 334252                       # Number of bytes of host memory used
+host_seconds                                   324.38                       # Real time elapsed on the host
 sim_insts                                    71858146                       # Number of instructions simulated
 sim_ops                                      71858146                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1366,40 +1366,34 @@ system.iobus.trans_dist::ReadResp                7317                       # Tr
 system.iobus.trans_dist::WriteReq               51364                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              51364                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5196                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          756                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18256                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total        33912                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  117362                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20784                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          952                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9128                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total        45584                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2707192                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy              2564500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               116500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               118500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy               55500                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
@@ -1407,10 +1401,8 @@ system.iobus.reqLayer23.occupancy             6287500                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy             2121000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy                2000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy            84230549                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer27.occupancy            84230549                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy             8820000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            16458000                       # Layer occupancy (ticks)
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal
index 8a879f578..cbce606f3 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 6 cycles, load miss latency 32 cycles
+
4096K Bcache detected; load hit latency 6 cycles, load miss latency 30 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
index 59a4cd7b1..979ece788 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -1615,10 +1615,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -1645,7 +1644,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1809,12 +1808,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -1907,16 +1903,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1932,7 +1927,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -2095,13 +2090,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -2111,9 +2106,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -2155,7 +2149,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -2236,14 +2230,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -2260,7 +2253,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -2275,7 +2268,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -2398,17 +2391,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -2460,7 +2455,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -2475,7 +2470,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
index acab3733b..0dba6a71c 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 17:55:15
-gem5 executing on e104799-lin, pid 4773
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 12:40:05
+gem5 executing on e104799-lin, pid 5560
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2848948370000 because m5_exit instruction encountered
+Exiting @ tick 2848979128500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
index 127fb305c..a63afd969 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
@@ -1,161 +1,161 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.848948                       # Number of seconds simulated
-sim_ticks                                2848948370000                       # Number of ticks simulated
-final_tick                               2848948370000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.848979                       # Number of seconds simulated
+sim_ticks                                2848979128500                       # Number of ticks simulated
+final_tick                               2848979128500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 148563                       # Simulator instruction rate (inst/s)
-host_op_rate                                   179897                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3333146012                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 619788                       # Number of bytes of host memory used
-host_seconds                                   854.73                       # Real time elapsed on the host
-sim_insts                                   126981470                       # Number of instructions simulated
-sim_ops                                     153764073                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 154282                       # Simulator instruction rate (inst/s)
+host_op_rate                                   186830                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3456392917                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 618280                       # Number of bytes of host memory used
+host_seconds                                   824.26                       # Real time elapsed on the host
+sim_insts                                   127169330                       # Number of instructions simulated
+sim_ops                                     153997543                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         8960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         8448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1698304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1350900                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8536512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           207232                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           624212                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       339264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1698560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1348800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8516160                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           208256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           632788                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       357568                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12767176                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1698304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       207232                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1905536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8850048                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12772244                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1698560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       208256                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1906816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8849024                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8867612                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          140                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8866588                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker          132                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             26536                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             21631                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       133383                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           12                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3238                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              9774                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         5301                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             26540                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             21601                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       133065                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3254                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              9908                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         5587                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                200031                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          138282                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                200113                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          138266                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               142673                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3145                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               142657                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2965                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              596116                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              474175                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2996373                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           270                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               72740                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              219103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       119084                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              596200                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              473433                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2989197                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           225                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               73098                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              222110                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       125507                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4481364                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         596116                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          72740                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             668856                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3106426                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4483095                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         596200                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          73098                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             669298                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3106033                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6151                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3112591                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3106426                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3112198                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3106033                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2965                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             596116                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             480326                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2996373                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          270                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              72740                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             219117                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       119084                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             596200                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             479584                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2989197                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          225                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              73098                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             222124                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       125507                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7593956                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        200031                       # Number of read requests accepted
-system.physmem.writeReqs                       142673                       # Number of write requests accepted
-system.physmem.readBursts                      200031                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     142673                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12791872                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10112                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8880320                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12767176                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8867612                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      158                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                7595293                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        200113                       # Number of read requests accepted
+system.physmem.writeReqs                       142657                       # Number of write requests accepted
+system.physmem.readBursts                      200113                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     142657                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12798592                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8640                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8879168                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12772244                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8866588                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      135                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3895                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          68768                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12184                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12601                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               13506                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12929                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               15744                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12758                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12529                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12787                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11927                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12161                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11607                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10617                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11871                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12870                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              12074                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11708                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8731                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9199                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9827                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9174                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8354                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8906                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8822                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8920                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8409                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8625                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8250                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7761                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8553                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8825                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8501                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7898                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          69084                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12287                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12592                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               13485                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12796                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               15663                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12764                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12615                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12815                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11998                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12140                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11596                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10685                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11914                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12844                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12075                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11709                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8805                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9189                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9797                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9112                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8303                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8892                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8866                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8915                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8401                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8590                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8283                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7752                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8566                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8822                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8545                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7899                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2848947824000                       # Total gap between requests
+system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2848978583000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                     554                       # Read request sizes (log2)
+system.physmem.readPktSize::2                     557                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  199449                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  199528                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 138282                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     88254                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     61332                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     11783                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9470                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7796                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6317                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5163                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4597                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3794                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       675                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      220                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      170                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      157                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 138266                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     88817                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     60985                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     11790                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9494                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::5                      6286                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5183                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4625                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3738                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       641                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      202                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::13                      113                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
@@ -184,118 +184,118 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3400                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4553                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5946                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6521                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7799                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8851                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9259                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    11099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8721                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7476                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      555                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      328                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       86                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        92034                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      235.479584                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     133.901184                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     297.713631                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          49789     54.10%     54.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17966     19.52%     73.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6251      6.79%     80.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3568      3.88%     84.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2967      3.22%     87.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1449      1.57%     89.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          893      0.97%     90.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          932      1.01%     91.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8219      8.93%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          92034                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6844                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.203828                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      563.949624                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6843     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2866                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3333                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63                       61                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        92122                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      235.314387                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     133.718922                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     297.822907                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          49981     54.26%     54.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17852     19.38%     73.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6274      6.81%     80.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3559      3.86%     84.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2993      3.25%     87.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1358      1.47%     89.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          900      0.98%     90.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          994      1.08%     91.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8211      8.91%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          92122                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6829                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.283204                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      564.566486                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6828     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6844                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6844                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.273963                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.786776                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.867549                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5615     82.04%     82.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             464      6.78%     88.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             114      1.67%     90.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             150      2.19%     92.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              34      0.50%     93.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             131      1.91%     95.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              38      0.56%     95.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              19      0.28%     95.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              23      0.34%     96.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              24      0.35%     96.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               8      0.12%     96.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.12%     96.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             141      2.06%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               9      0.13%     99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              23      0.34%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               5      0.07%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.03%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.01%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.04%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.03%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             3      0.04%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.01%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.01%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            13      0.19%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6844                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5355833046                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9103451796                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    999365000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       26796.18                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6829                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6829                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.315859                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.777431                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.379766                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5626     82.38%     82.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             466      6.82%     89.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              97      1.42%     90.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             149      2.18%     92.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              29      0.42%     93.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             128      1.87%     95.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              35      0.51%     95.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              17      0.25%     95.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              25      0.37%     96.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              23      0.34%     96.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               7      0.10%     96.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.12%     96.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             138      2.02%     98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               8      0.12%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              26      0.38%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.09%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               4      0.06%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.01%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.01%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.01%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             2      0.03%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            14      0.21%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.04%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6829                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5270639949                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9020227449                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    999890000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       26356.10                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45546.18                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  45106.10                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           4.49                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.12                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        4.48                       # Average system read bandwidth in MiByte/s
@@ -304,41 +304,41 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.97                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     165962                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     80631                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.03                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  58.10                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8313144.36                       # Average gap between requests
-system.physmem.pageHitRate                      72.82                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  368376120                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  200998875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 819296400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                466125840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           186079052640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            85041435285                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1634767692000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1907742977160                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.631992                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2719447345615                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95132440000                       # Time in different power states
+system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.71                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     166028                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     80563                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.02                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  58.06                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8311633.41                       # Average gap between requests
+system.physmem.pageHitRate                      72.80                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  367945200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  200763750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 819124800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                465775920                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186081086880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            85063480605                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1634767041000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1907765218155                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.632478                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2719452348147                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95133480000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     34362631885                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     34391644853                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  327400920                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  178641375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 739705200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                433006560                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           186079052640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            83645503290                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1635992193750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1907395503735                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.510026                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2721498270016                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95132440000                       # Time in different power states
+system.physmem_1.actEnergy                  328497120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  179239500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 740688000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                433239840                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186081086880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            83753939520                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1635915761250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1907432452110                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.515676                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2721369982715                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95133480000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     32317496984                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     32475502785                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          832                       # Number of bytes read from this memory
@@ -364,15 +364,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               36425252                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         17807915                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          1745628                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            20690008                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               15088743                       # Number of BTB hits
+system.cpu0.branchPred.lookups               36411615                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         17748077                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          1698439                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            20740706                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               15063288                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.927681                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               11310340                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            873015                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            72.626689                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               11337600                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            822333                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -403,56 +403,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    73398                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               73398                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        47504                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        25894                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples        73398                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          73398    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        73398                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         7534                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12254.313778                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11412.538854                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  6583.009911                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767         7485     99.35%     99.35% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535           43      0.57%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839            5      0.07%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         7534                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                    73296                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               73296                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        47393                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        25903                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples        73296                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          73296    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        73296                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         7538                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12243.300610                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11373.544979                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  7165.218707                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767         7499     99.48%     99.48% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535           33      0.44%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839            4      0.05%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-425983            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         7538                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples    581987000                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0      581987000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total    581987000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5832     77.41%     77.41% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1702     22.59%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         7534                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        73398                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         5846     77.55%     77.55% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1692     22.45%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         7538                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        73296                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        73398                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7534                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        73296                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7538                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7534                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        80932                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7538                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        80834                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    24893776                       # DTB read hits
-system.cpu0.dtb.read_misses                     66568                       # DTB read misses
-system.cpu0.dtb.write_hits                   18528826                       # DTB write hits
-system.cpu0.dtb.write_misses                     6830                       # DTB write misses
+system.cpu0.dtb.read_hits                    24914388                       # DTB read hits
+system.cpu0.dtb.read_misses                     66763                       # DTB read misses
+system.cpu0.dtb.write_hits                   18539888                       # DTB write hits
+system.cpu0.dtb.write_misses                     6533                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3826                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1295                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2023                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3822                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1461                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2016                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      643                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                24960344                       # DTB read accesses
-system.cpu0.dtb.write_accesses               18535656                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      633                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                24981151                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18546421                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         43422602                       # DTB hits
-system.cpu0.dtb.misses                          73398                       # DTB misses
-system.cpu0.dtb.accesses                     43496000                       # DTB accesses
+system.cpu0.dtb.hits                         43454276                       # DTB hits
+system.cpu0.dtb.misses                          73296                       # DTB misses
+system.cpu0.dtb.accesses                     43527572                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -482,38 +483,37 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     4162                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                4162                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walks                     4166                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                4166                       # Table walker walks initiated with short descriptors
 system.cpu0.itb.walker.walksShortTerminationLevel::Level1          324                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3838                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         4162                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           4162    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         4162                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2674                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12829.655946                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 12107.498542                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  5222.854689                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         2410     90.13%     90.13% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          239      8.94%     99.07% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           23      0.86%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         3842                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         4166                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           4166    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         4166                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2675                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12725.794393                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 12032.430474                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5005.050560                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         2427     90.73%     90.73% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          233      8.71%     99.44% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           14      0.52%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2674                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2675                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples    581277500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0      581277500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total    581277500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2355     88.07%     88.07% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K         2356     88.07%     88.07% # Table walker page sizes translated
 system.cpu0.itb.walker.walkPageSizes::1M          319     11.93%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2674                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2675                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4162                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4162                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         4166                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         4166                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2674                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2674                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         6836                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    71465911                       # ITB inst hits
-system.cpu0.itb.inst_misses                      4162                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2675                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2675                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         6841                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    71495102                       # ITB inst hits
+system.cpu0.itb.inst_misses                      4166                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -522,131 +522,131 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2452                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2450                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     8217                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     8197                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                71470073                       # ITB inst accesses
-system.cpu0.itb.hits                         71465911                       # DTB hits
-system.cpu0.itb.misses                           4162                       # DTB misses
-system.cpu0.itb.accesses                     71470073                       # DTB accesses
-system.cpu0.numCycles                       248898522                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                71499268                       # ITB inst accesses
+system.cpu0.itb.hits                         71495102                       # DTB hits
+system.cpu0.itb.misses                           4166                       # DTB misses
+system.cpu0.itb.accesses                     71499268                       # DTB accesses
+system.cpu0.numCycles                       248928104                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  112980792                       # Number of instructions committed
-system.cpu0.committedOps                    136605971                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                      8918624                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     1867                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                  5449022663                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.203016                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.453923                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  113059938                       # Number of instructions committed
+system.cpu0.committedOps                    136701894                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                      8937139                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     1889                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                  5449058014                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.201736                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.454187                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1869                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      199912219                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                       48986303                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements           760179                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          497.990908                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           41826926                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           760691                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            54.985436                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    1892                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      199965513                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                       48962591                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements           758556                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          498.399366                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           41853464                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           759068                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            55.137964                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        600550000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.990908                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.972638                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.972638                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   498.399366                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.973436                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.973436                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          334                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          141                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         86810511                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        86810511                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     23283800                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       23283800                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     17355484                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      17355484                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       329213                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       329213                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374953                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       374953                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370901                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       370901                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     40639284                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        40639284                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     40968497                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       40968497                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       494585                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       494585                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       604894                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       604894                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       141990                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       141990                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21416                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        21416                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20509                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20509                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1099479                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1099479                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1241469                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1241469                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6989932000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6989932000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  12583639500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  12583639500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    328970000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    328970000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    535273000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    535273000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       491000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       491000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  19573571500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  19573571500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  19573571500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  19573571500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     23778385                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     23778385                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     17960378                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     17960378                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       471203                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       471203                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396369                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       396369                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391410                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       391410                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     41738763                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     41738763                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     42209966                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     42209966                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.020800                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.020800                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033679                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.033679                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.301335                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.301335                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054030                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054030                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052398                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052398                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026342                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.026342                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029412                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029412                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14132.923562                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14132.923562                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20803.048964                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20803.048964                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.945088                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.945088                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26099.419767                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26099.419767                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         86857605                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        86857605                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     23301250                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       23301250                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     17363998                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      17363998                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       329371                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       329371                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374920                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       374920                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370784                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       370784                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     40665248                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        40665248                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     40994619                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       40994619                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       492930                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       492930                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       604783                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       604783                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       142057                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       142057                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21393                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        21393                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20582                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20582                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1097713                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1097713                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1239770                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1239770                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6978123000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6978123000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  12569253000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  12569253000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    330022000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    330022000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    544680500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    544680500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       637500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       637500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  19547376000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  19547376000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  19547376000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  19547376000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     23794180                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     23794180                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     17968781                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17968781                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       471428                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       471428                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396313                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       396313                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391366                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       391366                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     41762961                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     41762961                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     42234389                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     42234389                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.020716                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.020716                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.033657                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.033657                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.301333                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.301333                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053980                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053980                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052590                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052590                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026284                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.026284                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029355                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029355                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14156.417747                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14156.417747                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20783.079220                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 20783.079220                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15426.634881                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15426.634881                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26463.924789                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26463.924789                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17802.587862                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 17802.587862                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15766.460137                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15766.460137                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17807.364949                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 17807.364949                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15766.937416                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15766.937416                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -655,149 +655,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       760179                       # number of writebacks
-system.cpu0.dcache.writebacks::total           760179                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        76321                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        76321                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       266412                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       266412                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14897                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14897                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data       342733                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       342733                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data       342733                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       342733                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       418264                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       418264                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       338482                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       338482                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       108425                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       108425                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6519                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6519                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20509                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20509                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       756746                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       756746                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       865171                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       865171                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32043                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32043                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28725                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28725                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60768                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60768                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5296846500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5296846500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7120379000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7120379000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1808041000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1808041000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    103110500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    103110500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    514774000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    514774000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       481000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       481000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12417225500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  12417225500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14225266500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  14225266500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6702942500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6702942500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5452503000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5452503000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12155445500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12155445500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017590                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017590                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018846                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018846                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.230103                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.230103                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016447                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016447                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052398                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052398                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018131                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.018131                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020497                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.020497                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12663.883337                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12663.883337                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21036.211674                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21036.211674                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16675.499193                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16675.499193                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15816.919773                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15816.919773                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25099.907358                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25099.907358                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       758556                       # number of writebacks
+system.cpu0.dcache.writebacks::total           758556                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        75954                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        75954                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       266286                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       266286                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        14845                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14845                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data       342240                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       342240                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data       342240                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       342240                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       416976                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       416976                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       338497                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       338497                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       108439                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       108439                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6548                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6548                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20582                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20582                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       755473                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       755473                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       863912                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       863912                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32047                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32047                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28724                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28724                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60771                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60771                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5288189500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5288189500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7115551000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7115551000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1805226500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1805226500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    104756500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104756500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    524110500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    524110500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       625500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       625500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12403740500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  12403740500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14208967000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  14208967000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6702515500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6702515500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5452693000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5452693000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12155208500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12155208500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017524                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017524                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018838                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018838                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.230022                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.230022                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016522                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016522                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052590                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052590                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018090                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.018090                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020455                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.020455                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12682.239505                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12682.239505                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21021.016434                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21021.016434                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16647.391621                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16647.391621                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15998.243739                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15998.243739                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25464.507822                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25464.507822                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16408.709792                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16408.709792                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16442.144385                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16442.144385                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209185.859626                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209185.859626                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189817.336815                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189817.336815                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200030.369602                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200030.369602                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16418.509331                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16418.509331                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16447.238839                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16447.238839                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209146.425562                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209146.425562                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189830.559811                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189830.559811                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200016.595086                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200016.595086                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          2044142                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.727750                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           69412626                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          2044654                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            33.948348                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          2041160                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.728196                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           69444830                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          2041672                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            34.013705                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       6975539000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.727750                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999468                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999468                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.728196                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999469                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999469                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          246                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           94                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        144959270                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       144959270                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     69412626                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       69412626                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     69412626                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        69412626                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     69412626                       # number of overall hits
-system.cpu0.icache.overall_hits::total       69412626                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      2044673                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2044673                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      2044673                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2044673                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      2044673                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2044673                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  20581599000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  20581599000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  20581599000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  20581599000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  20581599000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  20581599000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     71457299                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     71457299                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     71457299                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     71457299                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     71457299                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     71457299                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028614                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.028614                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028614                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.028614                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028614                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.028614                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10065.961159                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10065.961159                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10065.961159                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10065.961159                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10065.961159                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10065.961159                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        145014717                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       145014717                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     69444830                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       69444830                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     69444830                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        69444830                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     69444830                       # number of overall hits
+system.cpu0.icache.overall_hits::total       69444830                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      2041686                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2041686                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      2041686                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2041686                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      2041686                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2041686                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  20560339500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  20560339500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  20560339500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  20560339500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  20560339500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  20560339500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     71486516                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     71486516                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     71486516                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     71486516                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     71486516                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     71486516                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.028560                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.028560                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.028560                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.028560                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.028560                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.028560                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10070.275008                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10070.275008                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10070.275008                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10070.275008                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10070.275008                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10070.275008                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -806,335 +806,337 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      2044142                       # number of writebacks
-system.cpu0.icache.writebacks::total          2044142                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2044673                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      2044673                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      2044673                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      2044673                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      2044673                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      2044673                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      2041160                       # number of writebacks
+system.cpu0.icache.writebacks::total          2041160                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      2041686                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      2041686                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      2041686                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      2041686                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      2041686                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      2041686                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         3917                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         3917                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  19559263000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  19559263000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  19559263000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  19559263000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  19559263000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  19559263000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  19539497000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  19539497000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  19539497000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  19539497000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  19539497000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  19539497000                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    557356500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    557356500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    557356500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    557356500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028614                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028614                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028614                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.028614                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028614                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.028614                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9565.961403                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9565.961403                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9565.961403                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9565.961403                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9565.961403                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9565.961403                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028560                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028560                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028560                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.028560                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028560                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.028560                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9570.275253                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9570.275253                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9570.275253                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total  9570.275253                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9570.275253                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total  9570.275253                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1928199                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1928402                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit          177                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1926179                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1926371                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit          166                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       245070                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          307107                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16117.232598                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           4904017                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          323243                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           15.171301                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       244645                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          305884                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16117.392846                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           4898605                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          322066                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           15.209941                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14756.112164                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    60.295680                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.052107                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1300.772647                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.900642                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003680                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000003                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.079393                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.983718                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022          975                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15154                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          320                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          419                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          227                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          348                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4177                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         8282                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2255                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.059509                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000427                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.924927                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        93492271                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       93492271                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        89943                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         5714                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         95657                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks       509380                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total       509380                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      2249647                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      2249647                       # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       233063                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       233063                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1974299                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1974299                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       431967                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       431967                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        89943                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         5714                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1974299                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       665030                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        2734986                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        89943                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         5714                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1974299                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       665030                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       2734986                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          730                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          113                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          843                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        56685                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        56685                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20508                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        20508                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            1                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        48745                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        48745                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        70374                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        70374                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101234                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       101234                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          730                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker          113                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        70374                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       149979                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       221196                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          730                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker          113                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        70374                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       149979                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       221196                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     34979500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2794000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total     37773500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    198503500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    198503500                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     45129500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     45129500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       464999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       464999                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   3219724000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   3219724000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   4513596000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4513596000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3550732497                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3550732497                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     34979500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2794000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4513596000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   6770456497                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  11321825997                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     34979500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2794000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4513596000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   6770456497                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  11321825997                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        90673                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5827                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        96500                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks       509380                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total       509380                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      2249647                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      2249647                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        56685                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        56685                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20508                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        20508                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       281808                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       281808                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      2044673                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      2044673                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       533201                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       533201                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        90673                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5827                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      2044673                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       815009                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      2956182                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        90673                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5827                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      2044673                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       815009                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      2956182                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.008051                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.019392                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.008736                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14778.459491                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    60.434424                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.065090                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1278.433841                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.902006                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003689                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.078029                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.983728                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022          978                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           12                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15192                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           14                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          328                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          421                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          213                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          403                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4034                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         8338                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2319                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.059692                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000732                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.927246                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        93368748                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       93368748                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        90396                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         5742                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total         96138                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks       507659                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total       507659                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      2247535                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      2247535                       # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       233006                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       233006                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1971438                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      1971438                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       430811                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       430811                       # number of ReadSharedReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        90396                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker         5742                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      1971438                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data       663817                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        2731393                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        90396                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         5742                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1971438                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       663817                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       2731393                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          708                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           94                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total          802                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        57006                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        57006                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        20580                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        20580                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            2                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            2                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        48494                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        48494                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        70248                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total        70248                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       101145                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       101145                       # number of ReadSharedReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          708                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker           94                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        70248                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       149639                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       220689                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          708                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker           94                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        70248                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       149639                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       220689                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker     33565000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2328500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total     35893500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    209633000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    209633000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     49175500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     49175500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data       605000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total       605000                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   3197349498                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   3197349498                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   4517158000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   4517158000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3550453498                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3550453498                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker     33565000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2328500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   4517158000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   6747802996                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  11300854496                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker     33565000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2328500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   4517158000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   6747802996                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  11300854496                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        91104                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5836                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        96940                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks       507659                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total       507659                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      2247535                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      2247535                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        57006                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        57006                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20580                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        20580                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       281500                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       281500                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      2041686                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      2041686                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       531956                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       531956                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        91104                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5836                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      2041686                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       813456                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2952082                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        91104                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5836                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      2041686                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       813456                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2952082                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.007771                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.016107                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.008273                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.172972                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.172972                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034418                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034418                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.189861                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.189861                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.008051                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.019392                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034418                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.184021                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.074825                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.008051                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.019392                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034418                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.184021                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.074825                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47917.123288                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24725.663717                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44808.422301                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3501.869983                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3501.869983                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2200.580261                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2200.580261                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       464999                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       464999                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66052.395117                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66052.395117                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 64137.266604                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 64137.266604                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35074.505571                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35074.505571                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47917.123288                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24725.663717                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 64137.266604                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45142.696624                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 51184.587411                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47917.123288                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24725.663717                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 64137.266604                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45142.696624                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 51184.587411                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs           52                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.172270                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.172270                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.034407                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.034407                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.190138                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.190138                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.007771                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.016107                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.034407                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.183955                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.074757                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.007771                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.016107                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.034407                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.183955                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.074757                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47408.192090                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24771.276596                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44754.987531                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3677.384837                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3677.384837                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2389.480078                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2389.480078                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       302500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       302500                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65932.888564                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65932.888564                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 64303.012185                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 64303.012185                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35102.610094                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35102.610094                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47408.192090                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24771.276596                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 64303.012185                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45093.879243                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 51207.148956                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47408.192090                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24771.276596                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 64303.012185                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45093.879243                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 51207.148956                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs          136                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           26                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       238189                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          238189                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5772                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         5772                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           79                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           79                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          597                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          597                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           79                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         6369                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         6448                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           79                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         6369                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         6448                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          730                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          113                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          843                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264088                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       264088                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        56685                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        56685                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20508                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20508                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42973                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        42973                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        70295                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        70295                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       100637                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       100637                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          730                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          113                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        70295                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       143610                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       214748                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          730                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        70295                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       143610                       # number of overall MSHR misses
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+system.cpu0.l2cache.writebacks::writebacks       237808                       # number of writebacks
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+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        57006                       # number of UpgradeReq MSHR misses
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+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3917                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32043                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        35960                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28725                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28725                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32047                       # number of ReadReq MSHR uncacheable
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28724                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28724                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3917                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60768                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        64685                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     30599500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2116000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     32715500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21010993372                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21010993372                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1525168000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1525168000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    360192000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    360192000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       404999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       404999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2462258500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2462258500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   4089276000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   4089276000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2913504497                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2913504497                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     30599500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2116000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   4089276000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5375762997                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   9497754497                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     30599500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2116000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   4089276000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5375762997                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21010993372                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  30508747869                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60771                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        64688                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     29317000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1764500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     31081500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  20868982731                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  20868982731                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1541137000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1541137000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    368989000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    368989000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       533000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       533000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2455445500                       # number of ReadExReq MSHR miss cycles
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+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   4093922000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   4093922000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2912555498                       # number of ReadSharedReq MSHR miss cycles
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+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     29317000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   4093922000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5368000998                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   9493004498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     29317000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1764500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   4093922000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5368000998                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.overall_mshr_miss_latency::total  30361987229                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6446417500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6972437500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5236548000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5236548000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6445976000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6971996000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5236748000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5236748000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    526020000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11682965500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12208985500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008051                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.019392                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.008736                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11682724000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12208744000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007771                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.016107                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.008273                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -1143,127 +1145,127 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.152490                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.152490                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034380                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034380                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.188741                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.188741                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.008051                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.019392                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034380                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.176207                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.072644                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.008051                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.019392                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034380                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.176207                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.153762                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.153762                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.034373                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.034373                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.189068                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189068                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.007771                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.016107                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.034373                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.176850                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.072776                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.007771                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.016107                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.034373                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.176850                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.161978                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38808.422301                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79560.575914                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79560.575914                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26906.024521                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26906.024521                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17563.487420                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17563.487420                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       404999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       404999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57297.803272                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57297.803272                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58173.070631                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58173.070631                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28950.629460                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28950.629460                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58173.070631                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37433.068707                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44227.440987                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58173.070631                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37433.068707                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79560.575914                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63714.398811                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.162267                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38754.987531                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78993.821493                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 78993.821493                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 27034.645476                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 27034.645476                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17929.494655                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17929.494655                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       266500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       266500                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56728.710378                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56728.710378                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58335.427977                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58335.427977                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28958.752565                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28958.752565                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58335.427977                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37314.062269                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44186.186519                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58335.427977                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37314.062269                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78993.821493                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63382.754233                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201180.210967                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193894.257508                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182299.321149                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182299.321149                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201141.323681                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193860.415972                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182312.630553                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182312.630553                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192255.224789                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188745.234598                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192241.760050                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188732.747959                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests      5764816                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2905184                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        45291                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       351229                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       346765                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4464                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        143291                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2770361                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28725                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28725                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       748097                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      2249647                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict       247676                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       331668                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        87164                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42906                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       114222                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           14                       # Transaction distribution
+system.cpu0.toL2Bus.snoop_filter.tot_requests      5755750                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2900650                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        44518                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       351752                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       347037                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4715                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        143210                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2766468                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28724                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28724                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       746011                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      2247535                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       246533                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       331594                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        87502                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        43040                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       114569                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
 system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       300767                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       297392                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      2044673                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       607119                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3062                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      6104641                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2759378                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13827                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       189965                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          9067811                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    259587264                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    104603354                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        23308                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       362692                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         364576618                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1079592                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      4075784                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.104187                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.309067                       # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadExReq       300476                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       297107                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      2041686                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       606504                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3118                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      6096444                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2755852                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        13844                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       190303                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          9056443                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    259253824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    104429286                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        23344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       364416                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         364070870                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1078661                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      4070756                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.104237                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.309335                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           3655604     89.69%     89.69% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            415716     10.20%     99.89% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              4464      0.11%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           3651149     89.69%     89.69% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            414892     10.19%     99.88% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              4715      0.12%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       4075784                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    5775269994                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       4070756                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    5766247494                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    115824460                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    116466956                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   3073569625                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   3069095112                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1308368315                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1306223847                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy      8011477                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy      8018479                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     99320942                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     99225447                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups                3602112                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          2032281                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           210658                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2218631                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1453392                       # Number of BTB hits
+system.cpu1.branchPred.lookups                3641195                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2056746                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           213596                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2171070                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1462919                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            65.508505                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 748126                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             55361                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            67.382397                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 753966                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             56559                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1293,57 +1295,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    22520                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               22520                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18297                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4223                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples        22520                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          22520    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        22520                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         1840                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11809.782609                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11060.962968                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6551.399815                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         1685     91.58%     91.58% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          142      7.72%     99.29% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151            8      0.43%     99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.16%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::147456-163839            2      0.11%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         1840                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                    23130                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               23130                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        18836                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4294                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples        23130                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0          23130    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total        23130                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1830                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11932.513661                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11127.774947                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7404.648675                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         1668     91.15%     91.15% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          148      8.09%     99.23% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151            8      0.44%     99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.16%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::147456-163839            3      0.16%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         1830                       # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walksPending::samples  -1558893032                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0    -1558893032    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total  -1558893032                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1331     72.34%     72.34% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          509     27.66%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1840                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        22520                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K         1322     72.24%     72.24% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          508     27.76%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1830                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        23130                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        22520                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1840                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        23130                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1830                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1840                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        24360                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1830                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        24960                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3580818                       # DTB read hits
-system.cpu1.dtb.read_misses                     20748                       # DTB read misses
-system.cpu1.dtb.write_hits                    2975375                       # DTB write hits
-system.cpu1.dtb.write_misses                     1772                       # DTB write misses
+system.cpu1.dtb.read_hits                     3607725                       # DTB read hits
+system.cpu1.dtb.read_misses                     21408                       # DTB read misses
+system.cpu1.dtb.write_hits                    2997772                       # DTB write hits
+system.cpu1.dtb.write_misses                     1722                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1719                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       96                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   254                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1725                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      120                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   261                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      213                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3601566                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2977147                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 3629133                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2999494                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6556193                       # DTB hits
-system.cpu1.dtb.misses                          22520                       # DTB misses
-system.cpu1.dtb.accesses                      6578713                       # DTB accesses
+system.cpu1.dtb.hits                          6605497                       # DTB hits
+system.cpu1.dtb.misses                          23130                       # DTB misses
+system.cpu1.dtb.accesses                      6628627                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1373,43 +1375,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     1949                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                1949                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walks                     1936                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                1936                       # Table walker walks initiated with short descriptors
 system.cpu1.itb.walker.walksShortTerminationLevel::Level1          152                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1797                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         1949                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           1949    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         1949                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples          843                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11825.029656                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11322.074300                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  4470.335302                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          130     15.42%     15.42% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          558     66.19%     81.61% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          110     13.05%     94.66% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479           21      2.49%     97.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575            4      0.47%     97.63% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           10      1.19%     98.81% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767            2      0.24%     99.05% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         1784                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         1936                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           1936    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         1936                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          845                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11855.029586                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11358.377652                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  4391.934541                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          130     15.38%     15.38% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          557     65.92%     81.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383          112     13.25%     94.56% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479           22      2.60%     97.16% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575            3      0.36%     97.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           10      1.18%     98.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767            2      0.24%     98.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.12%     99.05% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::36864-40959            6      0.71%     99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-61439            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total          843                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::61440-65535            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total          845                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples  -1559948532                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0    -1559948532    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total  -1559948532                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          703     83.39%     83.39% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          140     16.61%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total          843                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K          705     83.43%     83.43% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          140     16.57%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          845                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1949                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1949                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1936                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1936                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          843                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total          843                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         2792                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                     6911047                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1949                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          845                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          845                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         2781                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                     6961088                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1936                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1418,130 +1421,130 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     907                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     909                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1031                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1058                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 6912996                       # ITB inst accesses
-system.cpu1.itb.hits                          6911047                       # DTB hits
-system.cpu1.itb.misses                           1949                       # DTB misses
-system.cpu1.itb.accesses                      6912996                       # DTB accesses
-system.cpu1.numCycles                        40490463                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 6963024                       # ITB inst accesses
+system.cpu1.itb.hits                          6961088                       # DTB hits
+system.cpu1.itb.misses                           1936                       # DTB misses
+system.cpu1.itb.accesses                      6963024                       # DTB accesses
+system.cpu1.numCycles                        40816703                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   14000678                       # Number of instructions committed
-system.cpu1.committedOps                     17158102                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                      1376852                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     2767                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                  5656768220                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.892036                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.345777                       # IPC: instructions per cycle
+system.cpu1.committedInsts                   14109392                       # Number of instructions committed
+system.cpu1.committedOps                     17295649                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                      1386756                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     2772                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                  5656506173                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.892875                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.345677                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2770                       # number of quiesce instructions executed
-system.cpu1.tickCycles                       27318087                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                       13172376                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements           156172                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          474.293359                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            6205519                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           156527                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            39.645039                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      91623607000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   474.293359                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.926354                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.926354                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          355                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          304                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.693359                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         13166537                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        13166537                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3257703                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3257703                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2730447                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2730447                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42566                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        42566                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70436                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        70436                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61872                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        61872                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5988150                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5988150                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      6030716                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        6030716                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       134164                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       134164                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       121295                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       121295                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24483                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        24483                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16576                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        16576                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23384                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23384                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       255459                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        255459                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       279942                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       279942                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2171565000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2171565000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4482158000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   4482158000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    319581000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    319581000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    639162500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    639162500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1395500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1395500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   6653723000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   6653723000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   6653723000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   6653723000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3391867                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3391867                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2851742                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2851742                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        67049                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        67049                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87012                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        87012                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85256                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        85256                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      6243609                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      6243609                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      6310658                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      6310658                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039555                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.039555                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.042534                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.042534                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.365151                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.365151                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.190502                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.190502                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274280                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274280                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040915                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.040915                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044360                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.044360                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16185.899347                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 16185.899347                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36952.537203                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 36952.537203                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19279.741795                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19279.741795                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27333.326206                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27333.326206                       # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce                    2772                       # number of quiesce instructions executed
+system.cpu1.tickCycles                       27557255                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                       13259448                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements           157096                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          475.586306                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            6254726                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           157444                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            39.726671                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      91652045000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   475.586306                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.928880                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.928880                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          348                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           65                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.679688                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         13266107                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        13266107                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3282974                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3282974                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2751908                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2751908                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42647                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        42647                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70687                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        70687                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        62029                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        62029                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      6034882                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         6034882                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      6077529                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        6077529                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       135266                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       135266                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       122118                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       122118                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24580                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        24580                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16502                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        16502                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23395                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23395                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       257384                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        257384                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       281964                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       281964                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2192537500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2192537500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4529521000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   4529521000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    318889500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    318889500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    637518000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    637518000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1095000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1095000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   6722058500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6722058500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   6722058500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6722058500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3418240                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3418240                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2874026                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2874026                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        67227                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        67227                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87189                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        87189                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85424                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        85424                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      6292266                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      6292266                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      6359493                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      6359493                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039572                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.039572                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.042490                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.042490                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.365627                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.365627                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.189267                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.189267                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.273869                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.273869                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.040905                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.040905                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044337                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.044337                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16209.080626                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16209.080626                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37091.346075                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 37091.346075                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19324.294025                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19324.294025                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27250.181663                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27250.181663                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26046.148306                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 26046.148306                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23768.219846                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 23768.219846                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26116.846813                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 26116.846813                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23840.130300                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 23840.130300                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1550,149 +1553,149 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       156173                       # number of writebacks
-system.cpu1.dcache.writebacks::total           156173                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        12677                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        12677                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        41645                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        41645                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11699                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11699                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        54322                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        54322                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        54322                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        54322                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       121487                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       121487                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        79650                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        79650                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23961                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        23961                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4877                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4877                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23384                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23384                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       201137                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       201137                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       225098                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       225098                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2976                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2976                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.writebacks::writebacks       157097                       # number of writebacks
+system.cpu1.dcache.writebacks::total           157097                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        12921                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        12921                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        42016                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total        42016                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11695                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11695                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        54937                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        54937                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        54937                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        54937                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       122345                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       122345                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        80102                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        80102                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        24073                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        24073                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4807                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4807                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23395                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23395                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       202447                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       202447                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       226520                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       226520                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2973                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2973                       # number of ReadReq MSHR uncacheable
 system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
 system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2311                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5287                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5287                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1847735500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1847735500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2733456500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2733456500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    448084000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    448084000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     87974000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     87974000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    615791500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    615791500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1382500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1382500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4581192000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4581192000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5029276000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   5029276000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    389353500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    389353500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    251607000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    251607000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    640960500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    640960500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035817                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035817                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027930                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027930                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.357366                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.357366                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056050                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056050                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274280                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274280                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032215                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.032215                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035669                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.035669                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15209.326924                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15209.326924                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34318.349027                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34318.349027                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18700.555069                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18700.555069                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18038.548288                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18038.548288                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26333.882142                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26333.882142                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5284                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5284                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1862537500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1862537500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2760870000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2760870000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    453287500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    453287500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     86939500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     86939500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    614134000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    614134000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1084000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1084000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4623407500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4623407500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5076695000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5076695000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    389226500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    389226500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    251720500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    251720500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    640947000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    640947000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035792                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035792                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027871                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027871                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.358085                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.358085                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055133                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.055133                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.273869                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.273869                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032174                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.032174                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035619                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035619                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15223.650333                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15223.650333                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34466.929665                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34466.929665                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18829.705479                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18829.705479                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18086.020387                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18086.020387                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26250.651849                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26250.651849                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22776.475735                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22776.475735                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22342.606331                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22342.606331                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130831.149194                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130831.149194                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108873.647772                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108873.647772                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121233.308114                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121233.308114                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22837.619229                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22837.619229                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22411.685502                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22411.685502                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130920.450723                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130920.450723                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108922.760710                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108922.760710                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121299.583649                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121299.583649                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           857356                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.135276                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            6052000                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           857868                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             7.054698                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements           864194                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.135415                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            6095160                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           864706                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             7.048824                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle      73316283000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.135276                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.135415                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974874                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.974874                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          464                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           47                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          460                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           51                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         14677604                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        14677604                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      6052000                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        6052000                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      6052000                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         6052000                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      6052000                       # number of overall hits
-system.cpu1.icache.overall_hits::total        6052000                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       857868                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       857868                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       857868                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        857868                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       857868                       # number of overall misses
-system.cpu1.icache.overall_misses::total       857868                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7591768500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   7591768500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   7591768500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   7591768500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   7591768500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   7591768500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      6909868                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      6909868                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      6909868                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      6909868                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      6909868                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      6909868                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.124151                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.124151                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.124151                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.124151                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.124151                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.124151                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8849.576508                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  8849.576508                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8849.576508                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  8849.576508                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8849.576508                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  8849.576508                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         14784438                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        14784438                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      6095160                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        6095160                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      6095160                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         6095160                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      6095160                       # number of overall hits
+system.cpu1.icache.overall_hits::total        6095160                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       864706                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       864706                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       864706                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        864706                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       864706                       # number of overall misses
+system.cpu1.icache.overall_misses::total       864706                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7648423000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   7648423000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   7648423000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   7648423000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   7648423000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   7648423000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      6959866                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      6959866                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      6959866                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      6959866                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      6959866                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      6959866                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.124242                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.124242                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.124242                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.124242                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.124242                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.124242                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8845.113831                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8845.113831                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8845.113831                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8845.113831                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8845.113831                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8845.113831                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1701,331 +1704,332 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       857356                       # number of writebacks
-system.cpu1.icache.writebacks::total           857356                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       857868                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       857868                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       857868                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       857868                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       857868                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       857868                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       864194                       # number of writebacks
+system.cpu1.icache.writebacks::total           864194                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       864706                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       864706                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       864706                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       864706                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       864706                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       864706                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          112                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          112                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7162834500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   7162834500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7162834500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   7162834500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7162834500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   7162834500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7216070000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   7216070000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7216070000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   7216070000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7216070000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   7216070000                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     15350500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     15350500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     15350500                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total     15350500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.124151                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.124151                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.124151                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.124151                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.124151                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.124151                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8349.576508                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8349.576508                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8349.576508                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8349.576508                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8349.576508                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8349.576508                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.124242                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.124242                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.124242                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.124242                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.124242                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.124242                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8345.113831                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8345.113831                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8345.113831                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8345.113831                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8345.113831                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8345.113831                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       119508                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       119564                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           49                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       119025                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       119084                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           52                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        48908                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           37772                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15172.719385                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1844058                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           52876                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           34.875142                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        48684                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           38075                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15173.951540                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1858742                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           53288                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           34.881061                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14738.461893                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    30.967636                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.078899                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   403.210957                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.899564                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001890                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14749.353983                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    37.286789                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     0.078849                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   387.231918                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.900229                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002276                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000005                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.024610                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.926069                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          917                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           85                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14102                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           47                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          870                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           53                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          316                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1682                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12104                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.055969                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005188                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.860718                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        34274864                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       34274864                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        23931                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2459                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total         26390                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks        94554                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total        94554                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks       900775                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total       900775                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        17922                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        17922                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       845092                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       845092                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        83494                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total        83494                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        23931                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2459                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       845092                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data       101416                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         972898                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        23931                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2459                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       845092                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data       101416                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        972898                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          683                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          243                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          926                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29302                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        29302                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23383                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        23383                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.023635                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.926145                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          919                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           92                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14202                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            5                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           50                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          864                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           18                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           18                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           56                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          337                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1786                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12079                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.056091                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005615                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.866821                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        34538889                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       34538889                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker        24515                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         2453                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total         26968                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks        95201                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total        95201                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks       907759                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total       907759                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        18142                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        18142                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       851797                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       851797                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        83849                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total        83849                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker        24515                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         2453                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst       851797                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data       101991                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         980756                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker        24515                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         2453                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       851797                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data       101991                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        980756                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          708                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          242                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          950                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        29444                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        29444                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23394                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        23394                       # number of SCUpgradeReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
 system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32429                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        32429                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        12776                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total        12776                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        66828                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        66828                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          683                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          243                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst        12776                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data        99257                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       112959                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          683                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          243                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst        12776                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data        99257                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       112959                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     15528000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4905000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     20433000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     65464500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total     65464500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     59174500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     59174500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1363000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1363000                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1719425500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1719425500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    735868000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    735868000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1599140998                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1599140998                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     15528000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4905000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    735868000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3318566498                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   4074867498                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     15528000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4905000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    735868000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3318566498                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   4074867498                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker        24614                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2702                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total        27316                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks        94554                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total        94554                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks       900775                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total       900775                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29302                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        29302                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23383                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23383                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32519                       # number of ReadExReq misses
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+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        12909                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total        12909                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        67373                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total        67373                       # number of ReadSharedReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          708                       # number of demand (read+write) misses
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+system.cpu1.l2cache.demand_misses::total       113751                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          708                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          242                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst        12909                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data        99892                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       113751                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker     15804500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      4851500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     20656000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     65469500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total     65469500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     59113000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     59113000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      1066999                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      1066999                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1736092499                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1736092499                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    738228000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    738228000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1614591996                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1614591996                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker     15804500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      4851500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    738228000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3350684495                       # number of demand (read+write) miss cycles
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+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker     15804500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      4851500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    738228000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3350684495                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   4109568495                       # number of overall miss cycles
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+system.cpu1.l2cache.ReadReq_accesses::total        27918                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks        95201                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total        95201                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       907759                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       907759                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        29444                       # number of UpgradeReq accesses(hits+misses)
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+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23394                       # number of SCUpgradeReq accesses(hits+misses)
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 system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50351                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        50351                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       857868                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       857868                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       150322                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       150322                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        24614                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2702                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       857868                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       200673                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      1085857                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker        24614                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2702                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       857868                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       200673                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      1085857                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.027748                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.089933                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.033900                       # miss rate for ReadReq accesses
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+system.cpu1.l2cache.ReadExReq_accesses::total        50661                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       864706                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       864706                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       151222                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       151222                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker        25223                       # number of demand (read+write) accesses
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+system.cpu1.l2cache.overall_accesses::cpu1.inst       864706                       # number of overall (read+write) accesses
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.028070                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.089796                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.034028                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.644059                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.644059                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.014893                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.014893                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.444566                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.444566                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.027748                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.089933                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.014893                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.494621                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.104028                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.027748                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.089933                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.014893                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.494621                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.104028                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22734.992679                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20185.185185                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22065.874730                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2234.130776                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2234.130776                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2530.663302                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2530.663302                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1363000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1363000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53021.230997                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53021.230997                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 57597.683156                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 57597.683156                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23929.206291                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23929.206291                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22734.992679                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20185.185185                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 57597.683156                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33434.080196                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 36073.863065                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22734.992679                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20185.185185                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 57597.683156                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33434.080196                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 36073.863065                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs           91                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.641894                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.641894                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.014929                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.014929                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.445524                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.445524                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.028070                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.089796                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.014929                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.494801                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.103929                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.028070                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.089796                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.014929                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.494801                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.103929                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22322.740113                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20047.520661                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21743.157895                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2223.526015                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2223.526015                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2526.844490                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2526.844490                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1066999                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1066999                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53387.019865                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53387.019865                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 57187.078782                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 57187.078782                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23964.971071                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23964.971071                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22322.740113                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20047.520661                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 57187.078782                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33543.071467                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 36127.757075                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22322.740113                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20047.520661                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 57187.078782                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33543.071467                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 36127.757075                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs           84                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               4                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               3                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs    22.750000                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           28                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        29006                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           29006                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          239                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total          239                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.writebacks::writebacks        29108                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           29108                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data          236                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total          236                       # number of ReadExReq MSHR hits
 system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            9                       # number of ReadCleanReq MSHR hits
 system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           41                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           41                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           35                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           35                       # number of ReadSharedReq MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            9                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data          280                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total          289                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data          271                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total          280                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            9                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data          280                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total          289                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          683                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          243                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          926                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        20213                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        20213                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29302                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29302                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23383                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23383                       # number of SCUpgradeReq MSHR misses
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+system.cpu1.l2cache.HardPFReq_mshr_misses::total        20082                       # number of HardPFReq MSHR misses
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+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29444                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23394                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23394                       # number of SCUpgradeReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        32190                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        32190                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        12767                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        12767                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        66787                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        66787                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          683                       # number of demand (read+write) MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          683                       # number of overall MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        12767                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data        98977                       # number of overall MSHR misses
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+system.cpu1.l2cache.demand_mshr_misses::cpu1.data        99621                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total       133553                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          112                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         2976                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3088                       # number of ReadReq MSHR uncacheable
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+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3085                       # number of ReadReq MSHR uncacheable
 system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2311                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2311                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          112                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5287                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5399                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     11430000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3447000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     14877000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    967332273                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    967332273                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    596044000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    596044000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    438887000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    438887000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1285000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1285000                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1502190000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1502190000                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    658879500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    658879500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1196481498                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1196481498                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     11430000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3447000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    658879500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2698671498                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3372427998                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     11430000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3447000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    658879500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2698671498                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    967332273                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4339760271                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5284                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5396                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker     11556500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3399500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     14956000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1023264430                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1023264430                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    603797000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    603797000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    437130500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    437130500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1000999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1000999                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1515754000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1515754000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    660362000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    660362000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1209005996                       # number of ReadSharedReq MSHR miss cycles
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+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker     11556500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    660362000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2724759996                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3400077996                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker     11556500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3399500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    660362000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2724759996                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1023264430                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4423342426                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14454500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    365478500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    379933000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    234145500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    234145500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    365375500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    379830000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    234264000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    234264000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     14454500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    599624000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    614078500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.027748                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.089933                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.033900                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    599639500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    614094000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.028070                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.089796                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.034028                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -2034,117 +2038,117 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.639312                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.639312                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.014882                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014882                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.444293                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.444293                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.027748                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.089933                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.014882                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.493225                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.103761                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.027748                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.089933                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.014882                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.493225                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.637236                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.637236                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.014918                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.014918                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.445292                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.445292                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.028070                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.089796                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.014918                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.493459                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.103673                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.028070                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.089796                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.014918                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.493459                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.122376                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16065.874730                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47856.937268                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47856.937268                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.410143                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.410143                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18769.490656                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18769.490656                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1285000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1285000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46666.356011                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46666.356011                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51608.012846                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51608.012846                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17914.886101                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17914.886101                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51608.012846                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27265.642503                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29931.907322                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51608.012846                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27265.642503                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47856.937268                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32658.506137                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.122021                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15743.157895                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50954.308834                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50954.308834                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20506.622741                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20506.622741                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18685.581773                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18685.581773                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1000999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1000999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46952.080042                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46952.080042                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51190.852713                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51190.852713                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17954.290237                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17954.290237                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51190.852713                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27351.261240                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29964.290400                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51190.852713                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27351.261240                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50954.308834                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33120.502168                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122808.635753                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123035.297927                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101317.827780                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101317.827780                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122897.914564                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123121.555916                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101369.104284                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101369.104284                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113414.790997                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113739.303575                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113482.115821                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113805.411416                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests      2131909                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1073389                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        18199                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       177399                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       176178                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1221                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq         33577                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      1078735                       # Transaction distribution
+system.cpu1.toL2Bus.snoop_filter.tot_requests      2148021                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests      1081444                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        18331                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       178235                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       177001                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1234                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq         34229                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      1087159                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteReq         2311                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::WriteResp         2311                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       124920                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean       900775                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict        97230                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        24545                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        71695                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41696                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        84990                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       125656                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       907759                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        98212                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        24432                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        72484                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41782                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        85083                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
 system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        57514                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        55014                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       857868                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       234653                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq           35                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2557119                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       745420                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6448                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        51357                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          3360344                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    108744896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25394242                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        98456                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total         134248402                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     381517                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1451505                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.140526                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.349944                       # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadExReq        57811                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        55294                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       864706                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       235840                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq           36                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      2577500                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       749010                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6415                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        52647                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          3385572                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    109611648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     25531190                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        10780                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       100892                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total         135254510                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     383471                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1462314                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.140260                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.349678                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0           1248752     86.03%     86.03% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            201532     13.88%     99.92% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              1221      0.08%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0           1258444     86.06%     86.06% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            202636     13.86%     99.92% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              1234      0.08%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1451505                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    2095009994                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1462314                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    2111082490                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     78651519                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     78627228                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   1287084271                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   1297343267                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    333125737                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    334901961                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      3746000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      3720499                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     26768449                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     27451445                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                31009                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31009                       # Transaction distribution
@@ -2152,6 +2156,7 @@ system.iobus.trans_dist::WriteReq               59424                       # Tr
 system.iobus.trans_dist::WriteResp              59424                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56618                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
@@ -2167,16 +2172,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       107932                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  180866                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71562                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
@@ -2192,27 +2195,26 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       162812                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2483988                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             51019501                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             51120500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               109500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                28500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               320500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                12500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                85000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               572500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                12500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy                84500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               21500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               571500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
@@ -2232,31 +2234,25 @@ system.iobus.reqLayer20.occupancy                9500                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6101000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6117000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              169500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            32846500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32834001                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           186337026                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              123500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186304797                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               32500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84732000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36449                       # number of replacements
-system.iocache.tags.tagsinuse               14.470000                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.469949                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36465                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         272418338000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.470000                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.904375                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.904375                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         272430408000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.469949                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.904372                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.904372                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2270,14 +2266,14 @@ system.iocache.demand_misses::realview.ide          243                       #
 system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          243                       # number of overall misses
 system.iocache.overall_misses::total              243                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31658876                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31658876                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4735531921                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4735531921                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31658876                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31658876                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31658876                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31658876                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     32247375                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32247375                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4733187651                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4733187651                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32247375                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32247375                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32247375                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32247375                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2294,19 +2290,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 130283.440329                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 130283.440329                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130729.127678                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130729.127678                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 130283.440329                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 130283.440329                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 130283.440329                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 130283.440329                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           628                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 132705.246914                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 132705.246914                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130664.411744                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130664.411744                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 132705.246914                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 132705.246914                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 132705.246914                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 132705.246914                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           621                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   73                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   79                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.602740                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.860759                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -2320,14 +2316,14 @@ system.iocache.demand_mshr_misses::realview.ide          243
 system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     19508876                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     19508876                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2924331921                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2924331921                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     19508876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     19508876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     19508876                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     19508876                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     20097375                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     20097375                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2921987651                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2921987651                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     20097375                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     20097375                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     20097375                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     20097375                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2336,576 +2332,577 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80283.440329                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 80283.440329                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80729.127678                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80729.127678                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 80283.440329                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 80283.440329                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 80283.440329                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 80283.440329                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82705.246914                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 82705.246914                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80664.411744                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80664.411744                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 82705.246914                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 82705.246914                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 82705.246914                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 82705.246914                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   131732                       # number of replacements
-system.l2c.tags.tagsinuse                63242.215263                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     477411                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   195803                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.438221                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   131701                       # number of replacements
+system.l2c.tags.tagsinuse                63232.493895                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     477114                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   195835                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.436306                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   13388.492550                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    80.863480                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.040287                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     9301.116819                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2921.908325                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33330.007466                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     8.315084                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1918.660878                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      548.645359                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1744.165016                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.204292                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001234                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.141924                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.044585                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.508576                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000127                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.029276                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.008372                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.026614                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.965000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        29065                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023           58                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        34948                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          132                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         4807                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        24126                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4           58                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          442                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         3276                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        31196                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.443497                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000885                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.533264                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                  6405394                       # Number of tag accesses
-system.l2c.tags.data_accesses                 6405394                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks       267195                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          267195                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data           33822                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            2200                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               36022                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data          2272                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           961                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total              3233                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data             4378                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             1264                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                 5642                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker          435                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker          108                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst        47657                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data        51900                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher        49884                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           81                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker           16                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst         9621                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data         5534                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher         3616                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           168852                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker           435                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker           108                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst               47657                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data               56278                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher        49884                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker            81                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker            16                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                9621                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                6798                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher         3616                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  174494                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker          435                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker          108                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst              47657                       # number of overall hits
-system.l2c.overall_hits::cpu0.data              56278                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher        49884                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker           81                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker           16                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst               9621                       # number of overall hits
-system.l2c.overall_hits::cpu1.data               6798                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher         3616                       # number of overall hits
-system.l2c.overall_hits::total                 174494                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         10312                       # number of UpgradeReq misses
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-system.l2c.UpgradeReq_misses::total             12693                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          744                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data         1293                       # number of SCUpgradeReq misses
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-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          140                       # number of ReadSharedReq misses
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+system.l2c.tags.occ_blocks::cpu0.dtb.walker    81.189305                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030804                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     9276.099032                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2886.907500                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33207.909394                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     5.955383                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1918.551839                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      583.845643                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1772.821532                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.205981                       # Average percentage of cache occupancy
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+system.l2c.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::2          486                       # Occupied blocks per task id
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-system.l2c.ReadSharedReq_accesses::cpu1.data         7134                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher         8917                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total       345081                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker          575                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker          109                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst           70295                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data           77625                       # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.inst           12767                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           16569                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher         8917                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              370390                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker          575                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker          109                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst          70295                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data          77625                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu1.dtb.walker           93                       # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu1.inst          12767                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          16569                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher         8917                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             370390                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.233652                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.519756                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.260556                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.246684                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.573647                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.386528                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.724203                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.866031                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.777075                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.243478                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.009174                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.322043                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.159528                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.129032                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.246417                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.224278                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.510689                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.243478                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.009174                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.129032                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::cpu1.data       0.589716                       # miss rate for demand accesses
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-system.l2c.demand_miss_rate::total           0.528891                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.243478                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.009174                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.322043                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.129032                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.246417                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.528891                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3150.649728                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2719.655607                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  3069.802253                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7596.774194                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2696.442382                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  4486.254296                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 147998.651705                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132013.339860                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 141357.273606                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker       137225                       # average ReadSharedReq miss latency
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+system.l2c.WritebackDirty_accesses::total       266916                       # number of WritebackDirty accesses(hits+misses)
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.525855                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.262248                       # miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.577343                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.398302                       # miss rate for SCUpgradeReq accesses
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+system.l2c.ReadSharedReq_miss_rate::total     0.511313                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.236984                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.011111                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::total           0.529604                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.236984                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.011111                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.113636                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.529604                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2926.858399                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2516.253555                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2848.688791                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5325.415677                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1831.757289                       # average SCUpgradeReq miss latency
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 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       133000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 130603.432282                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136986.600345                       # average ReadSharedReq miss latency
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-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 136166.666667                       # average ReadSharedReq miss latency
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-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 137372.812500                       # average ReadSharedReq miss latency
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-system.l2c.ReadSharedReq_avg_miss_latency::total 147415.072077                       # average ReadSharedReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 130603.432282                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136166.666667                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.data 132890.952820                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::total 146806.898747                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker       133000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 130603.432282                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 142916.920410                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136166.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 133067.863954                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 132890.952820                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167896.665158                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 146806.898747                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               305                       # number of cycles access was blocked
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+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        6                       # number of cycles access was blocked
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 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     50.833333                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              102076                       # number of writebacks
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-system.l2c.CleanEvict_mshr_misses::total         3577                       # number of CleanEvict MSHR misses
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+system.l2c.overall_mshr_miss_latency::cpu1.inst    385923000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1217137500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    891120899                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  26722582178                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5869618000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5869112000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     12102000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    311913500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   6637396500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4748092000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    194851500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4942943500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    311853000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6636830000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4748303000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    194971500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4943274500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    443763000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10617710000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10617415000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     12102000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    506765000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  11580340000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    506824500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  11580104500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.233652                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.519756                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.260556                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.246684                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.573647                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.386528                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.724203                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.866031                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.777075                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.243478                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.009174                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.321929                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.159528                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.129032                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.245868                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.224278                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.510645                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.243478                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.009174                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.321929                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.275002                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.129032                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.245868                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.589716                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.528851                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.243478                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.009174                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.321929                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.275002                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728040                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.129032                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.245868                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.589716                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.594482                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.528851                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75581.070597                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75191.096178                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75507.917750                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77408.602151                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76636.504254                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76918.507609                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137998.651705                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122013.339860                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 131357.273606                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker       127225                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.234595                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.525855                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.262248                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.271438                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.577343                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.398302                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.726137                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.861140                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.777106                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.236984                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.011111                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.322518                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.159360                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728463                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.113636                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.244574                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.226573                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.612677                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.511298                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.236984                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011111                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.322518                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.275371                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728463                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.113636                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.244574                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.590492                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.612677                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.529591                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.236984                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011111                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.322518                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.275371                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.728463                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.113636                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.244574                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.590492                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.612677                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.529591                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75618.001147                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75302.316132                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75557.902065                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77386.579572                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76685.185185                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76964.945523                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136555.256299                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121725.510327                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 130351.028349                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120620.592134                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126986.600345                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123187.639376                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127372.812500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137420.742603                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       127225                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120956.790669                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127460.264901                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       132600                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122321.077655                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129241.975309                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137039.470064                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120620.592134                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132916.920410                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123187.639376                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122890.952820                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 136811.953365                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       127225                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120956.790669                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132369.214537                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       132600                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122321.077655                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122955.601576                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 136364.055714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120620.592134                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132916.920410                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123187.639376                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122890.952820                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 136811.953365                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120956.790669                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132369.214537                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129                       # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122321.077655                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122955.601576                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 136364.055714                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183179.415161                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183140.762006                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104915.405314                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169993.507491                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165294.760661                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84314.798788                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159264.837608                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105001.010101                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169974.645290                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165307.861022                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84366.724362                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159280.634767                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174725.348868                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174711.869148                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95905.563967                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 165242.219717                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95971.312251                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 165238.859320                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               39045                       # Transaction distribution
-system.membus.trans_dist::ReadResp             215502                       # Transaction distribution
-system.membus.trans_dist::WriteReq              31036                       # Transaction distribution
-system.membus.trans_dist::WriteResp             31036                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       138282                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            17700                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            74095                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40637                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14846                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             40045                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19551                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        176457                       # Transaction distribution
+system.membus.trans_dist::ReadReq               39046                       # Transaction distribution
+system.membus.trans_dist::ReadResp             215465                       # Transaction distribution
+system.membus.trans_dist::WriteReq              31035                       # Transaction distribution
+system.membus.trans_dist::WriteResp             31035                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       138266                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            17702                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            74461                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40765                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           15160                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             40157                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            19667                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        176419                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107932                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           42                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14226                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       678987                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       801187                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14220                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       679941                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       802135                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108925                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108925                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 910112                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 911060                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162812                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1344                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28452                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19316644                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     19509252                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19320688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19513284                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                21827396                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           120950                       # Total snoops (count)
-system.membus.snoop_fanout::samples            593773                       # Request fanout histogram
+system.membus.pkt_size::total                21831428                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           121126                       # Total snoops (count)
+system.membus.snoop_fanout::samples            594326                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  593773    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  594326    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              593773                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            91220498                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              594326                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            91340500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               23828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            12309500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            12352499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          1009592824                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1009821404                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1175000125                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1176071579                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64118281                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64144132                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2948,52 +2945,52 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      1045381                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       564426                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       153843                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          20977                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        20003                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops          974                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              39048                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            502086                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             31036                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            31036                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       405496                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          105907                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          110001                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         43870                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         153871                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests      1045963                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       564632                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       154673                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          20991                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        19997                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops          994                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              39049                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            502457                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             31035                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            31035                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       405200                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          105572                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          110705                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         43954                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         154659                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
 system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            51160                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           51160                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       463053                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            51324                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           51324                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       463423                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1307707                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       268101                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1575808                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     36951502                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4337654                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               41289156                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          448414                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           942644                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.339212                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.475620                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1306764                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       270016                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1576780                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     36870810                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4377514                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               41248324                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          449455                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           943932                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.340597                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.476127                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 623862     66.18%     66.18% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 317808     33.71%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    974      0.10%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 623426     66.05%     66.05% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 319512     33.85%     99.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    994      0.11%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             942644                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          904161512                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             943932                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          904213819                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           342622                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           343121                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         693453750                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         693007025                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         213389277                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         215048953                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
index 16d5ea249..c7afa2620 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -845,10 +845,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -875,7 +874,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1002,12 +1001,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -1100,16 +1096,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1125,7 +1120,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1288,13 +1283,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1304,9 +1299,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1348,7 +1342,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1429,14 +1423,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1453,7 +1446,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1468,7 +1461,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1591,17 +1584,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1653,7 +1648,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1668,7 +1663,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
index a0b666cf6..e3f9f5729 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 17:52:07
-gem5 executing on e104799-lin, pid 4748
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 12:02:21
+gem5 executing on e104799-lin, pid 1517
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2858554679500 because m5_exit instruction encountered
+Exiting @ tick 2858558607500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index dccee866f..456fdbc09 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.858555                       # Number of seconds simulated
-sim_ticks                                2858554679500                       # Number of ticks simulated
-final_tick                               2858554679500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.858559                       # Number of seconds simulated
+sim_ticks                                2858558607500                       # Number of ticks simulated
+final_tick                               2858558607500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 152763                       # Simulator instruction rate (inst/s)
-host_op_rate                                   184703                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3901193118                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 583172                       # Number of bytes of host memory used
-host_seconds                                   732.74                       # Real time elapsed on the host
-sim_insts                                   111935485                       # Number of instructions simulated
-sim_ops                                     135338943                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 164210                       # Simulator instruction rate (inst/s)
+host_op_rate                                   198546                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4188709682                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 583452                       # Number of bytes of host memory used
+host_seconds                                   682.44                       # Real time elapsed on the host
+sim_insts                                   112064376                       # Number of instructions simulated
+sim_ops                                     135496266                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         7616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         8064                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1708096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9149804                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1707776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9151404                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10866540                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1708096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1708096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7937280                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10868268                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1707776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1707776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7938560                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7954804                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker          119                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7956084                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker          126                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              26689                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             143487                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              26684                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             143512                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170311                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          124020                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                170338                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124040                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               128401                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2664                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               128421                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2821                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               597538                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3200850                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               597426                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3201405                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3801411                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          597538                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             597538                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2776676                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3802010                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          597426                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             597426                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2777120                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6130                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2782806                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2776676                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2664                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2783250                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2777120                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2821                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              597538                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3206980                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              597426                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3207535                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6584217                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170311                       # Number of read requests accepted
-system.physmem.writeReqs                       128401                       # Number of write requests accepted
-system.physmem.readBursts                      170311                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     128401                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10891264                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8640                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7967296                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10866540                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7954804                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      135                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6585260                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        170338                       # Number of read requests accepted
+system.physmem.writeReqs                       128421                       # Number of write requests accepted
+system.physmem.readBursts                      170338                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     128421                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10893184                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8448                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7968384                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10868268                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7956084                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      132                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          49408                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10771                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10784                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10887                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10717                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14062                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10208                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10996                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10949                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9936                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10239                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9937                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9167                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10278                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11186                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          49420                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               10768                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10789                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10902                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10725                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14061                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10215                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11008                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10953                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9930                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10231                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9936                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9160                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10275                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11196                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              10249                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9810                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8068                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8140                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8529                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8260                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7653                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7417                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7934                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8022                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7566                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9808                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8070                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8145                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8537                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8263                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7645                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7425                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7936                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8025                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7562                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                7724                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7504                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7051                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7682                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8291                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7536                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7112                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7502                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7049                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7677                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8301                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7534                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7111                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2858554234000                       # Total gap between requests
+system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2858558162000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     543                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  169754                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  169781                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 124020                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    163165                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      6708                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       291                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 124040                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    163465                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      6437                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       292                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -159,114 +159,113 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2047                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2399                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9757                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6847                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6581                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      244                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       99                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        2                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        61347                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      307.404893                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     183.124702                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.856556                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          22378     36.48%     36.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14856     24.22%     60.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6657     10.85%     71.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3691      6.02%     77.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2584      4.21%     81.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1979      3.23%     85.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1099      1.79%     86.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1109      1.81%     88.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6994     11.40%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          61347                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6216                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.377091                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      569.055211                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6215     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2066                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2481                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6805                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6796                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8339                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9752                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6834                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6459                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      174                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       18                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        61425                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      307.065592                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     182.884404                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.926844                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          22406     36.48%     36.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14897     24.25%     60.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6725     10.95%     71.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3636      5.92%     77.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2599      4.23%     81.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1993      3.24%     85.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1038      1.69%     86.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1103      1.80%     88.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7028     11.44%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          61425                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6226                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.335689                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      568.600385                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6225     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6216                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6215                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.029123                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.467033                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.100027                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5396     86.82%     86.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             102      1.64%     88.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              39      0.63%     89.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             172      2.77%     91.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              31      0.50%     92.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             152      2.45%     94.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              39      0.63%     95.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              12      0.19%     95.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              17      0.27%     95.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              24      0.39%     96.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               4      0.06%     96.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               7      0.11%     96.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             159      2.56%     99.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.10%     99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               7      0.11%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              26      0.42%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.03%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.02%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             5      0.08%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.05%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.05%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6215                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1812035750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5002835750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    850880000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10648.01                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6226                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6226                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.997751                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.449468                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.121367                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5404     86.80%     86.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             111      1.78%     88.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              39      0.63%     89.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             181      2.91%     92.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              25      0.40%     92.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             156      2.51%     95.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              42      0.67%     95.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               8      0.13%     95.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              19      0.31%     96.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              12      0.19%     96.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               4      0.06%     96.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.10%     96.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             165      2.65%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.05%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               4      0.06%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              22      0.35%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.05%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.02%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             9      0.14%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.05%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6226                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1816793750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5008156250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    851030000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10674.09                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29398.01                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29424.09                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.81                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.79                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.80                       # Average system read bandwidth in MiByte/s
@@ -276,40 +275,40 @@ system.physmem.busUtil                           0.05                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.83                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139556                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93759                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        23.34                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139582                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93704                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   82.01                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.30                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9569599.59                       # Average gap between requests
-system.physmem.pageHitRate                      79.17                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  241731000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  131896875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 697117200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                414817200                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           186706615680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            86828058675                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1638965418000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1913985654630                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.565069                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2726406946000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95453280000                       # Time in different power states
+system.physmem.writeRowHitRate                  75.24                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9568107.28                       # Average gap between requests
+system.physmem.pageHitRate                      79.15                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  242131680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  132115500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 697483800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                415018080                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           186707124240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            87047496990                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1638777600000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1914018970290                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.574900                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2726091168500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95453540000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     36694429000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     37013727750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  222037200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  121151250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 630247800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                391819680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           186706615680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            85116075930                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1640467157250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1913655104790                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.449434                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2728919167500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95453280000                       # Time in different power states
+system.physmem_1.actEnergy                  222241320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  121262625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 630115200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                391780800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           186707124240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            85156608060                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1640436274500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1913665406745                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.451214                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2728865158250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95453540000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     34182085000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     34239762750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          512                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           512                       # Number of bytes read from this memory
@@ -329,15 +328,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                31017399                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16820647                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           2503170                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18419836                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13303162                       # Number of BTB hits
+system.cpu.branchPred.lookups                31021791                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16837881                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           2510623                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18481524                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13330573                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.221935                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7872052                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1510670                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.129187                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 7835102                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1517797                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -368,55 +367,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     65808                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                65808                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        42987                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22821                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples        65808                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0           65808    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        65808                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples         7823                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 12723.315863                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10567.827696                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8328.598591                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767         7817     99.92%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839            5      0.06%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total         7823                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                     66394                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                66394                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        43409                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22985                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples        66394                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           66394    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        66394                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples         7806                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 12863.502434                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10677.385301                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8586.171053                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767         7798     99.90%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-163839            7      0.09%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total         7806                       # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walksPending::samples    517922000                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0       517922000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::total    517922000                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6431     82.21%     82.21% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1392     17.79%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7823                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        65808                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K          6430     82.37%     82.37% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1376     17.63%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7806                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        66394                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        65808                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7823                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        66394                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7806                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7823                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        73631                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7806                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        74200                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24739501                       # DTB read hits
-system.cpu.dtb.read_misses                      58797                       # DTB read misses
-system.cpu.dtb.write_hits                    19434146                       # DTB write hits
-system.cpu.dtb.write_misses                      7011                       # DTB write misses
+system.cpu.dtb.read_hits                     24767538                       # DTB read hits
+system.cpu.dtb.read_misses                      59423                       # DTB read misses
+system.cpu.dtb.write_hits                    19447940                       # DTB write hits
+system.cpu.dtb.write_misses                      6971                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4354                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1307                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   1800                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4352                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1291                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   1803                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                       763                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24798298                       # DTB read accesses
-system.cpu.dtb.write_accesses                19441157                       # DTB write accesses
+system.cpu.dtb.perms_faults                       767                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 24826961                       # DTB read accesses
+system.cpu.dtb.write_accesses                19454911                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44173647                       # DTB hits
-system.cpu.dtb.misses                           65808                       # DTB misses
-system.cpu.dtb.accesses                      44239455                       # DTB accesses
+system.cpu.dtb.hits                          44215478                       # DTB hits
+system.cpu.dtb.misses                           66394                       # DTB misses
+system.cpu.dtb.accesses                      44281872                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -446,36 +445,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                      5439                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                 5439                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1          319                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2         5120                       # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples         5439                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0            5439    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total         5439                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3184                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12910.175879                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10824.296487                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  7389.330309                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         2456     77.14%     77.14% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          727     22.83%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks                      5448                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 5448                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1          321                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2         5127                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples         5448                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            5448    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         5448                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3187                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 13028.710386                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10952.783272                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  7366.378700                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         2453     76.97%     76.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          733     23.00%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3184                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total         3187                       # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walksPending::samples    517267500                       # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::0       517267500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::total    517267500                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          2874     90.26%     90.26% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           310      9.74%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3184                       # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K          2877     90.27%     90.27% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           310      9.73%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3187                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5439                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total         5439                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         5448                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total         5448                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3184                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3184                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total         8623                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     57560838                       # ITB inst hits
-system.cpu.itb.inst_misses                       5439                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3187                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3187                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total         8635                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     57565583                       # ITB inst hits
+system.cpu.itb.inst_misses                       5448                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -484,274 +483,274 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2972                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2975                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      8472                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      8500                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 57566277                       # ITB inst accesses
-system.cpu.itb.hits                          57560838                       # DTB hits
-system.cpu.itb.misses                            5439                       # DTB misses
-system.cpu.itb.accesses                      57566277                       # DTB accesses
-system.cpu.numCycles                        333233745                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 57571031                       # ITB inst accesses
+system.cpu.itb.hits                          57565583                       # DTB hits
+system.cpu.itb.misses                            5448                       # DTB misses
+system.cpu.itb.accesses                      57571031                       # DTB accesses
+system.cpu.numCycles                        333209630                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   111935485                       # Number of instructions committed
-system.cpu.committedOps                     135338943                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       7768370                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts                   112064376                       # Number of instructions committed
+system.cpu.committedOps                     135496266                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                       7785576                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                      3035                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                   5383936377                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.977016                       # CPI: cycles per instruction
-system.cpu.ipc                               0.335907                       # IPC: instructions per cycle
+system.cpu.quiesceCycles                   5383968359                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.973377                       # CPI: cycles per instruction
+system.cpu.ipc                               0.336318                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     3035                       # number of quiesce instructions executed
-system.cpu.tickCycles                       228546607                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       104687138                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            843126                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.899809                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42573204                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            843638                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             50.463829                       # Average number of references to valid blocks.
+system.cpu.tickCycles                       228553577                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       104656053                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            842821                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.899795                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42614913                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            843333                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             50.531537                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         594757500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.899809                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.899795                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999804                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          358                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          359                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         176066237                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        176066237                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23041742                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23041742                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18267850                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18267850                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       356487                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        356487                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443903                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443903                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460330                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460330                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41309592                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41309592                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41666079                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41666079                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       494543                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        494543                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       548727                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       548727                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       169803                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       169803                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22255                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22255                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         176231729                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        176231729                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23070027                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23070027                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18281270                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18281270                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       356578                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        356578                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443846                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443846                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460293                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460293                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41351297                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41351297                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41707875                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41707875                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       494345                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        494345                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       548690                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       548690                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       169778                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       169778                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22262                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22262                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      1043270                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1043270                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1213073                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1213073                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   8036420500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   8036420500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  35621632480                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  35621632480                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    292921000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    292921000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      1043035                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1043035                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1212813                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1212813                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8029817000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8029817000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  35659469481                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  35659469481                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    293513500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    293513500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       167000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  43658052980                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  43658052980                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  43658052980                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  43658052980                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23536285                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23536285                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     18816577                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     18816577                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       526290                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       526290                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466158                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       466158                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460332                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460332                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42352862                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42352862                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42879152                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42879152                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021012                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.021012                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029162                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029162                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.322642                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.322642                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047741                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047741                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data  43689286481                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  43689286481                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  43689286481                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  43689286481                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23564372                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23564372                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     18829960                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     18829960                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       526356                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       526356                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466108                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       466108                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460295                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460295                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42394332                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42394332                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42920688                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42920688                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020978                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.020978                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029139                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029139                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.322554                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.322554                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047761                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.047761                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024633                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024633                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.028291                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.028291                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16250.195635                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16250.195635                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64916.857527                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64916.857527                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13162.031004                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13162.031004                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024603                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024603                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.028257                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.028257                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16243.346246                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16243.346246                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64990.193882                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64990.193882                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13184.507232                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13184.507232                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83500                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83500                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41847.319467                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41847.319467                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35989.633748                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35989.633748                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          277                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41886.692662                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41886.692662                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36023.102062                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 36023.102062                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          280                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                23                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                21                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.043478                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    13.333333                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       700279                       # number of writebacks
-system.cpu.dcache.writebacks::total            700279                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        76721                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        76721                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249708                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       249708                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14008                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        14008                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       326429                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       326429                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       326429                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       326429                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       417822                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       417822                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299019                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299019                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121366                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       121366                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8247                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8247                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       699997                       # number of writebacks
+system.cpu.dcache.writebacks::total            699997                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        76799                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        76799                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       249722                       # number of WriteReq MSHR hits
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+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        13994                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        13994                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       326521                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       326521                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       326521                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       326521                       # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total       417546                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298968                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       298968                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       121374                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       121374                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8268                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8268                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       716841                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       716841                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       838207                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       838207                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       716514                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       716514                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       837888                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       837888                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31130                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27584                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6533285000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6533285000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19191527000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19191527000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1710229000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1710229000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    114982000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    114982000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6518403500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6518403500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19210408500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19210408500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1713722500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1713722500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    116087000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    116087000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25724812000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  25724812000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27435041000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  27435041000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277494000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277494000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5085199500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5085199500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11362693500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11362693500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017752                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017752                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015891                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015891                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230607                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230607                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017691                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017691                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25728812000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25728812000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27442534500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27442534500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277728500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277728500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5083599000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5083599000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11361327500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11361327500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017719                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017719                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015877                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015877                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.230593                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.230593                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017738                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017738                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016925                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016925                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019548                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019548                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15636.527038                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15636.527038                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64181.630599                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64181.630599                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.500091                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14091.500091                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13942.282042                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13942.282042                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016901                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016901                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019522                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019522                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15611.222476                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15611.222476                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64255.734727                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64255.734727                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14119.354227                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14119.354227                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14040.517658                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14040.517658                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82500                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82500                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35886.356947                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 35886.356947                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32730.627399                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 32730.627399                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201654.159974                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201654.159974                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184353.230133                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184353.230133                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193526.135164                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193526.135164                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35908.317214                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35908.317214                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32752.031894                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 32752.031894                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201661.692901                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201661.692901                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184295.207367                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184295.207367                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193502.869844                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193502.869844                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           2897280                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.208865                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            54654096                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           2897792                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             18.860600                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           2896771                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.208867                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            54659323                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           2897283                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             18.865718                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       18409362500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.208865                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.208867                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998455                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998455                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          198                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          60449703                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         60449703                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     54654096                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        54654096                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      54654096                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         54654096                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     54654096                       # number of overall hits
-system.cpu.icache.overall_hits::total        54654096                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      2897804                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       2897804                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      2897804                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        2897804                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      2897804                       # number of overall misses
-system.cpu.icache.overall_misses::total       2897804                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  40494431000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  40494431000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  40494431000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  40494431000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  40494431000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  40494431000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     57551900                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     57551900                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     57551900                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     57551900                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     57551900                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     57551900                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050351                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.050351                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.050351                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.050351                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.050351                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.050351                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13974.178723                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13974.178723                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13974.178723                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13974.178723                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13974.178723                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13974.178723                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          60453912                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60453912                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     54659323                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        54659323                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      54659323                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         54659323                       # number of demand (read+write) hits
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+system.cpu.icache.ReadReq_misses::cpu.inst      2897295                       # number of ReadReq misses
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+system.cpu.icache.overall_misses::cpu.inst      2897295                       # number of overall misses
+system.cpu.icache.overall_misses::total       2897295                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  40482979500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  40482979500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  40482979500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  40482979500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  40482979500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  40482979500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     57556618                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     57556618                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     57556618                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     57556618                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     57556618                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     57556618                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.050338                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.050338                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.050338                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.050338                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.050338                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.050338                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13972.681242                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13972.681242                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13972.681242                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13972.681242                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13972.681242                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13972.681242                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -760,218 +759,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      2897280                       # number of writebacks
-system.cpu.icache.writebacks::total           2897280                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2897804                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      2897804                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      2897804                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      2897804                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      2897804                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      2897804                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks      2896771                       # number of writebacks
+system.cpu.icache.writebacks::total           2896771                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      2897295                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      2897295                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      2897295                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      2897295                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      2897295                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      2897295                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3763                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3763                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3763                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3763                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  37596628000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  37596628000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  37596628000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  37596628000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  37596628000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  37596628000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  37585685500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  37585685500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  37585685500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  37585685500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  37585685500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  37585685500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    485921500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    485921500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    485921500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    485921500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050351                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050351                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050351                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.050351                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.050351                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.050351                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12974.179068                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12974.179068                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12974.179068                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12974.179068                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12974.179068                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12974.179068                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.050338                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.050338                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.050338                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.050338                       # mshr miss rate for demand accesses
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+system.cpu.icache.overall_mshr_miss_rate::total     0.050338                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12972.681587                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12972.681587                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12972.681587                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12972.681587                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12972.681587                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12972.681587                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96402                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65018.831836                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            7030117                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           161646                       # Sample count of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
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 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000511                       # Average occupied blocks per requestor
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+system.cpu.l2cache.overall_accesses::cpu.data       843365                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      3817737                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001740                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000212                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001647                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.982085                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.982085                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.441961                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.441961                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.442309                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.442309                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.007923                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.007923                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026106                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026106                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001663                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000216                       # miss rate for demand accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026019                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.026019                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001740                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000212                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.007923                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.172126                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.044084                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001663                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000216                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.172216                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.044090                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001740                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000212                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.007923                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.172126                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.044084                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 141340.336134                       # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.172216                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.044090                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 141650.793651                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       132500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 141266.666667                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1120.431287                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1120.431287                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 141578.740157                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1118.934695                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1118.934695                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81000                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128126.602050                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128126.602050                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130563.066202                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130563.066202                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132281.505843                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132281.505843                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 141340.336134                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128202.558700                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128202.558700                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130373.105071                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130373.105071                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132233.335675                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132233.335675                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 141650.793651                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       132500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130563.066202                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128535.491712                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 128821.182196                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 141340.336134                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130373.105071                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128597.668702                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 128849.596611                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 141650.793651                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       132500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130563.066202                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128535.491712                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 128821.182196                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130373.105071                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128597.668702                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 128849.596611                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -980,41 +979,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        87830                       # number of writebacks
-system.cpu.l2cache.writebacks::total            87830                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           23                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           23                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks        87850                       # number of writebacks
+system.cpu.l2cache.writebacks::total            87850                       # number of writebacks
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           24                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           24                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          142                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total          142                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           23                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           24                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data          142                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           23                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          166                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           24                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data          142                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          165                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          119                       # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total          166                       # number of overall MSHR hits
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 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          120                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2736                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2736                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          127                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2741                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2741                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130926                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130926                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22937                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22937                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14149                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14149                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          119                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131004                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       131004                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        22932                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        22932                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        14095                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        14095                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          126                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        22937                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       145075                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       168132                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          119                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        22932                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       145099                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168158                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          126                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        22937                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       145075                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168132                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        22932                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       145099                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168158                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3763                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31130                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34893                       # number of ReadReq MSHR uncacheable
@@ -1023,146 +1022,146 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27584
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3763                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        62477                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     15629500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     16588000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       122500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15752000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    193587000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    193587000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16710500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    193945500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    193945500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15465843500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15465843500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2766934500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2766934500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1732237500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1732237500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     15629500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15485008000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15485008000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2761851500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2761851500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1724788500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1724788500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker     16588000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       122500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2766934500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17198081000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  19980767500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     15629500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2761851500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17209796500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  19988358500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker     16588000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       122500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2766934500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17198081000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  19980767500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2761851500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17209796500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  19988358500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    427218000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888307500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6315525500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4767951000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4767951000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888547000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6315765000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4766348500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4766348500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    427218000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10656258500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11083476500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001663                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000216                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001575                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982406                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982406                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10654895500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11082113500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001740                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000212                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001647                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.982085                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.982085                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.441961                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.441961                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.442309                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.442309                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.007915                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.007915                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025846                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025846                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001663                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000216                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025759                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.025759                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001740                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000212                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007915                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.171957                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.044041                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001663                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000216                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172048                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.044047                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001740                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000212                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007915                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.171957                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.044041                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172048                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.044047                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131650.793651                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131266.666667                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70755.482456                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70755.482456                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131578.740157                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70757.205399                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70757.205399                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71000                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118126.602050                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118126.602050                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120631.926582                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120631.926582                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122428.263482                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122428.263482                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118202.558700                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118202.558700                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120436.573347                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120436.573347                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122368.818730                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122368.818730                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131650.793651                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120631.926582                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118546.138204                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118839.765779                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120436.573347                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118607.271587                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118866.533260                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131650.793651                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       122500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120631.926582                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118546.138204                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118839.765779                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120436.573347                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118607.271587                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118866.533260                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189152.184388                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180996.919153                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172852.051914                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172852.051914                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189159.877931                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181003.782994                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172793.956642                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172793.956642                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181494.336955                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177400.907534                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181471.122731                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177379.091506                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      7513660                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      3772219                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58915                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      7512196                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      3771568                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        58931                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops          590                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops          590                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         134081                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3579527                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         134847                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3579536                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27584                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27584                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       824300                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      2845639                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       144382                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2785                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       824044                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      2845126                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       144354                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2791                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2787                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       296239                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       296239                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      2897804                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       547664                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2793                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296182                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296182                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      2897295                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       547417                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8648746                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2646408                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15180                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       160178                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          11470512                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    367819456                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     99009385                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18484                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       286196                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          467133521                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      192542                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4075210                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.021724                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.145782                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      8647216                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2645494                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        15284                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       161772                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          11469766                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    367754112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98971817                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        18836                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       289572                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          467034337                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      192407                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4075202                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.021767                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.145921                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3986679     97.83%     97.83% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              88531      2.17%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3986498     97.82%     97.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              88704      2.18%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4075210                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     7434516500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        4075202                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     7433298000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       380377                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       379376                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    4352877441                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    4352139390                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1312009118                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1311523184                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      10561994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      10577994                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      88663416                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      89414413                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30183                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30183                       # Transaction distribution
@@ -1170,6 +1169,7 @@ system.iobus.trans_dist::WriteReq               59014                       # Tr
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
@@ -1185,16 +1185,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72916                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72916                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  178394                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
@@ -1210,27 +1208,26 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480229                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             46504000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             46508500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               331500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                89000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               569500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy                89500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               20500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               576500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
@@ -1250,31 +1247,25 @@ system.iobus.reqLayer20.occupancy                9500                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6052000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6069000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              168000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33518500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            33698500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           186322027                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              124500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186339520                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               37500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36740000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36424                       # number of replacements
-system.iocache.tags.tagsinuse                1.036928                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.036865                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36440                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         274875272000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.036928                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.064808                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.064808                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         274891173000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.036865                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.064804                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.064804                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1288,14 +1279,14 @@ system.iocache.demand_misses::realview.ide          234                       #
 system.iocache.demand_misses::total               234                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          234                       # number of overall misses
 system.iocache.overall_misses::total              234                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     29051377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     29051377                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4719366143                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4719366143                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     29051377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     29051377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     29051377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     29051377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     29064376                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     29064376                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4718637651                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4718637651                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     29064376                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     29064376                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     29064376                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     29064376                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          234                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            234                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1312,19 +1303,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124151.183761                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124151.183761                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130282.855096                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130282.855096                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124151.183761                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124151.183761                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124151.183761                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124151.183761                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           731                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 124206.735043                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124206.735043                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130262.744341                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130262.744341                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 124206.735043                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124206.735043                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 124206.735043                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124206.735043                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           864                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   70                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   82                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.442857                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.536585                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1338,14 +1329,14 @@ system.iocache.demand_mshr_misses::realview.ide          234
 system.iocache.demand_mshr_misses::total          234                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          234                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          234                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     17351377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     17351377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2908166143                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2908166143                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     17351377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     17351377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     17351377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     17351377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     17364376                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     17364376                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2907437651                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2907437651                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     17364376                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     17364376                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     17364376                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     17364376                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1354,68 +1345,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74151.183761                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 74151.183761                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80282.855096                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80282.855096                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74151.183761                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74151.183761                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74151.183761                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74151.183761                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74206.735043                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74206.735043                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80262.744341                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80262.744341                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 74206.735043                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 74206.735043                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 74206.735043                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 74206.735043                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               34893                       # Transaction distribution
-system.membus.trans_dist::ReadResp              72333                       # Transaction distribution
+system.membus.trans_dist::ReadResp              72281                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27584                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27584                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       124020                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8585                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4599                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       124040                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8592                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4604                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4601                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129063                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129063                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         37440                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4606                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129141                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129141                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         37388                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2074                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455241                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562809                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455331                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562899                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108900                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108900                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 671709                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 671799                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          512                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16504224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16668009                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16507232                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16671017                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18985129                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              506                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402632                       # Request fanout histogram
+system.membus.pkt_size::total                18988137                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              505                       # Total snoops (count)
+system.membus.snoop_fanout::samples            402696                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402632    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402696    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402632                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            87539000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402696                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            87390000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                8500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1722000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1706000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           878086902                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           878074394                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          999035643                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          999225638                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64196432                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64122797                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 1b1910e7a..5488fc86a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -901,10 +901,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -931,7 +930,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1058,12 +1057,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -1156,16 +1152,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1181,7 +1176,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1344,13 +1339,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1360,9 +1355,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1404,7 +1398,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1485,14 +1479,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1509,7 +1502,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1524,7 +1517,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1647,17 +1640,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1709,7 +1704,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1724,7 +1719,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
index 091864339..4aea4f504 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
@@ -42,6 +42,6 @@ warn: Ignoring write to miscreg pmovsr
 warn: Ignoring write to miscreg pmovsr
 warn: Ignoring write to miscreg pmcr
 warn: Ignoring write to miscreg pmcr
-warn: 409464655500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
+warn: 409464076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
 warn: 	instruction 'mcr dcisw' unimplemented
 warn: 	instruction 'mcr bpiall' unimplemented
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
index ece79dd87..b4dca0554 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 18:04:32
-gem5 executing on e104799-lin, pid 5292
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 12:53:29
+gem5 executing on e104799-lin, pid 6838
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@@ -42,4 +42,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2832917624000 because m5_exit instruction encountered
+Exiting @ tick 2832912592000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 5f1c2232f..36baf0032 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.832918                       # Number of seconds simulated
-sim_ticks                                2832917624000                       # Number of ticks simulated
-final_tick                               2832917624000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.832913                       # Number of seconds simulated
+sim_ticks                                2832912592000                       # Number of ticks simulated
+final_tick                               2832912592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  70397                       # Simulator instruction rate (inst/s)
-host_op_rate                                    85384                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1763575466                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 583680                       # Number of bytes of host memory used
-host_seconds                                  1606.35                       # Real time elapsed on the host
-sim_insts                                   113081477                       # Number of instructions simulated
-sim_ops                                     137157144                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  73621                       # Simulator instruction rate (inst/s)
+host_op_rate                                    89295                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1844379035                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 584220                       # Number of bytes of host memory used
+host_seconds                                  1535.97                       # Real time elapsed on the host
+sim_insts                                   113079343                       # Number of instructions simulated
+sim_ops                                     137154534                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker         1344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1316032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9392488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1316096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9383208                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10711336                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1316032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1316032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8002368                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10702120                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1316096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1316096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7997312                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8019892                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8014836                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker           21                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            8                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22810                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             147278                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22811                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             147133                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170132                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          125037                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                169988                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124958                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129418                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               129339                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            474                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker            181                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               464550                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3315482                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               464573                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3312212                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3781026                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          464550                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             464550                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2824780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3777780                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          464573                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             464573                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2823000                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6186                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2830965                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2824780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2829186                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2823000                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           474                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker           181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              464550                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3321668                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              464573                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3318398                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6611992                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170133                       # Number of read requests accepted
-system.physmem.writeReqs                       129418                       # Number of write requests accepted
-system.physmem.readBursts                      170133                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129418                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10877696                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10816                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8031936                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10711400                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8019892                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      169                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6606966                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        169989                       # Number of read requests accepted
+system.physmem.writeReqs                       129339                       # Number of write requests accepted
+system.physmem.readBursts                      169989                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129339                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10867584                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     11712                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8027584                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10702184                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8014836                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      183                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          48557                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11298                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10506                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10925                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11199                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12883                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10202                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10845                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11219                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10577                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10527                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10037                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8948                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9970                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10631                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9988                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10209                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8496                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7860                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8364                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8532                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7663                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7568                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8029                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8274                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8070                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7909                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7508                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6646                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7551                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8006                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7465                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7558                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          48490                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11395                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10615                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11052                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11362                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12761                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10093                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10904                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11084                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10554                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10523                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10030                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8841                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9967                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10661                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9878                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10086                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8599                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7964                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8486                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8679                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7544                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7468                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8077                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8182                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8055                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7911                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7496                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6568                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7556                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8042                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7357                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7447                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2832917392000                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2832912360000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166581                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166437                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 125037                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150592                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16496                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       726                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 124958                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    150468                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16446                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2150                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       725                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
@@ -159,156 +159,156 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2033                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5707                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7704                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7922                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6870                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6611                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2028                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6673                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6911                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7819                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9948                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7795                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7406                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6937                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6529                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      304                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      125                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::44                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       20                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       36                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62145                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      304.281406                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.810971                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.663684                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23300     37.49%     37.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14989     24.12%     61.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6559     10.55%     72.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3523      5.67%     77.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2511      4.04%     81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1609      2.59%     84.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1592      2.56%     87.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1065      1.71%     88.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6997     11.26%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62145                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6266                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.121768                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      563.971651                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6265     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::60                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        62097                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      304.283685                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.850271                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.574400                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23280     37.49%     37.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14997     24.15%     61.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6479     10.43%     72.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3584      5.77%     77.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2530      4.07%     81.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1603      2.58%     84.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1574      2.53%     87.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1048      1.69%     88.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7002     11.28%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          62097                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6262                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.116097                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      564.155612                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6261     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6266                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6266                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.028567                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.454463                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.210745                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5460     87.14%     87.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             110      1.76%     88.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              30      0.48%     89.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             168      2.68%     92.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              26      0.41%     92.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             137      2.19%     94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              53      0.85%     95.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              15      0.24%     95.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              11      0.18%     95.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              21      0.34%     96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.10%     96.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               7      0.11%     96.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             165      2.63%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.08%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              23      0.37%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.03%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            12      0.19%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6266                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2116809750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5303634750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    849820000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12454.46                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6262                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6262                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.030501                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.464444                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.039261                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5446     86.97%     86.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             116      1.85%     88.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              36      0.57%     89.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             167      2.67%     92.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              22      0.35%     92.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             138      2.20%     94.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              54      0.86%     95.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.19%     95.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              19      0.30%     95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              16      0.26%     96.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.10%     96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               3      0.05%     96.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             160      2.56%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.10%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               9      0.14%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              25      0.40%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.05%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.02%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.21%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6262                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2134847750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5318710250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    849030000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12572.28                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31204.46                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31322.28                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.84                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.84                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.83                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.78                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.83                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139542                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93775                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.70                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9457212.27                       # Average gap between requests
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.05                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139313                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93826                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.04                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.79                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9464241.10                       # Average gap between requests
 system.physmem.pageHitRate                      78.96                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  246546720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  134524500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 694792800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                419813280                       # Energy for write commands per rank (pJ)
+system.physmem_0.actEnergy                  247680720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  135143250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 696267000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                421193520                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           185031927600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83588992920                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626422631000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1896539228820                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.466691                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705562728250                       # Time in different power states
+system.physmem_0.actBackEnergy            83693103705                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1626331305750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1896556621545                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.472831                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2705407276500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     94597100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32757782250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32908202000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  223269480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  121823625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 630918600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                393420240                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                  221772600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  121006875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 628212000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                391599360                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           185031927600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            81878542335                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1627923026250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1896202928130                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.347979                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2708066096500                       # Time in different power states
+system.physmem_1.actBackEnergy            81799663455                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1627992218250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1896186400140                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.342145                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2708183660500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     94597100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30247332250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30129768250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
@@ -328,15 +328,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46858822                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24018425                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1233385                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29501817                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21322160                       # Number of BTB hits
+system.cpu.branchPred.lookups                46857763                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24018162                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1233841                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29502900                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21322687                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.274057                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11724285                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33905                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.273190                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11723693                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33902                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -367,30 +367,30 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.walks              9701                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksShort         9701                       # Table walker walks initiated with short descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples         9701                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0         9701    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total         9701                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walks              9704                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksShort         9704                       # Table walker walks initiated with short descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples         9704                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0         9704    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total         9704                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.dtb.walker.walksPending::samples    375751000                       # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::0    375751000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::total    375751000                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K         6238     82.77%     82.77% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::1M         1299     17.23%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total         7537                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9701                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkPageSizes::4K         6218     82.47%     82.47% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::1M         1322     17.53%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total         7540                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data         9704                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9701                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7537                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total         9704                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data         7540                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7537                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total        17238                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total         7540                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total        17244                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             24572028                       # DTB read hits
-system.cpu.checker.dtb.read_misses               8280                       # DTB read misses
-system.cpu.checker.dtb.write_hits            19630755                       # DTB write hits
-system.cpu.checker.dtb.write_misses              1421                       # DTB write misses
+system.cpu.checker.dtb.read_hits             24571778                       # DTB read hits
+system.cpu.checker.dtb.read_misses               8287                       # DTB read misses
+system.cpu.checker.dtb.write_hits            19630535                       # DTB write hits
+system.cpu.checker.dtb.write_misses              1417                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                  128                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva             1834                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
@@ -400,12 +400,12 @@ system.cpu.checker.dtb.align_faults                 0                       # Nu
 system.cpu.checker.dtb.prefetch_faults           1642                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               445                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         24580308                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        19632176                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         24580065                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        19631952                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  44202783                       # DTB hits
-system.cpu.checker.dtb.misses                    9701                       # DTB misses
-system.cpu.checker.dtb.accesses              44212484                       # DTB accesses
+system.cpu.checker.dtb.hits                  44202313                       # DTB hits
+system.cpu.checker.dtb.misses                    9704                       # DTB misses
+system.cpu.checker.dtb.accesses              44212017                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -453,7 +453,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst         3170                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total         3170                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin::total         7995                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            115778479                       # ITB inst hits
+system.cpu.checker.itb.inst_hits            115776285                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4825                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -470,11 +470,11 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        115783304                       # ITB inst accesses
-system.cpu.checker.itb.hits                 115778479                       # DTB hits
+system.cpu.checker.itb.inst_accesses        115781110                       # ITB inst accesses
+system.cpu.checker.itb.hits                 115776285                       # DTB hits
 system.cpu.checker.itb.misses                    4825                       # DTB misses
-system.cpu.checker.itb.accesses             115783304                       # DTB accesses
-system.cpu.checker.numCycles                139006189                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses             115781110                       # DTB accesses
+system.cpu.checker.numCycles                139003519                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -506,84 +506,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     71435                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                71435                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29241                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22400                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19794                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        51641                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   426.153638                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2576.445985                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095        49864     96.56%     96.56% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191          585      1.13%     97.69% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287          525      1.02%     98.71% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383          340      0.66%     99.37% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                     71876                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                71876                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29748                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22357                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        19771                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52105                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   423.395068                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2574.283993                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095        50327     96.59%     96.59% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191          585      1.12%     97.71% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287          525      1.01%     98.72% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383          339      0.65%     99.37% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::16384-20479           52      0.10%     99.47% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::20480-24575          220      0.43%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::20480-24575          221      0.42%     99.89% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::24576-28671           14      0.03%     99.92% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::28672-32767           10      0.02%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-36863            8      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::36864-40959            5      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-36863            8      0.02%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::36864-40959            5      0.01%     99.96% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::40960-45055            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::45056-49151           11      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::45056-49151           12      0.02%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::49152-53247            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::53248-57343            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::57344-61439            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::61440-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        51641                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17522                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11533.700491                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  9159.086359                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8173.463802                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767        17339     98.96%     98.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkWaitTime::total        52105                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        17499                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11526.115778                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  9158.153521                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8139.378931                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767        17316     98.95%     98.95% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::32768-65535          177      1.01%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::131072-163839            5      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17522                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131382086816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.616564                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.493575                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  131327318816     99.96%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      37570000      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       7000000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6185500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1198500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        17499                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131377054816                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.616890                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.493493                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  131322424316     99.96%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      37436500      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       7011000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       6169000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9       1200000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::10-11       643000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::12-13      1366500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::14-15       794500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::16-17        10000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131382086816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6381     82.69%     82.69% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1336     17.31%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7717                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71435                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 131377054816                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6345     82.32%     82.32% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1363     17.68%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7708                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71876                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71435                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7717                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71876                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7708                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7717                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        79152                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7708                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        79584                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25445516                       # DTB read hits
-system.cpu.dtb.read_misses                      61525                       # DTB read misses
-system.cpu.dtb.write_hits                    19906341                       # DTB write hits
-system.cpu.dtb.write_misses                      9910                       # DTB write misses
+system.cpu.dtb.read_hits                     25445789                       # DTB read hits
+system.cpu.dtb.read_misses                      61974                       # DTB read misses
+system.cpu.dtb.write_hits                    19906281                       # DTB write hits
+system.cpu.dtb.write_misses                      9902                       # DTB write misses
 system.cpu.dtb.flush_tlb                          128                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4317                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       358                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.align_faults                       357                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                   2185                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                      1330                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25507041                       # DTB read accesses
-system.cpu.dtb.write_accesses                19916251                       # DTB write accesses
+system.cpu.dtb.read_accesses                 25507763                       # DTB read accesses
+system.cpu.dtb.write_accesses                19916183                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45351857                       # DTB hits
-system.cpu.dtb.misses                           71435                       # DTB misses
-system.cpu.dtb.accesses                      45423292                       # DTB accesses
+system.cpu.dtb.hits                          45352070                       # DTB hits
+system.cpu.dtb.misses                           71876                       # DTB misses
+system.cpu.dtb.accesses                      45423946                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -613,55 +613,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                     11899                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                11899                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3941                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walks                     11893                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                11893                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3935                       # Level at which table walker walks with short descriptors terminate
 system.cpu.itb.walker.walksShortTerminationLevel::Level2         7737                       # Level at which table walker walks with short descriptors terminate
 system.cpu.itb.walker.walksSquashedBefore          221                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11678                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   616.629560                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  2880.318774                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095        11122     95.24%     95.24% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::samples        11672                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   618.017478                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  2885.502200                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095        11116     95.24%     95.24% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::4096-8191          159      1.36%     96.60% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287          193      1.65%     98.25% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383           62      0.53%     98.78% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479           98      0.84%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575           32      0.27%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287          192      1.64%     98.24% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383           62      0.53%     98.77% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479           98      0.84%     99.61% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575           33      0.28%     99.90% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.91% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::28672-32767            7      0.06%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::45056-49151            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::49152-53247            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::57344-61439            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11678                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3549                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12870.386024                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10191.624224                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  8688.844550                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         2600     73.26%     73.26% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          892     25.13%     98.39% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151           55      1.55%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total        11672                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3547                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12874.259938                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10191.545390                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  8701.526273                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         2599     73.27%     73.27% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          890     25.09%     98.36% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-49151           56      1.58%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3549                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  24007842416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.962955                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.189019                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       889977000      3.71%      3.71% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     23117314916     96.29%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::total         3547                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  24002810416                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.962951                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.189029                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       889895500      3.71%      3.71% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     23112364416     96.29%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::2          493000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::3           57500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  24007842416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          3008     90.38%     90.38% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           320      9.62%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3328                       # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total  24002810416                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          3008     90.44%     90.44% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           318      9.56%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3326                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11899                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        11899                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11893                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        11893                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3328                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3328                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        15227                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     66219818                       # ITB inst hits
-system.cpu.itb.inst_misses                      11899                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3326                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3326                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        15219                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     66221269                       # ITB inst hits
+system.cpu.itb.inst_misses                      11893                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -670,98 +670,98 @@ system.cpu.itb.flush_tlb                          128                       # Nu
 system.cpu.itb.flush_tlb_mva                     1834                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3095                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3094                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2205                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2209                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66231717                       # ITB inst accesses
-system.cpu.itb.hits                          66219818                       # DTB hits
-system.cpu.itb.misses                           11899                       # DTB misses
-system.cpu.itb.accesses                      66231717                       # DTB accesses
-system.cpu.numCycles                        278809396                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66233162                       # ITB inst accesses
+system.cpu.itb.hits                          66221269                       # DTB hits
+system.cpu.itb.misses                           11893                       # DTB misses
+system.cpu.itb.accesses                      66233162                       # DTB accesses
+system.cpu.numCycles                        278796094                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104752228                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184594753                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46858822                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33046445                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     161837102                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6149420                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     189977                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 9772                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        357687                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       560902                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          181                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66220013                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1133469                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5179                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          270782559                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.831431                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.217897                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104750737                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184597310                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46857763                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33046380                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     161828011                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6150220                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     189816                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                10180                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        357136                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       560173                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          186                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  66221459                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1133676                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5180                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          270771349                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.831471                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.217911                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                171565839     63.36%     63.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29222654     10.79%     74.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14067780      5.20%     79.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55926286     20.65%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                171553381     63.36%     63.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29224188     10.79%     74.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14067085      5.20%     79.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55926695     20.65%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            270782559                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.168068                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.662082                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 77849645                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             121907615                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64584092                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3844418                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2596789                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3423202                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                486322                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157325754                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3698413                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2596789                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83693975                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11775859                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       76672657                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62585691                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              33457588                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146699029                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                957260                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                452831                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  63761                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  16550                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30707740                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150373398                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678238170                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164317610                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            270771349                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.168072                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.662123                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 77850364                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             121893157                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64586539                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3844068                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2597221                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3423151                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                486287                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157328219                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3698916                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2597221                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83695488                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11783440                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       76673328                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62587040                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              33434832                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146701505                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                957116                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                452960                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  63776                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  16375                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30685156                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150380164                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             678249075                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164321181                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups             10889                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141712294                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8661101                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2840653                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2644485                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13863116                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26394295                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21292545                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1689185                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2215742                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143439670                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2121732                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143229007                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            270292                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8404254                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14686510                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125844                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     270782559                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.528945                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.865530                       # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps             141709271                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8670890                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2840534                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2644382                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13862021                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26394587                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21292605                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1688978                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2214312                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143440731                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2121629                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143228275                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            270765                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8407822                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14697300                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         125774                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     270771349                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.528964                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.865543                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           182544969     67.41%     67.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45137079     16.67%     84.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            32020155     11.83%     95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10269839      3.79%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              810484      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           182535287     67.41%     67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45134238     16.67%     84.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32022031     11.83%     95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10269230      3.79%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              810530      0.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -769,9 +769,9 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       270782559                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       270771349                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7336568     32.74%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7336420     32.74%     32.74% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                     32      0.00%     32.74% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.74% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.74% # attempts to use FU when none available
@@ -800,13 +800,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.74% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.74% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.74% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5631848     25.13%     57.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9441706     42.13%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5631672     25.13%     57.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9443165     42.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95930740     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               113813      0.08%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95929589     66.98%     66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               113798      0.08%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
@@ -834,95 +834,95 @@ system.cpu.iq.FU_type_0::SimdFloatMisc           8576      0.01%     67.06% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26175663     18.28%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            20997878     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26176168     18.28%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20997807     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143229007                       # Type of FU issued
-system.cpu.iq.rate                           0.513717                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22410154                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156464                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          579885434                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         153971015                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140120635                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              143228275                       # Type of FU issued
+system.cpu.iq.rate                           0.513738                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22411289                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156473                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          579874368                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153975557                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140119306                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads               35585                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes              13122                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses        11367                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165613479                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              165613882                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                   23345                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           322744                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads           322775                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1495175                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          502                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18526                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       703988                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1495918                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          503                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18543                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       704297                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        87827                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6407                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        87804                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6457                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2596789                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1243570                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                532137                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145762333                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2597221                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1240950                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                535645                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145763292                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26394295                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21292545                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1096246                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17995                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                497968                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18526                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317449                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471196                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               788645                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142286885                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25773498                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            870795                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26394587                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21292605                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1096200                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17982                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                501480                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18543                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         317940                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471176                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               789116                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142285522                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25773547                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            870984                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        200931                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46642508                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26501737                       # Number of branches executed
-system.cpu.iew.exec_stores                   20869010                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.510337                       # Inst execution rate
-system.cpu.iew.wb_sent                      141900432                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140132002                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63223126                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95712973                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.502609                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660549                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         7603118                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995888                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755464                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    267848804                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.512648                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.117834                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        200932                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46642466                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26501161                       # Number of branches executed
+system.cpu.iew.exec_stores                   20868919                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.510357                       # Inst execution rate
+system.cpu.iew.wb_sent                      141899022                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140130673                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63222272                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95712658                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.502628                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660542                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         7606616                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995855                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            755952                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    267837215                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.512660                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.117818                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    194453826     72.60%     72.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43232556     16.14%     88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15468323      5.78%     94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4394328      1.64%     96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6341907      2.37%     98.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1685586      0.63%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       800919      0.30%     99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       412081      0.15%     99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1059278      0.40%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    194442706     72.60%     72.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43232016     16.14%     88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15468771      5.78%     94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4394333      1.64%     96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6341721      2.37%     98.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1685699      0.63%     99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       801066      0.30%     99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       412117      0.15%     99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1058786      0.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    267848804                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113236382                       # Number of instructions committed
-system.cpu.commit.committedOps              137312049                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    267837215                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113234248                       # Number of instructions committed
+system.cpu.commit.committedOps              137309439                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45487677                       # Number of memory references committed
-system.cpu.commit.loads                      24899120                       # Number of loads committed
-system.cpu.commit.membars                      814929                       # Number of memory barriers committed
-system.cpu.commit.branches                   26016406                       # Number of branches committed
+system.cpu.commit.refs                       45486977                       # Number of memory references committed
+system.cpu.commit.loads                      24898669                       # Number of loads committed
+system.cpu.commit.membars                      814916                       # Number of memory barriers committed
+system.cpu.commit.branches                   26015904                       # Number of branches committed
 system.cpu.commit.fp_insts                      11364                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120142081                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4881652                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120139692                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4881505                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91703052     66.78%     66.78% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          112745      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91701155     66.78%     66.78% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          112732      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -950,36 +950,36 @@ system.cpu.commit.op_class_0::SimdFloatMisc         8575      0.01%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24899120     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20588557     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24898669     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20588308     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137312049                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1059278                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    389547304                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292761659                       # The number of ROB writes
-system.cpu.timesIdled                          892855                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         8026837                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5387025853                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113081477                       # Number of Instructions Simulated
-system.cpu.committedOps                     137157144                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.465562                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.465562                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.405587                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.405587                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155726558                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88564581                       # number of integer regfile writes
+system.cpu.commit.op_class_0::total         137309439                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1058786                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    389537878                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292763814                       # The number of ROB writes
+system.cpu.timesIdled                          892824                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         8024745                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5387029091                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113079343                       # Number of Instructions Simulated
+system.cpu.committedOps                     137154534                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.465491                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.465491                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.405599                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.405599                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155725297                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88564294                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                      9527                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502647576                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53157224                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               348272878                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521665                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            837515                       # number of replacements
+system.cpu.cc_regfile_reads                 502644824                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53156150                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               348441241                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521640                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            837355                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.925653                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40092431                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            838027                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.841455                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            40093226                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            837867                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.851540                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         441954500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.925653                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999855                       # Average percentage of cache occupancy
@@ -989,190 +989,190 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          120
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179262738                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179262738                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23296604                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23296604                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15545032                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15545032                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345927                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345927                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441660                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441660                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460331                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460331                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38841636                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38841636                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39187563                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39187563                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       708765                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        708765                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3602792                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3602792                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177926                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177926                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        27128                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        27128                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         179262562                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179262562                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23296906                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23296906                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15545467                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15545467                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       345973                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        345973                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441682                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441682                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460325                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460325                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38842373                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38842373                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39188346                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39188346                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       708692                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        708692                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3602140                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3602140                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177879                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177879                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        27097                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        27097                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4311557                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4311557                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4489483                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4489483                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11704891500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11704891500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232547539185                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232547539185                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    374670000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    374670000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      4310832                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4310832                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4488711                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4488711                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11726844500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11726844500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 232349107178                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 232349107178                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    373049000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    373049000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       305000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       305000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244252430685                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244252430685                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244252430685                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244252430685                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24005369                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24005369                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19147824                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19147824                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523853                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523853                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468788                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468788                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43153193                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43153193                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43677046                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43677046                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029525                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029525                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188157                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188157                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339649                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339649                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057868                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057868                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 244075951678                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 244075951678                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 244075951678                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 244075951678                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24005598                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24005598                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19147607                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19147607                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523852                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523852                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468779                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468779                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460332                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460332                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43153205                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43153205                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43677057                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43677057                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029522                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029522                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188125                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.188125                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339560                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339560                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057803                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057803                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000015                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000015                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.099913                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.099913                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102788                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102788                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16514.488582                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16514.488582                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64546.479282                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64546.479282                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13811.191389                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13811.191389                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.099896                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.099896                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102770                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102770                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.166470                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.166470                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64503.075166                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64503.075166                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13767.169797                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13767.169797                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56650.632401                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56650.632401                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54405.469557                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54405.469557                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       871729                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56619.221458                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56619.221458                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54375.510403                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54375.510403                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       870696                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6864                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6851                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.000146                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.090352                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       695593                       # number of writebacks
-system.cpu.dcache.writebacks::total            695593                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295624                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       295624                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3303164                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3303164                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18735                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18735                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3598788                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3598788                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3598788                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3598788                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       413141                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       413141                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299628                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299628                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119644                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119644                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8393                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8393                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       695416                       # number of writebacks
+system.cpu.dcache.writebacks::total            695416                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295634                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       295634                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3302552                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3302552                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18703                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18703                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3598186                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3598186                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3598186                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3598186                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       413058                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       413058                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299588                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299588                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119604                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119604                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8394                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8394                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       712769                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       712769                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       832413                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       832413                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       712646                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       712646                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       832250                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       832250                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6386936500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6386936500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19975151483                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19975151483                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1701142500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1701142500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126808000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126808000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6391901000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6391901000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19972155480                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19972155480                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1700460500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1700460500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126799500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126799500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       298000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       298000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26362087983                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26362087983                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28063230483                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28063230483                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277199000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277199000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075698951                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075698951                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11352897951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11352897951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017210                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017210                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015648                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015648                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228392                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228392                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017904                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017904                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26364056480                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26364056480                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28064516980                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28064516980                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276327500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276327500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075770951                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075770951                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11352098451                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11352098451                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017207                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017207                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015646                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015646                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228316                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228316                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017906                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017906                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000015                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000015                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016517                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016517                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019058                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019058                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15459.459361                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15459.459361                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66666.504743                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66666.504743                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14218.368660                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14218.368660                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15108.781127                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15108.781127                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016514                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016514                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019055                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019055                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15474.584683                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15474.584683                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66665.405423                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66665.405423                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.421658                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.421658                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15105.968549                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15105.968549                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36985.458098                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36985.458098                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33713.109338                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33713.109338                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201651.161297                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201651.161297                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.137067                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.137067                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193359.300184                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193359.300184                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36994.603885                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36994.603885                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33721.258011                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33721.258011                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.164894                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.164894                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184004.747181                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184004.747181                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193345.683329                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193345.683329                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1886833                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.154154                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64237730                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1887345                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             34.036029                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1886675                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.154168                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64239376                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1887187                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             34.039751                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       16318088500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.154154                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.154168                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -1181,272 +1181,272 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          197
 system.cpu.icache.tags.age_task_id_blocks_1024::2          209                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68104377                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68104377                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64237730                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64237730                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64237730                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64237730                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64237730                       # number of overall hits
-system.cpu.icache.overall_hits::total        64237730                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1979279                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1979279                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1979279                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1979279                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1979279                       # number of overall misses
-system.cpu.icache.overall_misses::total       1979279                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  28148050491                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  28148050491                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  28148050491                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  28148050491                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  28148050491                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  28148050491                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66217009                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66217009                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66217009                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66217009                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66217009                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66217009                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029891                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029891                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029891                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029891                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029891                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029891                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14221.365705                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14221.365705                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14221.365705                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14221.365705                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14221.365705                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14221.365705                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4340                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          68105664                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         68105664                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64239376                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64239376                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64239376                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64239376                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     64239376                       # number of overall hits
+system.cpu.icache.overall_hits::total        64239376                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1979079                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1979079                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1979079                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1979079                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1979079                       # number of overall misses
+system.cpu.icache.overall_misses::total       1979079                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  28144068491                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  28144068491                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  28144068491                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  28144068491                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  28144068491                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  28144068491                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66218455                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66218455                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66218455                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66218455                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66218455                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66218455                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029887                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029887                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029887                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029887                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029887                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029887                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14220.790828                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14220.790828                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14220.790828                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14220.790828                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14220.790828                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14220.790828                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         5080                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               160                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               162                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    27.125000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    31.358025                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1886833                       # number of writebacks
-system.cpu.icache.writebacks::total           1886833                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91909                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        91909                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        91909                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        91909                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        91909                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        91909                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1887370                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1887370                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1887370                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1887370                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1887370                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1887370                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks      1886675                       # number of writebacks
+system.cpu.icache.writebacks::total           1886675                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91868                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        91868                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        91868                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        91868                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        91868                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        91868                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1887211                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1887211                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1887211                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1887211                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1887211                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1887211                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25183213993                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  25183213993                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25183213993                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  25183213993                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25183213993                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  25183213993                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25180995493                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  25180995493                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25180995493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  25180995493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25180995493                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  25180995493                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377667500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377667500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377667500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    377667500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028503                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028503                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028503                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028503                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028503                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028503                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13343.019118                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13343.019118                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13343.019118                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028500                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028500                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028500                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.028500                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028500                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.028500                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13342.967741                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13342.967741                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13342.967741                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13342.967741                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13342.967741                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13342.967741                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96631                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65023.762629                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4997690                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           161869                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            30.874905                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            96487                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65023.312748                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4997676                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           161725                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            30.902309                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49540.037548                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.058123                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     1.836532                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10328.574212                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5143.256214                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.755921                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000153                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 49475.678025                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.897856                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     1.835471                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10343.602046                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5191.299351                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.754939                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000166                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000028                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.157602                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.078480                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.992184                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1023           12                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65226                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2892                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2890                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6640                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55528                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55530                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995270                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         44234795                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        44234795                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        54117                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        11847                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          65964                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       695593                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       695593                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1846839                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1846839                       # number of WritebackClean hits
+system.cpu.l2cache.tags.tag_accesses         44233161                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        44233161                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        54581                       # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_hits::total          66422                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       695416                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       695416                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1846676                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1846676                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           33                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           33                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            4                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       161471                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       161471                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1867481                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1867481                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       527598                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       527598                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        54117                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        11847                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1867481                       # number of demand (read+write) hits
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-system.cpu.l2cache.demand_hits::total         2622514                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        54117                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        11847                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1867481                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       689069                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2622514                       # number of overall hits
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+system.cpu.l2cache.ReadExReq_hits::total       161568                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1867325                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1867325                       # number of ReadCleanReq hits
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+system.cpu.l2cache.demand_hits::cpu.inst      1867325                       # number of demand (read+write) hits
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+system.cpu.l2cache.demand_hits::total         2622800                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        54581                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        11841                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1867325                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       689053                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2622800                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           21                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            8                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total           29                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2723                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2723                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2721                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2721                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       135531                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       135531                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19843                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        19843                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        13450                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        13450                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       135393                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       135393                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        19844                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        19844                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        13444                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        13444                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker           21                       # number of demand (read+write) misses
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-system.cpu.l2cache.demand_misses::cpu.inst        19843                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       148981                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        168853                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        19844                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       148837                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        168710                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker           21                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            8                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        19843                       # number of overall misses
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-system.cpu.l2cache.overall_misses::total       168853                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      2920500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker      1140500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total      4061000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2260500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      2260500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst        19844                       # number of overall misses
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+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2179500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total      2179500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162000                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  17607551500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  17607551500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2626802500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2626802500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1813838000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1813838000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      2920500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker      1140500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2626802500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  19421389500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  22052253000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      2920500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker      1140500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2626802500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  19421389500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  22052253000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        54138                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        11855                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        65993                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       695593                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       695593                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1846839                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1846839                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2756                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2756                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  17603720000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  17603720000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2626422000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2626422000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1819515000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1819515000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3081000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker      1062000                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.WritebackDirty_accesses::writebacks       695416                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       695416                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1846676                       # number of WritebackClean accesses(hits+misses)
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+system.cpu.l2cache.UpgradeReq_accesses::total         2754                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            7                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            7                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       297002                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       297002                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1887324                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1887324                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       541048                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       541048                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        54138                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        11855                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1887324                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       838050                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2791367                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        54138                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        11855                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1887324                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       838050                       # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000388                       # miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1887169                       # number of ReadCleanReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000385                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000675                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000439                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.988026                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.988026                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000436                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.988017                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.988017                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.428571                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.428571                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.456330                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.456330                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010514                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010514                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.024859                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024859                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000388                       # miss rate for demand accesses
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+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010515                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010515                       # miss rate for ReadCleanReq accesses
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+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000385                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000675                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010514                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.177771                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.060491                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000388                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010515                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.177633                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.060437                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000385                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000675                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010514                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.177771                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.060491                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 139071.428571                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 142562.500000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 140034.482759                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   830.150569                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   830.150569                       # average UpgradeReq miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010515                       # miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 146714.285714                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       132750                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 142862.068966                       # average ReadReq miss latency
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   800.992282                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        54000                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        54000                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129915.307199                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129915.307199                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132379.302525                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132379.302525                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134857.843866                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134857.843866                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 139071.428571                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 142562.500000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132379.302525                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130361.519254                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 130600.303222                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139071.428571                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 142562.500000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132379.302525                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130361.519254                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 130600.303222                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130019.424933                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130019.424933                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132353.456964                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132353.456964                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135340.300506                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135340.300506                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 146714.285714                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       132750                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132353.456964                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130500.043672                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 130720.170707                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 146714.285714                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       132750                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132353.456964                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130500.043672                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 130720.170707                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1455,41 +1455,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        88877                       # number of writebacks
-system.cpu.l2cache.writebacks::total            88877                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        88798                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88798                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           26                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          112                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          112                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          113                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          113                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           26                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          112                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          138                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          139                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           26                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          138                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          139                       # number of overall MSHR hits
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           21                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            8                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total           29                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2723                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2723                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2721                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2721                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135531                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       135531                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19817                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19817                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13338                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13338                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135393                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       135393                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19818                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19818                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13331                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13331                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           21                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            8                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        19817                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       148869                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       168715                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        19818                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       148724                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168571                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           21                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            8                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        19817                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       148869                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168715                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        19818                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       148724                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168571                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34133                       # number of ReadReq MSHR uncacheable
@@ -1498,146 +1498,146 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27585
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61718                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker      1060500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3771000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    192695000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    192695000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2871000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       982000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3853000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    192556500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    192556500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       212500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       212500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16252241500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16252241500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2425990000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2425990000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1667259500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1667259500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker      1060500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2425990000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17919501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20349262000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker      1060500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2425990000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17919501000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20349262000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16249790000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16249790000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2425294500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2425294500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1672223500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1672223500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2871000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       982000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2425294500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17922013500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20351161000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2871000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       982000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2425294500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17922013500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20351161000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340117000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888077000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6228194000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4756881000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4756881000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5887205500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6227322500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4756953000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4756953000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340117000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10644958000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10985075000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10644158500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10984275500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000385                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000439                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.988026                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.988026                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000436                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.988017                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.988017                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.456330                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.456330                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010500                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024652                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024652                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455929                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455929                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010501                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010501                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024645                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024645                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000385                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177637                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060442                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010501                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177498                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060387                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000385                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177637                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060442                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130034.482759                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70765.699596                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70765.699596                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010501                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177498                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060387                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132862.068966                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70766.813671                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70766.813671                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119915.307199                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119915.307199                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122419.639703                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125000.712251                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125000.712251                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120370.936864                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120613.235338                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120370.936864                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120613.235338                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120019.424933                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120019.424933                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122378.368150                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122378.368150                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125438.714275                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125438.714275                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122378.368150                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120505.187461                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120727.533206                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122378.368150                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120505.187461                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120727.533206                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189150.856115                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182468.403012                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172444.480696                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172444.480696                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.859713                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.870536                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.090810                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.090810                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181301.870082                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177988.188211                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.253228                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.234129                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5484076                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2758688                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        47112                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          381                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          381                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5483387                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2758318                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        47114                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          382                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          382                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         127589                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2556141                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         128004                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2556278                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27585                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       820637                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1846839                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       142823                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2757                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       820384                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1846676                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       142776                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2755                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2763                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297002                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297002                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1887370                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       541297                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2761                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296961                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296961                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1887211                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       541178                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        36194                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5627539                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2629603                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31270                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128179                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8416591                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    239034368                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98344937                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        47420                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       216552                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          337643277                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      197136                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3052848                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.025905                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.158851                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5627062                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2629120                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31258                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       129064                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8416504                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    239014016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98323369                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        47396                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       218408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          337603189                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      196948                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3052801                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025889                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.158805                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2973765     97.41%     97.41% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              79083      2.59%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2973766     97.41%     97.41% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              79035      2.59%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3052848                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5400072997                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3052801                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5399625997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       264877                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2834880345                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2834640846                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1303595064                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1303359054                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19421986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19415986                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74092896                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74513896                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
@@ -1645,6 +1645,7 @@ system.iobus.trans_dist::WriteReq               59014                       # Tr
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
@@ -1660,16 +1661,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  178424                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
@@ -1685,26 +1684,25 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             43091000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             43090500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                99500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                29000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               325000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                91000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               647500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy                91000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer8.occupancy               648000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
@@ -1721,35 +1719,29 @@ system.iobus.reqLayer18.occupancy                9000                       # La
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6192000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6193500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              167000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33084000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            33054500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           186380025                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              126000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186395016                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               31500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36409                       # number of replacements
-system.iocache.tags.tagsinuse                1.005392                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.005380                       # Cycle average of tags in use
 system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256608771000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.005392                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062837                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062837                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         256605907000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.005380                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062836                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062836                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1765,14 +1757,14 @@ system.iocache.demand_misses::realview.ide          249                       #
 system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          249                       # number of overall misses
 system.iocache.overall_misses::total              249                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31311876                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31311876                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4715518140                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4715518140                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31311876                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31311876                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31311876                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31311876                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     31316876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31316876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4717082149                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4717082149                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     31316876                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     31316876                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     31316876                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     31316876                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1789,19 +1781,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.506024                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125750.506024                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130280.926647                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130280.926647                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125750.506024                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125750.506024                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125750.506024                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125750.506024                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           725                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 125770.586345                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125770.586345                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130324.137284                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130324.137284                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125770.586345                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125770.586345                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125770.586345                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125770.586345                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           902                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   77                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   96                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.415584                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.395833                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1815,14 +1807,14 @@ system.iocache.demand_mshr_misses::realview.ide          249
 system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     18861876                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     18861876                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2905768140                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2905768140                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     18861876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     18861876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     18861876                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     18861876                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18866876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     18866876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2907332149                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2907332149                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     18866876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     18866876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     18866876                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     18866876                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteLineReq accesses
@@ -1831,68 +1823,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.506024                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.506024                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.926647                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80280.926647                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.506024                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75750.506024                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.506024                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75750.506024                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75770.586345                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75770.586345                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80324.137284                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80324.137284                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75770.586345                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75770.586345                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75770.586345                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75770.586345                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               34133                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67565                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67559                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27585                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27585                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       125037                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7766                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4596                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       124958                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7701                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4594                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4599                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133659                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133659                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33433                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4597                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133521                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133521                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         33427                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36194                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455099                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562669                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       454663                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562233                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108826                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108826                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 671495                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 671059                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16416028                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16579433                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16401756                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16565161                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315200                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2315200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18894633                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18880361                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              513                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402650                       # Request fanout histogram
+system.membus.snoop_fanout::samples            402363                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402650    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402363    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402650                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83677500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402363                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            83709500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1748500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1749000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           874312374                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           873720378                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          988164899                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          987389399                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64093300                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64116283                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 3ec6d9660..b9459834e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -1423,10 +1423,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -1453,7 +1452,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1617,12 +1616,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -1715,16 +1711,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1740,7 +1735,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1903,13 +1898,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1919,9 +1914,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1963,7 +1957,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -2044,14 +2038,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -2068,7 +2061,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -2083,7 +2076,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -2206,17 +2199,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -2268,7 +2263,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -2283,7 +2278,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index b77f15d87..c56e46cb6 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 18:09:43
-gem5 executing on e104799-lin, pid 6272
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 11:33:05
+gem5 executing on e104799-lin, pid 30938
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2837504217500 because m5_exit instruction encountered
+Exiting @ tick 2827514981500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index bfde5ebda..9f7a5e2b6 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,166 +1,166 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.837504                       # Number of seconds simulated
-sim_ticks                                2837504217500                       # Number of ticks simulated
-final_tick                               2837504217500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.827515                       # Number of seconds simulated
+sim_ticks                                2827514981500                       # Number of ticks simulated
+final_tick                               2827514981500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  94020                       # Simulator instruction rate (inst/s)
-host_op_rate                                   114023                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2216148296                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 620044                       # Number of bytes of host memory used
-host_seconds                                  1280.38                       # Real time elapsed on the host
-sim_insts                                   120381204                       # Number of instructions simulated
-sim_ops                                     145991739                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 101964                       # Simulator instruction rate (inst/s)
+host_op_rate                                   123693                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2400293976                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 620072                       # Number of bytes of host memory used
+host_seconds                                  1177.99                       # Real time elapsed on the host
+sim_insts                                   120112531                       # Number of instructions simulated
+sim_ops                                     145708890                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         1792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         2048                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1298560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1282472                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8427712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1298880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1333736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8603840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           172400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           575316                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       374464                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           183536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           661460                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       448448                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12134316                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1298560                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       172400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1470960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8568768                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12533612                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1298880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       183536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1482416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8896000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8586332                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           28                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8913564                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           32                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             22537                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             20559                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       131683                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             22542                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             21360                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       134435                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2762                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              9010                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         5851                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2936                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             10356                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         7007                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                192455                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          133887                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                198694                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          139000                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               138278                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           632                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               143391                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           724                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            68                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              457642                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              451972                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2970114                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              459372                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              471699                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      3042898                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           158                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               60758                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              202754                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       131969                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide              338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4276405                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         457642                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          60758                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             518399                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3019826                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               64911                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              233937                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       158601                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4432731                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         459372                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          64911                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             524282                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3146226                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6198                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3026016                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3019826                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          632                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                3152437                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3146226                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          724                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           68                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             457642                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             458148                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2970114                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          135                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             459372                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             477897                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      3042898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          158                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              60758                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             202768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       131969                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide             338                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7302420                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        192456                       # Number of read requests accepted
-system.physmem.writeReqs                       138278                       # Number of write requests accepted
-system.physmem.readBursts                      192456                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     138278                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12307136                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9984                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8599232                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12134380                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8586332                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      156                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu1.inst              64911                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             233951                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       158601                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7585168                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        198695                       # Number of read requests accepted
+system.physmem.writeReqs                       143391                       # Number of write requests accepted
+system.physmem.readBursts                      198695                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     143391                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12706944                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9536                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8926464                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12533676                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8913564                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      149                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3896                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          65662                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11960                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11050                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12052                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12058                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               14137                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12072                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12490                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12293                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12129                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11971                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11835                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10924                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11792                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12532                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11740                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              11264                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8435                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7998                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8830                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8684                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                8112                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8575                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8926                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8709                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8491                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8366                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8474                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8070                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8488                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8576                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8125                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7504                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          66310                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12511                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12409                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               13005                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12914                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14688                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12279                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12659                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12545                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12216                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11968                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11724                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10899                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              12000                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12901                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12154                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11674                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9120                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9128                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9608                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9301                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8579                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8797                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8898                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8634                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8555                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8430                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8386                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7930                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8700                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8975                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8498                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7937                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2837503950500                       # Total gap between requests
+system.physmem.numWrRetry                           1                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2827514698000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     551                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    3087                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  188790                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  195029                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 133887                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     61458                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     73949                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     12857                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      9980                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      8183                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7124                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      6164                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      5080                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      4433                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1271                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      792                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      552                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      233                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      214                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 139000                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     63536                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     75209                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     13408                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     10355                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      8590                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7482                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      6561                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      5366                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      4742                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1364                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      854                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      595                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      246                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      222                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                       11                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -188,159 +188,160 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2740                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4058                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4515                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5397                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5851                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7270                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8413                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8785                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10865                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     9207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8864                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7907                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7439                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      624                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      403                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      219                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2872                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::17                     4292                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::19                     5578                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27                     9482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9504                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10926                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     9080                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7724                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::43                      100                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::46                       72                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::50                       81                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::56                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       16                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       11                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        86935                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      240.482751                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     135.610645                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     303.163398                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          46710     53.73%     53.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16982     19.53%     73.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5795      6.67%     79.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3191      3.67%     83.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2666      3.07%     86.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1598      1.84%     88.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          941      1.08%     89.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          911      1.05%     90.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8141      9.36%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          86935                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6558                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.322812                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      574.114177                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6556     99.97%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6558                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6558                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.488411                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.922621                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       11.969935                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5288     80.63%     80.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             495      7.55%     88.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             103      1.57%     89.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             154      2.35%     92.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              30      0.46%     92.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             130      1.98%     94.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              43      0.66%     95.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              19      0.29%     95.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              29      0.44%     95.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              20      0.30%     96.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              10      0.15%     96.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              12      0.18%     96.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             145      2.21%     98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               7      0.11%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               5      0.08%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              33      0.50%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              10      0.15%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.05%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.03%     99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.02%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.03%     99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            10      0.15%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6558                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6213827144                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9819433394                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    961495000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       32313.19                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      4999.97                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  51063.10                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.34                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.03                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.03                       # Average system write bandwidth in MiByte/s
+system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        91952                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      235.267792                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     133.235046                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     298.839280                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          50134     54.52%     54.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17916     19.48%     74.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5936      6.46%     80.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3412      3.71%     84.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2785      3.03%     87.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1606      1.75%     88.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          997      1.08%     90.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          910      0.99%     91.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8256      8.98%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          91952                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6854                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.967610                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      561.585770                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6852     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6854                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6854                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.349577                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.863128                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       11.733584                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5532     80.71%     80.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             528      7.70%     88.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             124      1.81%     90.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             151      2.20%     92.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              37      0.54%     92.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             137      2.00%     94.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              51      0.74%     95.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              13      0.19%     95.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              30      0.44%     96.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              17      0.25%     96.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.07%     96.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              10      0.15%     96.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             152      2.22%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.07%     99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               2      0.03%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              27      0.39%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.01%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.04%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.04%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               3      0.04%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.01%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.01%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.01%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.19%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6854                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6593126991                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10315864491                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    992730000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       33207.05                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  51957.05                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           4.49                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.16                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        4.43                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.15                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.04                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.17                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     160530                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     79197                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.48                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  58.93                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8579414.12                       # Average gap between requests
-system.physmem.pageHitRate                      73.38                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  333396000                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  181912500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 765273600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                442383120                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           185331978000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80482301685                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1631904131250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1899441376155                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.405614                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2714718220190                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     94750240000                       # Time in different power states
+system.physmem.avgWrQLen                        28.41                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     165438                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     80631                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.32                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  57.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8265508.38                       # Average gap between requests
+system.physmem.pageHitRate                      72.79                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  362418840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  197748375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 803470200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                466981200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           184679495520                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            80961093990                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1625490282750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1892961490875                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.478934                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2704041495487                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     94416920000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     28035696060                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     29056546513                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  323832600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  176694375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 734658600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                428289120                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           185331978000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80147926575                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1632197442750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1899340822020                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.370176                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2715209176165                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     94750240000                       # Time in different power states
+system.physmem_1.actEnergy                  332738280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  181553625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 745180800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                436823280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           184679495520                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            80279403345                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1626088257000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1892743451850                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.401821                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2705042490853                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     94416920000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     27544740085                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     28055246647                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          192                       # Number of bytes read from this memory
@@ -366,15 +367,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               53984881                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         25029279                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          1031275                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            32703051                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               24288553                       # Number of BTB hits
+system.cpu0.branchPred.lookups               53824650                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         24914718                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          1030270                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            32581460                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               24224214                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            74.269991                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15579180                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             33867                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            74.349688                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15556762                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             33886                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -405,90 +406,81 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    71885                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               71885                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        26706                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        21113                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        24066                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        47819                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   500.773751                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  3132.734175                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-8191        46517     97.28%     97.28% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-16383          936      1.96%     99.23% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-24575          174      0.36%     99.60% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-32767          150      0.31%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-40959           13      0.03%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-49151           21      0.04%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-65535            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                    72482                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               72482                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        26840                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        21370                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        24272                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        48210                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   483.737814                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  3068.363590                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191        46935     97.36%     97.36% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383          960      1.99%     99.35% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575          127      0.26%     99.61% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767          144      0.30%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959           11      0.02%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151           24      0.05%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535            3      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::65536-73727            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::73728-81919            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::81920-90111            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::98304-106495            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::106496-114687            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::114688-122879            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        47819                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        18759                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 11059.171598                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean  9588.566879                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  7711.880133                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767        18631     99.32%     99.32% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535          106      0.57%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-131071           16      0.09%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::360448-393215            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-425983            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        18759                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  84429292764                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.657402                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.487897                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0    29095217424     34.46%     34.46% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    55270258340     65.46%     99.92% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2       29607500      0.04%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::3       15656000      0.02%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4        4826500      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::5        2762000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6        4173000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::7        1494500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8        1031000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::9         697500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10        703000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::11        393500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12       1099500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::13        296000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14        143000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::15        934000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  84429292764                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5818     79.12%     79.12% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1535     20.88%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         7353                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        71885                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total        48210                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        19223                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 10866.878219                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean  9427.660612                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  7974.318697                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767        19122     99.47%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535           77      0.40%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839           23      0.12%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::425984-458751            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        19223                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  87324939152                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.584645                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.504578                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  87261759152     99.93%     99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     45052000      0.05%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5      7883000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      5458000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      1586500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11       936000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13      1172500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15      1091000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17         1000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  87324939152                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5998     77.94%     77.94% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1698     22.06%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         7696                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        72482                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        71885                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7353                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        72482                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7696                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7353                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        79238                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7696                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        80178                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    24461690                       # DTB read hits
-system.cpu0.dtb.read_misses                     61076                       # DTB read misses
-system.cpu0.dtb.write_hits                   18142518                       # DTB write hits
-system.cpu0.dtb.write_misses                    10809                       # DTB write misses
+system.cpu0.dtb.read_hits                    24348850                       # DTB read hits
+system.cpu0.dtb.read_misses                     61646                       # DTB read misses
+system.cpu0.dtb.write_hits                   18136813                       # DTB write hits
+system.cpu0.dtb.write_misses                    10836                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3811                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      171                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2460                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3858                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      293                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  2461                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     1016                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                24522766                       # DTB read accesses
-system.cpu0.dtb.write_accesses               18153327                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      958                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                24410496                       # DTB read accesses
+system.cpu0.dtb.write_accesses               18147649                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         42604208                       # DTB hits
-system.cpu0.dtb.misses                          71885                       # DTB misses
-system.cpu0.dtb.accesses                     42676093                       # DTB accesses
+system.cpu0.dtb.hits                         42485663                       # DTB hits
+system.cpu0.dtb.misses                          72482                       # DTB misses
+system.cpu0.dtb.accesses                     42558145                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -518,56 +510,56 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    10900                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort               10900                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4234                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6533                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          133                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        10767                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean   543.187517                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  2520.119999                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095        10263     95.32%     95.32% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191          147      1.37%     96.68% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287          248      2.30%     98.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383           60      0.56%     99.54% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479           13      0.12%     99.67% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575           18      0.17%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671           11      0.10%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::28672-32767            3      0.03%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863            2      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-45055            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        10767                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         3015                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 13136.152570                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 12059.608238                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  6103.776811                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         2740     90.88%     90.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          236      7.83%     98.71% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           36      1.19%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535            2      0.07%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    11063                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort               11063                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         4358                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         6586                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          119                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        10944                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean   511.878655                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  2393.914880                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095        10440     95.39%     95.39% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191          166      1.52%     96.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287          245      2.24%     99.15% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383           55      0.50%     99.65% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479           14      0.13%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575           14      0.13%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::28672-32767            1      0.01%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863            2      0.02%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::36864-40959            4      0.04%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::45056-49151            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        10944                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         3006                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12466.400532                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11507.410615                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  5482.679017                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         2781     92.51%     92.51% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          206      6.85%     99.37% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           17      0.57%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.03%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         3015                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  20004739824                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.958205                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.200359                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0      836985000      4.18%      4.18% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    19166939824     95.81%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2         745000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3          70000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  20004739824                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         2539     88.10%     88.10% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          343     11.90%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2882                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         3006                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  18373803416                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.969102                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.173359                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0      568612000      3.09%      3.09% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    17804392916     96.90%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2         690500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         108000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  18373803416                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2539     87.95%     87.95% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          348     12.05%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2887                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        10900                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        10900                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        11063                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        11063                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2882                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2882                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total        13782                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    74221386                       # ITB inst hits
-system.cpu0.itb.inst_misses                     10900                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2887                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2887                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        13950                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    74042794                       # ITB inst hits
+system.cpu0.itb.inst_misses                     11063                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -576,109 +568,109 @@ system.cpu0.itb.flush_tlb                          66                       # Nu
 system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2623                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2625                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     2177                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     2170                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                74232286                       # ITB inst accesses
-system.cpu0.itb.hits                         74221386                       # DTB hits
-system.cpu0.itb.misses                          10900                       # DTB misses
-system.cpu0.itb.accesses                     74232286                       # DTB accesses
-system.cpu0.numCycles                       211089412                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                74053857                       # ITB inst accesses
+system.cpu0.itb.hits                         74042794                       # DTB hits
+system.cpu0.itb.misses                          11063                       # DTB misses
+system.cpu0.itb.accesses                     74053857                       # DTB accesses
+system.cpu0.numCycles                       211047403                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          21154368                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     200477778                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   53984881                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          39867733                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    180634648                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                5887980                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    163875                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               73228                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       386540                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       467083                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       106682                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 74221667                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               284223                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   5134                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         205930414                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.189818                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.306225                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          21173136                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     200001666                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   53824650                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          39780976                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    180559136                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                5880452                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    163694                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               71518                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       416219                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       467581                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       105314                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 74043107                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               284080                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   5158                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         205896824                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.187509                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.306152                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                98513446     47.84%     47.84% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                31147875     15.13%     62.96% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                14935472      7.25%     70.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                61333621     29.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                98736671     47.95%     47.95% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                31028549     15.07%     63.02% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                14918972      7.25%     70.27% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                61212632     29.73%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           205930414                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.255744                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.949729                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                26441792                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            111116512                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 60639193                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              5147176                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               2585741                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             3185045                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               362773                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             158832709                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4189276                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               2585741                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                35360438                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               13326930                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      85149071                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 56726750                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             12781484                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             141877128                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              1133387                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents              1508513                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                170712                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                 63171                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               8443572                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands          146064106                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            654194105                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       157626069                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups            10971                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            133804111                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                12259992                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           2731692                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       2584898                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 22953113                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            25474104                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           19753680                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1758400                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2611655                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 138738893                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1764680                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                136614694                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           514032                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       11572613                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     23827744                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        127449                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    205930414                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.663402                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       0.962674                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           205896824                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.255036                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.947662                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26444854                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            111284081                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 60438396                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              5147375                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               2582118                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             3181251                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               362597                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             158450982                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4186687                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               2582118                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                35356822                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               13355442                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      85192856                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 56532551                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             12877035                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             141523079                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              1131567                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents              1510730                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                170563                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                 62525                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               8538727                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands          145648252                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            652695637                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       157341344                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups            11002                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            133402169                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                12246080                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           2729481                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       2582524                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 22941481                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            25362929                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           19747073                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1756360                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2710793                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 138386443                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1765013                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                136262498                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           514521                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       11554986                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     23816746                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        127231                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    205896824                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.661800                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       0.962021                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          127115623     61.73%     61.73% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           34474239     16.74%     78.47% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           32051807     15.56%     94.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           11118185      5.40%     99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            1170514      0.57%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                 46      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          127277158     61.82%     61.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           34398562     16.71%     78.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           31970025     15.53%     94.05% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           11080468      5.38%     99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            1170573      0.57%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                 38      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      205930414                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      205896824                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               11113465     43.69%     43.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                    76      0.00%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               11103787     43.69%     43.69% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                    71      0.00%     43.69% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IntDiv                      0      0.00%     43.69% # attempts to use FU when none available
 system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     43.69% # attempts to use FU when none available
 system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     43.69% # attempts to use FU when none available
@@ -706,129 +698,129 @@ system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     43.69% # at
 system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     43.69% # attempts to use FU when none available
 system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.69% # attempts to use FU when none available
 system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     43.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               5930869     23.32%     67.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              8390890     32.99%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5926512     23.32%     67.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              8382229     32.98%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass             2315      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             92049537     67.38%     67.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult              112728      0.08%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  1      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.46% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          8149      0.01%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             91815128     67.38%     67.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult              112435      0.08%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          8235      0.01%     67.47% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     67.47% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.47% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            25196866     18.44%     85.91% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           19245098     14.09%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            25085333     18.41%     85.88% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           19239052     14.12%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             136614694                       # Type of FU issued
-system.cpu0.iq.rate                          0.647189                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   25435300                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.186183                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         505071342                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        152083684                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    132900099                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              37792                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes             13226                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses        11443                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             162023237                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                  24442                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          380983                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             136262498                       # Type of FU issued
+system.cpu0.iq.rate                          0.645649                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   25412599                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.186497                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         504310819                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        151713950                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    132552939                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              38121                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes             13270                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses        11439                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             161648054                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                  24728                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          380758                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2125903                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2726                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        20804                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1085884                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2120893                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2730                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        20852                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1081680                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       121982                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       393712                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       121274                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       393141                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               2585741                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                1952892                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               228879                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          140712950                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               2582118                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                1967503                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               225282                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          140361265                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             25474104                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            19753680                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            902814                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 28763                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents               175994                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         20804                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        314282                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       420638                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              734920                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            135458636                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             24717807                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          1084310                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             25362929                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            19747073                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            903285                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 28583                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents               172530                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         20852                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        314243                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       420118                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              734361                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            135106830                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             24606381                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          1083325                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       209377                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    43763584                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                26159060                       # Number of branches executed
-system.cpu0.iew.exec_stores                  19045777                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.641712                       # Inst execution rate
-system.cpu0.iew.wb_sent                     134853240                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    132911542                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 67798610                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                109653581                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.629646                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.618298                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       10465758                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1637231                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           673026                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    202620964                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.637065                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.337510                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       209809                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    43646202                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                26044471                       # Number of branches executed
+system.cpu0.iew.exec_stores                  19039821                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.640173                       # Inst execution rate
+system.cpu0.iew.wb_sent                     134503420                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    132564378                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 67577240                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                109379746                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.628126                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.617822                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       10448394                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1637782                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           672162                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    202592939                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.635502                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.338703                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    140811364     69.49%     69.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     34122035     16.84%     86.34% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     12973971      6.40%     92.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      3422170      1.69%     94.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      4965504      2.45%     96.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      2761485      1.36%     98.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1431161      0.71%     98.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       576287      0.28%     99.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1556987      0.77%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    141057849     69.63%     69.63% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     33954375     16.76%     86.39% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     12905235      6.37%     92.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      3389250      1.67%     94.43% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      4963565      2.45%     96.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      2666475      1.32%     98.20% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1522321      0.75%     98.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       575799      0.28%     99.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1558070      0.77%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    202620964                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           106609467                       # Number of instructions committed
-system.cpu0.commit.committedOps             129082799                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    202592939                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           106280740                       # Number of instructions committed
+system.cpu0.commit.committedOps             128748309                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      42015997                       # Number of memory references committed
-system.cpu0.commit.loads                     23348201                       # Number of loads committed
-system.cpu0.commit.membars                     664671                       # Number of memory barriers committed
-system.cpu0.commit.branches                  25482813                       # Number of branches committed
+system.cpu0.commit.refs                      41907429                       # Number of memory references committed
+system.cpu0.commit.loads                     23242036                       # Number of loads committed
+system.cpu0.commit.membars                     664627                       # Number of memory barriers committed
+system.cpu0.commit.branches                  25370057                       # Number of branches committed
 system.cpu0.commit.fp_insts                     11428                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                112616062                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             4882659                       # Number of function calls committed.
+system.cpu0.commit.int_insts                112383608                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             4877012                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        86948458     67.36%     67.36% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult         110195      0.09%     67.44% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        86722676     67.36%     67.36% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult         109969      0.09%     67.44% # Class of committed instruction
 system.cpu0.commit.op_class_0::IntDiv               0      0.00%     67.44% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     67.44% # Class of committed instruction
 system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     67.44% # Class of committed instruction
@@ -852,635 +844,635 @@ system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     67.44% #
 system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     67.44% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     67.44% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     67.44% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         8149      0.01%     67.45% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         8235      0.01%     67.45% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     67.45% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.45% # Class of committed instruction
 system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.45% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       23348201     18.09%     85.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      18667796     14.46%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       23242036     18.05%     85.50% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      18665393     14.50%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        129082799                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1556987                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   317266716                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  282405799                       # The number of ROB writes
-system.cpu0.timesIdled                         139400                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        5158998                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5463919353                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  106457624                       # Number of Instructions Simulated
-system.cpu0.committedOps                    128930956                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.982849                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.982849                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.504325                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.504325                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               146869793                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               83863812                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     9544                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                    2721                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                478325864                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                51342401                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              283146795                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes               1260752                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           750420                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          496.151485                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           38802198                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           750932                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            51.672053                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total        128748309                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1558070                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   316922543                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  281696540                       # The number of ROB writes
+system.cpu0.timesIdled                         138499                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        5150579                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5443982755                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  106128897                       # Number of Instructions Simulated
+system.cpu0.committedOps                    128596466                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.988595                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.988595                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.502868                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.502868                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               146588252                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               83723999                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     9570                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                    2716                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                476941595                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                51071402                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              282603834                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes               1261450                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           749987                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          496.992457                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           38690178                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           750499                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            51.552604                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        426635500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.151485                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.969046                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.969046                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.992457                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970688                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.970688                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          186                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         83743288                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        83743288                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     22166108                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       22166108                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     15386838                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15386838                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       316240                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       316240                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       371193                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       371193                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       369806                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       369806                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     37552946                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        37552946                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     37869186                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       37869186                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       688329                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       688329                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1970797                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1970797                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       153398                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       153398                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        26102                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        26102                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20247                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        20247                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2659126                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2659126                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2812524                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2812524                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   9979901000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   9979901000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36499508368                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  36499508368                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    419269000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    419269000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    539016500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    539016500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       316500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total       316500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  46479409368                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  46479409368                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  46479409368                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  46479409368                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     22854437                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     22854437                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     17357635                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     17357635                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       469638                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       469638                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       397295                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       397295                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       390053                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       390053                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     40212072                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     40212072                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     40681710                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     40681710                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.030118                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.030118                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.113541                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.113541                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.326630                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.326630                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.065699                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.065699                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051908                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051908                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.066128                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.066128                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.069135                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.069135                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14498.736796                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14498.736796                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18520.176542                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18520.176542                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16062.715501                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16062.715501                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26622.042772                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26622.042772                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         83515372                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        83515372                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     22054482                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       22054482                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     15385393                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      15385393                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       316703                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       316703                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       371938                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       371938                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       370232                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       370232                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     37439875                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        37439875                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     37756578                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       37756578                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       687176                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       687176                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1969830                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1969830                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       153892                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       153892                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        25692                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        25692                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        20263                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        20263                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2657006                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2657006                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2810898                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2810898                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  10005125000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  10005125000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36953361360                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  36953361360                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    414445500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    414445500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    533612500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    533612500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data       572000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total       572000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  46958486360                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  46958486360                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  46958486360                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  46958486360                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     22741658                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     22741658                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     17355223                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     17355223                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       470595                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       470595                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       397630                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       397630                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       390495                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       390495                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     40096881                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     40096881                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     40567476                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     40567476                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.030217                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.030217                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.113501                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.113501                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.327016                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.327016                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.064613                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.064613                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.051891                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.051891                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.066265                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.066265                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.069289                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.069289                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14559.770714                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14559.770714                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18759.670307                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18759.670307                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16131.305465                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16131.305465                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26334.328579                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26334.328579                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17479.205336                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 17479.205336                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16525.871199                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16525.871199                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         1220                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      5610117                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               53                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         211671                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.018868                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    26.503947                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17673.458908                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 17673.458908                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16705.866367                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16705.866367                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs         1927                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      5691402                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               46                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         211704                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    41.891304                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    26.883772                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       750420                       # number of writebacks
-system.cpu0.dcache.writebacks::total           750420                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       277928                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       277928                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1634691                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1634691                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        19352                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        19352                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1912619                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1912619                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1912619                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1912619                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       410401                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       410401                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       336106                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       336106                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       107319                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       107319                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6750                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6750                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20247                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        20247                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       746507                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       746507                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       853826                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       853826                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31838                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31838                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28498                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28498                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60336                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60336                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5125711500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5125711500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7684887402                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7684887402                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1795459000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1795459000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    109420000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    109420000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    518776500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    518776500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       309500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       309500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12810598902                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  12810598902                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14606057902                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  14606057902                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6629004500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6629004500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5396257500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5396257500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12025262000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12025262000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017957                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017957                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019364                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019364                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.228514                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.228514                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016990                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016990                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051908                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051908                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018564                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.018564                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.020988                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.020988                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12489.520006                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12489.520006                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22864.475499                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22864.475499                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16730.113028                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16730.113028                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16210.370370                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16210.370370                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25622.388502                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25622.388502                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       749987                       # number of writebacks
+system.cpu0.dcache.writebacks::total           749987                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       277260                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       277260                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1634141                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1634141                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        19045                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        19045                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1911401                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1911401                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1911401                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1911401                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       409916                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       409916                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       335689                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       335689                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       107270                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       107270                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6647                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6647                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        20263                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        20263                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       745605                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       745605                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       852875                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       852875                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31809                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31809                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28493                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28493                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60302                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60302                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   5149096500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5149096500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7778892390                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7778892390                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1793614000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1793614000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    108165500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    108165500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    513361500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    513361500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data       560000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total       560000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12927988890                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  12927988890                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  14721602890                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  14721602890                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6623643500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6623643500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5395209000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5395209000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12018852500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12018852500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.018025                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.018025                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019342                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019342                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.227945                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227945                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016717                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016717                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.051891                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.051891                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.018595                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.018595                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.021024                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.021024                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.345495                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.345495                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23172.914185                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23172.914185                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16720.555607                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16720.555607                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16272.829848                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16272.829848                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25334.920792                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25334.920792                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17160.721737                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17160.721737                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17106.597717                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17106.597717                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208210.456059                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208210.456059                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189355.656537                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189355.656537                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199304.925749                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199304.925749                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17338.924618                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17338.924618                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17261.149512                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17261.149512                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208231.742589                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208231.742589                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189352.086477                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189352.086477                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199311.009585                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199311.009585                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1310169                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.377289                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           72850689                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1310681                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            55.582319                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1312325                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.728748                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           72670068                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1312837                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            55.353458                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       8207375500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.377289                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998784                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998784                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.728748                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999470                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999470                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          138                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          135                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        149746644                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       149746644                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     72850689                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       72850689                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     72850689                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        72850689                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     72850689                       # number of overall hits
-system.cpu0.icache.overall_hits::total       72850689                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1367277                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1367277                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1367277                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1367277                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1367277                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1367277                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14942894261                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  14942894261                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14942894261                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  14942894261                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14942894261                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  14942894261                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     74217966                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     74217966                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     74217966                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     74217966                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     74217966                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     74217966                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.018422                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.018422                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.018422                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.018422                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.018422                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.018422                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10928.944362                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10928.944362                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10928.944362                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10928.944362                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10928.944362                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10928.944362                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      2021185                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        149391678                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       149391678                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     72670068                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       72670068                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     72670068                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        72670068                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     72670068                       # number of overall hits
+system.cpu0.icache.overall_hits::total       72670068                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1369337                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1369337                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1369337                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1369337                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1369337                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1369337                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14942606327                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14942606327                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14942606327                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14942606327                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14942606327                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14942606327                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     74039405                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     74039405                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     74039405                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     74039405                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     74039405                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     74039405                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.018495                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.018495                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.018495                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.018495                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.018495                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.018495                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10912.292830                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10912.292830                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10912.292830                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10912.292830                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10912.292830                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10912.292830                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      2029991                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets         1804                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           126207                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           126413                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets             15                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.014841                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.058404                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets   120.266667                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1310169                       # number of writebacks
-system.cpu0.icache.writebacks::total          1310169                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        56563                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        56563                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        56563                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        56563                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        56563                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        56563                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1310714                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1310714                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1310714                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1310714                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1310714                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1310714                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1312325                       # number of writebacks
+system.cpu0.icache.writebacks::total          1312325                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        56467                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        56467                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        56467                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        56467                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        56467                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        56467                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1312870                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1312870                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1312870                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1312870                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1312870                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1312870                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13414113616                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  13414113616                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13414113616                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  13414113616                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13414113616                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  13414113616                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  13422835685                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  13422835685                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  13422835685                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  13422835685                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  13422835685                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  13422835685                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    420651998                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    420651998                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    420651998                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    420651998                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017660                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017660                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017660                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.017660                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017660                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.017660                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10234.203355                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10234.203355                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10234.203355                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10234.203355                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10234.203355                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10234.203355                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.017732                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017732                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.017732                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.017732                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.017732                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.017732                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10224.040221                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10224.040221                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10224.040221                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10224.040221                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10224.040221                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10224.040221                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1920430                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1923198                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         2526                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1922264                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1925121                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         2600                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       245058                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          284507                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16100.171768                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3421600                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          300660                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           11.380297                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       245295                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          283525                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16106.133558                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3424599                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          299662                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           11.428206                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14677.549696                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    12.049066                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     1.660096                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1408.912909                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.895847                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000735                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000101                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.085993                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.982676                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1016                       # Occupied blocks per task id
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-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           23                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          340                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          424                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          229                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
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 system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
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+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker        14423                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        74554                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks       505100                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total       505100                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      1523954                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      1523954                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55447                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        55447                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        20261                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        20261                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            2                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       280461                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       280461                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1312845                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1312845                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       523696                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       523696                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        60131                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker        14423                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1312845                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       804157                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      2191556                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        60131                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker        14423                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1312845                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       804157                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      2191556                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.005654                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.007141                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.005942                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999982                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999982                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.268953                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.268953                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.042174                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.042174                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.186382                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.186382                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.006601                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.010612                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.042174                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.215181                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.104514                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.006601                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.010612                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.042174                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.215181                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.104514                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32802.469136                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25630.573248                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30798.932384                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3346.001405                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3346.001405                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2267.114492                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2267.114492                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       296999                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       296999                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53348.777910                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53348.777910                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 68604.672793                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 68604.672793                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34868.093044                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34868.093044                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32802.469136                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25630.573248                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 68604.672793                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42924.432603                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 49090.922949                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32802.469136                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25630.573248                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 68604.672793                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42924.432603                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 49090.922949                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs          171                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.265919                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.265919                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.041587                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.041587                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.185831                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.185831                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.005654                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.007141                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.041587                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.213763                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.103552                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.005654                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.007141                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.041587                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.213763                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.103552                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36614.705882                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26286.407767                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34213.318284                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3258.377520                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3258.377520                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2104.807265                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2104.807265                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       270249                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       270249                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55231.074014                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55231.074014                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 69236.707108                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 69236.707108                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35246.565398                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35246.565398                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36614.705882                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26286.407767                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 69236.707108                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43917.032665                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 49989.499363                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36614.705882                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26286.407767                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 69236.707108                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43917.032665                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 49989.499363                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           34                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    28.500000                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       233188                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          233188                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks       233393                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          233393                       # number of writebacks
 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            1                       # number of ReadReq MSHR hits
 system.cpu0.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        32801                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        32801                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           45                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           45                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          791                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          791                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        33060                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total        33060                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst           43                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total           43                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          786                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          786                       # number of ReadSharedReq MSHR hits
 system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           45                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        33592                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        33638                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.inst           43                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data        33846                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        33890                       # number of demand (read+write) MSHR hits
 system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            1                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst           45                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        33592                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        33638                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          404                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker          157                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          561                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       259766                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       259766                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55507                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55507                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20246                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20246                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        42727                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        42727                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        55232                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        55232                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        96937                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        96937                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          404                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          157                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        55232                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       139664                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       195457                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          404                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          157                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        55232                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       139664                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       259766                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       455223                       # number of overall MSHR misses
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+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          339                       # number of ReadReq MSHR misses
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+system.cpu0.l2cache.ReadReq_mshr_misses::total          442                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       260432                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       260432                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55446                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55446                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        20261                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        20261                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            2                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41520                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        41520                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        54554                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        54554                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        96533                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        96533                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          339                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker          103                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        54554                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       138053                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::total       193049                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          339                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker          103                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        54554                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       138053                       # number of overall MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total       453481                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         3004                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31838                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        34842                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28498                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28498                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31809                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        34813                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28493                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28493                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         3004                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60336                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63340                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10845500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      3082000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     13927500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  21538120931                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  21538120931                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1460130500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1460130500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    365635499                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    365635499                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       254999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       254999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2446283000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2446283000                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3458747998                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3458747998                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2770762497                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2770762497                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     10845500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      3082000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3458747998                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5217045497                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   8689720995                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     10845500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      3082000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3458747998                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5217045497                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  21538120931                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  30227841926                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60302                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        63306                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker     10399500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      2089500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total     12489000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  22074812822                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  22074812822                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1462138500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1462138500                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    360190499                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    360190499                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data       468498                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       468498                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2502746000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2502746000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3450718498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3450718498                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2793545998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2793545998                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker     10399500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      2089500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3450718498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5296291998                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   8759499496                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker     10399500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      2089500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3450718498                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5296291998                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  22074812822                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  30834312318                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst    398120500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6373987500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6772108000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5179265462                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5179265462                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6368846000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   6766966500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5178267462                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5178267462                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst    398120500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11553252962                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11951373462                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.006585                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.010612                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.007367                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11547113462                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11945233962                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.005638                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.007141                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.005929                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999982                       # mshr miss rate for UpgradeReq accesses
@@ -1489,127 +1481,127 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.152150                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.152150                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.042140                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.042140                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.184874                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.184874                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.006585                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.010612                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.042140                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.173460                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.089168                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.006585                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.010612                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.042140                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.173460                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.148042                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.148042                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.041554                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.041554                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.184330                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.184330                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.005638                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.007141                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.041554                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.171674                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.088088                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.005638                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.007141                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.041554                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.171674                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.207675                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24826.203209                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 82913.548852                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26305.339867                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26305.339867                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18059.641361                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18059.641361                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       254999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       254999                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57253.797365                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57253.797365                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62622.175514                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62622.175514                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28583.126123                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28583.126123                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62622.175514                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37354.260919                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44458.479333                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62622.175514                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37354.260919                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66402.273009                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.206922                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28255.656109                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84762.290433                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26370.495617                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26370.495617                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17777.528207                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17777.528207                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       234249                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       234249                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60278.082852                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60278.082852                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63253.262785                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63253.262785                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28938.767033                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28938.767033                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63253.262785                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38364.193447                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45374.487804                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63253.262785                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38364.193447                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67994.717128                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200200.625039                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194366.224671                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181741.366482                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181741.366482                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200221.509636                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194380.446959                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181738.232619                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181738.232619                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191481.917296                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188686.035081                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191488.067759                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188690.392096                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests      4274202                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2158357                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        33137                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       328935                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       324390                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4545                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        121088                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      2005227                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28498                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28498                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       739211                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      1521984                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict       210746                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       317495                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        85916                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42642                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       113550                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq            9                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           15                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       299038                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       295760                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1310714                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       595848                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3361                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3912120                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2727113                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        32094                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       130288                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6801615                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    166153536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    103357964                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        59176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       245424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         269816100                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    1019832                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      3249125                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.119614                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.328792                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests      4279317                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      2162325                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        33276                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       327449                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       323077                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4372                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        121937                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      2006842                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28493                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28493                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       739077                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      1523954                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       209281                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       317808                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        85654                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42585                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       113145                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           13                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       298662                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       295385                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1312870                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       595361                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3427                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3918545                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2723305                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        31953                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       129711                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6803514                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    166426752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    103211806                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        57692                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       240524                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         269936774                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    1020233                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      3250109                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.119815                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.328862                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           2865028     88.18%     88.18% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            379552     11.68%     99.86% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              4545      0.14%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           2865068     88.15%     88.15% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            380669     11.71%     99.87% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              4372      0.13%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       3249125                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    4275785445                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       3250109                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    4279335949                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    115025120                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    113715191                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1969663813                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1972888832                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1293120190                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1291542228                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy     17309980                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy     17537485                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     68982399                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     69622914                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups                4001540                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          2313487                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           245860                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2018567                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1484210                       # Number of BTB hits
+system.cpu1.branchPred.lookups                4034173                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2335207                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           244345                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             2038897                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                1508183                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            73.527904                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 788035                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect              5731                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            73.970534                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 793679                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              5620                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1639,87 +1631,88 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    15963                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               15963                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8440                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         3082                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore         4441                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        11522                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   609.182434                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  3297.605064                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095        10996     95.43%     95.43% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191          174      1.51%     96.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287          184      1.60%     98.54% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383           58      0.50%     99.05% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479           13      0.11%     99.16% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575           21      0.18%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671            5      0.04%     99.38% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767           47      0.41%     99.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863           21      0.18%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::36864-40959            2      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    15746                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               15746                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         8388                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         3065                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore         4293                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        11453                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   595.826421                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  3233.762475                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095        10927     95.41%     95.41% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191          176      1.54%     96.94% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287          209      1.82%     98.77% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383           35      0.31%     99.07% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479           13      0.11%     99.19% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575           23      0.20%     99.39% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671            3      0.03%     99.42% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767           42      0.37%     99.78% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863           20      0.17%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::36864-40959            4      0.03%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::53248-57343            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        11522                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         3235                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11713.446677                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 10455.998129                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  6677.373091                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         2744     84.82%     84.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          453     14.00%     98.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-49151           32      0.99%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::49152-65535            5      0.15%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         3235                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  75555560672                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.169680                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.377976                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    62765308336     83.07%     83.07% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    12774698836     16.91%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2       10450000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::3        2017500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4        1080000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::5         463500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6         984500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::7         133500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8          33500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::9          93000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10         18000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::11         18000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12         88500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::13         11000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14         24500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::15        138000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  75555560672                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1230     72.78%     72.78% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          460     27.22%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1690                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        15963                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total        11453                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         3271                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11706.970345                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 10400.215389                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7344.366479                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         2791     85.33%     85.33% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          443     13.54%     98.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-49151           31      0.95%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.09%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-147455            1      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::147456-163839            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         3271                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  78450006060                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.184600                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.390418                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    63997466940     81.58%     81.58% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    14437247120     18.40%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2       10341500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3        2133500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4         875500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5         457000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6         962000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7          87500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8          30500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9          79000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10         14000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11         48000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12         54000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13         17000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14         17500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15        175000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  78450006060                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1233     71.11%     71.11% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          501     28.89%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1734                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        15746                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        15963                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1690                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        15746                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1734                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1690                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        17653                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1734                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        17480                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3544820                       # DTB read hits
-system.cpu1.dtb.read_misses                     14056                       # DTB read misses
-system.cpu1.dtb.write_hits                    3033862                       # DTB write hits
-system.cpu1.dtb.write_misses                     1907                       # DTB write misses
+system.cpu1.dtb.read_hits                     3564995                       # DTB read hits
+system.cpu1.dtb.read_misses                     13832                       # DTB read misses
+system.cpu1.dtb.write_hits                    3032176                       # DTB write hits
+system.cpu1.dtb.write_misses                     1914                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1651                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                       51                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   364                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    1668                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                       34                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   253                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      252                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3558876                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3035769                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      227                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 3578827                       # DTB read accesses
+system.cpu1.dtb.write_accesses                3034090                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6578682                       # DTB hits
-system.cpu1.dtb.misses                          15963                       # DTB misses
-system.cpu1.dtb.accesses                      6594645                       # DTB accesses
+system.cpu1.dtb.hits                          6597171                       # DTB hits
+system.cpu1.dtb.misses                          15746                       # DTB misses
+system.cpu1.dtb.accesses                      6612917                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1749,60 +1742,55 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     6382                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                6382                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         4076                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2250                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore           56                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         6326                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean   181.394246                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  1406.259305                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-4095         6214     98.23%     98.23% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-8191           59      0.93%     99.16% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-12287           37      0.58%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-16383            6      0.09%     99.84% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-20479            4      0.06%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-24575            2      0.03%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-28671            3      0.05%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::36864-40959            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         6326                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples          893                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11600.783875                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 10727.998992                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5550.111041                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095           41      4.59%      4.59% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          147     16.46%     21.05% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          548     61.37%     82.42% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383          107     11.98%     94.40% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479           11      1.23%     95.63% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575            5      0.56%     96.19% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           19      2.13%     98.32% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767            3      0.34%     98.66% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.11%     98.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959            5      0.56%     99.33% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            3      0.34%     99.66% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::53248-57343            2      0.22%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::61440-65535            1      0.11%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total          893                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  11098487732                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.931053                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.253398                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0      765303264      6.90%      6.90% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    10333090968     93.10%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2          93500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  11098487732                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K          693     82.80%     82.80% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          144     17.20%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total          837                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     6257                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                6257                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         3920                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2276                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore           61                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         6196                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean   206.181407                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  1542.947362                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-4095         6076     98.06%     98.06% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-8191           60      0.97%     99.03% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-12287           39      0.63%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-16383            7      0.11%     99.77% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-20479            5      0.08%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::20480-24575            4      0.06%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-28671            4      0.06%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-36863            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         6196                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples          896                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11471.540179                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 10591.082273                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5713.555798                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191          197     21.99%     21.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383          650     72.54%     94.53% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575           13      1.45%     95.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767           24      2.68%     98.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959            5      0.56%     99.22% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151            2      0.22%     99.44% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-57343            4      0.45%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-73727            1      0.11%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total          896                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  13992892620                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.945402                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.227238                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0      764122764      5.46%      5.46% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    13228629356     94.54%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2         140500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  13992892620                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          692     82.87%     82.87% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          143     17.13%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total          835                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6382                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6382                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         6257                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         6257                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          837                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total          837                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         7219                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                     7191521                       # ITB inst hits
-system.cpu1.itb.inst_misses                      6382                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          835                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total          835                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         7092                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                     7247489                       # ITB inst hits
+system.cpu1.itb.inst_misses                      6257                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1811,1027 +1799,1015 @@ system.cpu1.itb.flush_tlb                          66                       # Nu
 system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     901                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     899                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                      347                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                      342                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 7197903                       # ITB inst accesses
-system.cpu1.itb.hits                          7191521                       # DTB hits
-system.cpu1.itb.misses                           6382                       # DTB misses
-system.cpu1.itb.accesses                      7197903                       # DTB accesses
-system.cpu1.numCycles                        32425900                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 7253746                       # ITB inst accesses
+system.cpu1.itb.hits                          7247489                       # DTB hits
+system.cpu1.itb.misses                           6257                       # DTB misses
+system.cpu1.itb.accesses                      7253746                       # DTB accesses
+system.cpu1.numCycles                        32825676                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           8095443                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      21322301                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    4001540                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           2272245                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     22576717                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 701366                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     87665                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               29928                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles       190452                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       273109                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles        16492                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  7191191                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               105174                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2314                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples          31620489                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.824543                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.195918                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           8001289                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      21471337                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    4034173                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           2301862                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     23036367                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 699414                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     85773                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               29291                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles       185520                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       275269                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles        17468                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  7247139                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               103562                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   2283                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples          31980684                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.819942                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.194084                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                19556210     61.85%     61.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 4372737     13.83%     75.68% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 1374906      4.35%     80.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 6316636     19.98%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                19847655     62.06%     62.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 4393311     13.74%     75.80% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 1390148      4.35%     80.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 6349570     19.85%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            31620489                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.123406                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.657570                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 6635373                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             16232056                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  7605382                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               916534                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                231144                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              619166                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               122135                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              20047523                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               930312                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                231144                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 7872130                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                2262020                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      11428772                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  7266376                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              2560047                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              19035604                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts               152359                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents               204838                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 28045                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                 12601                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               1704098                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           18785965                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             89036414                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        21967957                       # Number of integer rename lookups
+system.cpu1.fetch.rateDist::total            31980684                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.122897                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.654102                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 6559156                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             16660335                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  7594258                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               935690                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                231245                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              620374                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               121000                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              20120105                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               926045                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                231245                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 7803762                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2337008                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      11658570                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  7267589                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2682510                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              19097640                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts               153089                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents               210195                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 28229                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                 13307                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               1810658                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           18872486                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             89304984                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        22006430                       # Number of integer rename lookups
 system.cpu1.rename.fp_rename_lookups                6                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             16823959                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1962006                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            364639                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        299553                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2452699                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             3781052                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            3343720                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           554765                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          448879                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  18340674                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             508914                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 18185979                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            84059                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1788804                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      4127246                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved         41236                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     31620489                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.575133                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       0.924807                       # Number of insts issued each cycle
+system.cpu1.rename.CommittedMaps             16903103                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1969383                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            373801                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        306197                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2490350                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             3798024                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            3334408                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           558239                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          459403                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  18396455                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             514218                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 18243143                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            80370                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1798248                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined      4138161                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved         41963                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     31980684                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.570443                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       0.921832                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           20837444     65.90%     65.90% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            5408008     17.10%     83.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            3574976     11.31%     94.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            1572233      4.97%     99.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             227820      0.72%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5                  8      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           21156406     66.15%     66.15% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            5430198     16.98%     83.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            3595564     11.24%     94.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            1572256      4.92%     99.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             226251      0.71%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5                  9      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       31620489                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       31980684                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                1135208     27.60%     27.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   664      0.02%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     27.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               1335102     32.46%     60.07% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              1642689     39.93%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                1148262     27.95%     27.95% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   668      0.02%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     27.97% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               1340987     32.64%     60.61% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              1618003     39.39%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass               24      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             11205359     61.62%     61.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               26215      0.14%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          3128      0.02%     61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             3726030     20.49%     82.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            3225223     17.73%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             11255159     61.70%     61.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               26433      0.14%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     61.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          3176      0.02%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     61.86% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             3744432     20.53%     82.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            3213919     17.62%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              18185979                       # Type of FU issued
-system.cpu1.iq.rate                          0.560847                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    4113663                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.226200                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          72190169                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         20646412                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     17793804                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total              18243143                       # Type of FU issued
+system.cpu1.iq.rate                          0.555758                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    4107920                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.225176                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          72655260                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         20717149                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     17851675                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 4                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              22299618                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses              22351039                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           72560                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           72767                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       346468                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          605                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         8056                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       274891                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       344909                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          550                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         8264                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       279088                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads        35566                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        53462                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads        35940                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        54533                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                231144                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 519259                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               154115                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           18866238                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles                231245                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 541574                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               157299                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           18927437                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              3781052                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             3343720                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            266301                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  6646                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents               141712                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          8056                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         30125                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       104168                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              134293                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             17982694                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              3650056                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           187326                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts              3798024                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             3334408                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            272337                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  6587                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               145035                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          8264                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         30633                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       103644                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              134277                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             18042171                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              3670535                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           185229                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        16650                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     6820794                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 2588349                       # Number of branches executed
-system.cpu1.iew.exec_stores                   3170738                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.554578                       # Inst execution rate
-system.cpu1.iew.wb_sent                      17880625                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     17793804                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  8844802                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 13735859                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.548753                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.643921                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts        1618894                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         467678                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           126321                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     31256140                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.545936                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.299262                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                        16764                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     6830795                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 2603132                       # Number of branches executed
+system.cpu1.iew.exec_stores                   3160260                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.549636                       # Inst execution rate
+system.cpu1.iew.wb_sent                      17938795                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     17851675                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  8886835                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 13789507                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.543833                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.644464                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts        1628624                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         472255                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           125883                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     31615084                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.541371                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.295044                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     23000082     73.59%     73.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      4925249     15.76%     89.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      1442060      4.61%     93.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       538119      1.72%     95.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       452265      1.45%     97.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       297433      0.95%     98.08% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       181915      0.58%     98.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7        99730      0.32%     98.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       319287      1.02%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     23337715     73.82%     73.82% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      4942860     15.63%     89.45% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1433345      4.53%     93.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       542164      1.71%     95.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       455708      1.44%     97.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       302171      0.96%     98.10% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       181914      0.58%     98.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7        99381      0.31%     98.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       319826      1.01%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     31256140                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            13926644                       # Number of instructions committed
-system.cpu1.commit.committedOps              17063847                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     31615084                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            13986698                       # Number of instructions committed
+system.cpu1.commit.committedOps              17115488                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       6503413                       # Number of memory references committed
-system.cpu1.commit.loads                      3434584                       # Number of loads committed
-system.cpu1.commit.membars                     191656                       # Number of memory barriers committed
-system.cpu1.commit.branches                   2466066                       # Number of branches committed
+system.cpu1.commit.refs                       6508435                       # Number of memory references committed
+system.cpu1.commit.loads                      3453115                       # Number of loads committed
+system.cpu1.commit.membars                     191139                       # Number of memory barriers committed
+system.cpu1.commit.branches                   2479082                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 15229015                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              413334                       # Number of function calls committed.
+system.cpu1.commit.int_insts                 15267561                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              414980                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        10531890     61.72%     61.72% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          25416      0.15%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.87% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         3128      0.02%     61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.89% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead        3434584     20.13%     82.02% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite       3068829     17.98%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        10578262     61.81%     61.81% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          25615      0.15%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     61.95% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         3176      0.02%     61.97% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     61.97% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     61.97% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     61.97% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead        3453115     20.18%     82.15% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite       3055320     17.85%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         17063847                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events               319287                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                    48731479                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   37726129                       # The number of ROB writes
-system.cpu1.timesIdled                          54512                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         805411                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  5642014046                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   13923580                       # Number of Instructions Simulated
-system.cpu1.committedOps                     17060783                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              2.328848                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        2.328848                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.429397                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.429397                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                20183446                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               11616875                       # number of integer regfile writes
-system.cpu1.cc_regfile_reads                 64541382                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                 5516447                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads               46291245                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                345789                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements           150536                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          478.106753                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            5837857                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           150895                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            38.688207                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      89621465500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   478.106753                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.933802                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.933802                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          359                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          351                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.701172                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         12869097                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        12869097                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3072993                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3072993                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2528751                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2528751                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42878                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        42878                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70516                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        70516                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61926                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        61926                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5601744                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5601744                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      5644622                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5644622                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       178967                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       178967                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       316584                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       316584                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        23990                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        23990                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17392                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        17392                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23411                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23411                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       495551                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        495551                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       519541                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       519541                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3311567500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   3311567500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11108580447                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  11108580447                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    357363500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    357363500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    641574000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    641574000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data       819500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total       819500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  14420147947                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  14420147947                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  14420147947                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  14420147947                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3251960                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3251960                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2845335                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2845335                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66868                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        66868                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87908                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        87908                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        85337                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        85337                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      6097295                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      6097295                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      6164163                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      6164163                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.055034                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.055034                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.111264                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.111264                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.358767                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.358767                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.197843                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.197843                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274336                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274336                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.081274                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.081274                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.084284                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.084284                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18503.788408                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 18503.788408                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35088.887774                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 35088.887774                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20547.579347                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20547.579347                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27404.809705                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27404.809705                       # average StoreCondReq miss latency
+system.cpu1.commit.op_class_0::total         17115488                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events               319826                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                    49145756                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   37850174                       # The number of ROB writes
+system.cpu1.timesIdled                          55034                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         844992                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5621633430                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   13983634                       # Number of Instructions Simulated
+system.cpu1.committedOps                     17112424                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              2.347435                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.347435                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.425997                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.425997                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                20215691                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               11658166                       # number of integer regfile writes
+system.cpu1.cc_regfile_reads                 64782198                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                 5550427                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads               46731168                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                350339                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements           150744                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          471.669505                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            5845075                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           151083                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            38.687840                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     104824569000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.669505                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.921230                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.921230                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          339                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          328                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.662109                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         12896760                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        12896760                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3092594                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3092594                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2524465                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2524465                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        42426                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        42426                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        70168                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        70168                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61430                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        61430                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5617059                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5617059                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      5659485                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5659485                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       178952                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       178952                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       316827                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       316827                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        23604                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        23604                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        17348                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        17348                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23299                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23299                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       495779                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        495779                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       519383                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       519383                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   3441746500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   3441746500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11862734947                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  11862734947                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    362002500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    362002500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    631001500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    631001500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      1169000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      1169000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  15304481447                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  15304481447                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  15304481447                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  15304481447                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3271546                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3271546                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2841292                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2841292                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66030                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        66030                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        87516                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        87516                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84729                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        84729                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      6112838                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      6112838                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      6178868                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      6178868                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.054700                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.054700                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.111508                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.111508                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.357474                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.357474                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.198227                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.198227                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.274983                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.274983                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.081105                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.081105                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.084058                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.084058                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19232.791475                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 19232.791475                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37442.310621                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 37442.310621                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20867.102836                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20867.102836                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27082.771793                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27082.771793                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29099.220760                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 29099.220760                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27755.553358                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 27755.553358                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs          351                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      1652938                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs               24                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets          30246                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    14.625000                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    54.649805                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30869.563751                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 30869.563751                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29466.658414                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 29466.658414                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs          358                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      1808008                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs               31                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets          30216                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    11.548387                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    59.836113                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       150537                       # number of writebacks
-system.cpu1.dcache.writebacks::total           150537                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        62639                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        62639                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       238187                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       238187                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12480                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12480                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       300826                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       300826                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       300826                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       300826                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       116328                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       116328                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        78397                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        78397                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23066                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        23066                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4912                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4912                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23411                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23411                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       194725                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       194725                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       217791                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       217791                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3053                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3053                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2412                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2412                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5465                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5465                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1734233000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1734233000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2786620456                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2786620456                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    403892500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    403892500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     94891500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     94891500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    618171000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    618171000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data       811500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total       811500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4520853456                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4520853456                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4924745956                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4924745956                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    433886500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    433886500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    300722000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    300722000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    734608500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    734608500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035772                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035772                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027553                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027553                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.344948                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.344948                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055877                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.055877                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274336                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274336                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031936                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.031936                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035332                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.035332                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14908.130459                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14908.130459                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35544.988405                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35544.988405                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17510.296540                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17510.296540                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19318.302117                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19318.302117                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26405.151425                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26405.151425                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       150744                       # number of writebacks
+system.cpu1.dcache.writebacks::total           150744                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        62223                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        62223                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       237836                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       237836                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        12586                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        12586                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       300059                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       300059                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       300059                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       300059                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       116729                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       116729                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        78991                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        78991                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        22881                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        22881                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4762                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4762                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23299                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23299                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       195720                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       195720                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       218601                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       218601                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3069                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3069                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2411                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2411                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5480                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5480                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1778715000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1778715000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2939877456                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2939877456                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    425185000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    425185000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     98534500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     98534500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    607713500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    607713500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      1158000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      1158000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4718592456                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4718592456                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5143777456                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5143777456                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    437774500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    437774500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    301405500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    301405500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    739180000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    739180000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035680                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035680                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027801                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027801                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.346524                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.346524                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.054413                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.054413                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.274983                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.274983                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.032018                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.032018                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035379                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035379                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15237.987133                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15237.987133                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37217.878695                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 37217.878695                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18582.448320                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18582.448320                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 20691.831163                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 20691.831163                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26083.243916                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26083.243916                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23216.605243                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23216.605243                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.256503                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22612.256503                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142118.080576                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142118.080576                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124677.446103                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124677.446103                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134420.585544                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134420.585544                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24108.892581                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24108.892581                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23530.438818                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23530.438818                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142644.020854                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142644.020854                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125012.650353                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125012.650353                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134886.861314                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134886.861314                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           559207                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          499.428858                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            6611589                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           559719                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            11.812336                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      79408312500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.428858                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975447                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.975447                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           551908                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          499.384443                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            6675021                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           552420                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            12.083236                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      79408503500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.384443                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975360                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.975360                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::2          494                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         14941719                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        14941719                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      6611589                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        6611589                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      6611589                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         6611589                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      6611589                       # number of overall hits
-system.cpu1.icache.overall_hits::total        6611589                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       579409                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       579409                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       579409                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        579409                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       579409                       # number of overall misses
-system.cpu1.icache.overall_misses::total       579409                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5260271690                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5260271690                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5260271690                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5260271690                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5260271690                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5260271690                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      7190998                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      7190998                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      7190998                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      7190998                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      7190998                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      7190998                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.080574                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.080574                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.080574                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.080574                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.080574                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.080574                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9078.684815                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9078.684815                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9078.684815                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9078.684815                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9078.684815                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9078.684815                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       508858                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs            41527                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.253666                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses         15046317                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        15046317                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      6675021                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        6675021                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      6675021                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         6675021                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      6675021                       # number of overall hits
+system.cpu1.icache.overall_hits::total        6675021                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       571924                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       571924                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       571924                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        571924                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       571924                       # number of overall misses
+system.cpu1.icache.overall_misses::total       571924                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5247903529                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5247903529                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5247903529                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5247903529                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5247903529                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5247903529                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      7246945                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      7246945                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      7246945                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      7246945                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      7246945                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      7246945                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.078919                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.078919                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.078919                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.078919                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.078919                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.078919                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9175.875692                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  9175.875692                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9175.875692                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  9175.875692                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9175.875692                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  9175.875692                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       518390                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          438                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs            40965                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              3                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    12.654461                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          146                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       559207                       # number of writebacks
-system.cpu1.icache.writebacks::total           559207                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        19686                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        19686                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        19686                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        19686                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        19686                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        19686                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       559723                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       559723                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       559723                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       559723                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       559723                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       559723                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       551908                       # number of writebacks
+system.cpu1.icache.writebacks::total           551908                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        19497                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        19497                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        19497                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        19497                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        19497                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        19497                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       552427                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       552427                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       552427                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       552427                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       552427                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       552427                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          103                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          103                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          103                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          103                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4814325924                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4814325924                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4814325924                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4814325924                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4814325924                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4814325924                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4796273338                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4796273338                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4796273338                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4796273338                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4796273338                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4796273338                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14117999                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14117999                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14117999                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total     14117999                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.077837                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.077837                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.077837                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.077837                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.077837                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.077837                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8601.265133                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8601.265133                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8601.265133                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8601.265133                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8601.265133                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8601.265133                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.076229                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.076229                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.076229                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.076229                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.076229                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.076229                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8682.184864                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8682.184864                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8682.184864                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8682.184864                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8682.184864                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8682.184864                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137067.951456                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137067.951456                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       109440                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       110020                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          525                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       114901                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       115599                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          633                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        49988                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           32853                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       15122.347980                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1241496                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           48030                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           25.848345                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        47913                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           38341                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       15301.887572                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1226523                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           53480                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           22.934237                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14684.371026                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    11.723090                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.949001                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   423.304863                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.896263                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000716                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000180                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.025836                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.922995                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          986                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           52                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14139                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          660                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          322                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           24                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          776                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14854.525753                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     7.568708                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     3.883063                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   435.910048                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.906648                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000462                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000237                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.026606                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.933953                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          923                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           61                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14155                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2           11                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          616                       # Occupied blocks per task id
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 system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         2695                       # Occupied blocks per task id
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+system.cpu1.l2cache.overall_accesses::total       766566                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.036368                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.041034                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.038060                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999957                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999957                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.653446                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.653446                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.018631                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.018631                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.450142                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.450142                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.034488                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.040263                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.018631                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.502437                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.140538                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.034488                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.040263                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.018631                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.502437                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.140538                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22119.266055                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19933.673469                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21239.041096                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2269.835535                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2269.835535                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2700.546868                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2700.546868                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       199625                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       199625                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53771.207203                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53771.207203                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59187.427982                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59187.427982                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22839.799233                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22839.799233                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22119.266055                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19933.673469                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59187.427982                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33187.450046                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 35599.974239                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22119.266055                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19933.673469                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59187.427982                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33187.450046                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 35599.974239                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs           60                       # number of cycles access was blocked
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.661582                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.661582                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.019916                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.019916                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.458149                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.458149                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.036368                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.041034                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.019916                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.510600                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.144896                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.036368                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.041034                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.019916                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.510600                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.144896                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22045.054945                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20018.835616                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21253.012048                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2146.690640                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2146.690640                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2646.916177                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2646.916177                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 57453.376933                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 57453.376933                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59856.298764                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59856.298764                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23598.711832                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23598.711832                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22045.054945                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20018.835616                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59856.298764                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34908.596176                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 37287.898813                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22045.054945                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20018.835616                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59856.298764                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34908.596176                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 37287.898813                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs           52                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               2                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           30                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           26                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        26302                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           26302                       # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks        31325                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           31325                       # number of writebacks
 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            1                       # number of ReadReq MSHR hits
 system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker           17                       # number of ReadReq MSHR hits
 system.cpu1.l2cache.ReadReq_mshr_hits::total           18                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1057                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         1057                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            3                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           31                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           31                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         1215                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         1215                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            5                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data           35                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total           35                       # number of ReadSharedReq MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker           17                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            3                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1088                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         1109                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            5                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         1250                       # number of demand (read+write) MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::total         1273                       # number of demand (read+write) MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker            1                       # number of overall MSHR hits
 system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker           17                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            3                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1088                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         1109                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          435                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          277                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          712                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        19626                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        19626                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29064                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29064                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23406                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23406                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31597                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        31597                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        10425                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        10425                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        64925                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        64925                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          435                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          277                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        10425                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data        96522                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       107659                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          435                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          277                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        10425                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data        96522                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        19626                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       127285                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            5                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         1250                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         1273                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          454                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          275                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total          729                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        21206                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        21206                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        29477                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        29477                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23299                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23299                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31966                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total        31966                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst        10997                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total        10997                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        66107                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        66107                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          454                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          275                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst        10997                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data        98073                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total       109799                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          454                       # number of overall MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst        10997                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data        98073                       # number of overall MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total       131005                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          103                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3053                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3156                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2412                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2412                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3069                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3172                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2411                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2411                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          103                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5465                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5568                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7015500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3985000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11000500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1124452152                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1124452152                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    598927500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    598927500                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    441961500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    441961500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data       750500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total       750500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1488249500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1488249500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    554608999                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    554608999                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1092439499                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1092439499                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7015500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3985000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    554608999                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2580688999                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   3146298498                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7015500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3985000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    554608999                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2580688999                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1124452152                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   4270750650                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5480                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5583                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      7288000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      3982000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total     11270000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher   1346298482                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total   1346298482                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    600399000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    600399000                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    432262000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    432262000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      1075500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1075500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1610738500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1610738500                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    592445999                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    592445999                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1162092498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1162092498                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      7288000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      3982000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    592445999                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2772830998                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   3376546997                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      7288000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      3982000                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    592445999                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2772830998                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher   1346298482                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total   4722845479                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13345000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    409170500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    422515500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    282391996                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    282391996                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    413019000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    426364000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    283076496                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    283076496                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13345000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    691562496                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    704907496                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.034409                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.037935                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.035700                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    696095496                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    709440496                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.036288                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.038645                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.037143                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999957                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999957                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.632294                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.632294                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018625                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.018625                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.449928                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.449928                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.034409                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.037935                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.018625                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.496837                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.139105                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.034409                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.037935                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.018625                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.496837                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.637357                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.637357                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.019907                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.019907                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.457906                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.457906                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.036288                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.038645                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.019907                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.504174                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.143235                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.036288                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.038645                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.019907                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.504174                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.164464                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15450.140449                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57294.005503                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57294.005503                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20607.194467                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20607.194467                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18882.401948                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18882.401948                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       187625                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       187625                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47100.974776                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47100.974776                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53199.903981                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53199.903981                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16826.176342                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16826.176342                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53199.903981                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26736.795746                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29224.667682                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53199.903981                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26736.795746                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57294.005503                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33552.662529                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.170899                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        14480                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15459.533608                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63486.677450                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20368.388913                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20368.388913                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18552.813425                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18552.813425                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50389.116561                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50389.116561                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53873.419933                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53873.419933                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17578.962863                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17578.962863                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker        14480                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53873.419933                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28273.133258                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30752.074217                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker        14480                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53873.419933                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28273.133258                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36050.879577                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134022.436947                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133876.901141                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117077.941957                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117077.941957                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134577.712610                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134414.880202                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117410.408959                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117410.408959                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126543.915096                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126599.765805                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127024.725547                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127071.555794                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests      1523677                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests       769701                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12410                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       171538                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       169858                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1680                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq         26336                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       768409                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         2412                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2412                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       120538                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean       604293                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict        90253                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        23776                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        71073                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41600                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        85044                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           11                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           15                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        57287                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        54410                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       559723                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       223005                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq           24                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1668415                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       728070                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        15878                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        27246                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2439609                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     70944752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24680600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        29208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        50568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          95705128                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     366083                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples      1123000                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.171945                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.381277                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests      1510050                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests       763127                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        12108                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       172945                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       171137                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         1808                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq         26162                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       760461                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2411                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2411                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       125070                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       598066                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        92914                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        26023                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        70036                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        41455                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        85358                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           12                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        57012                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        54811                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       552427                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       220569                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq           25                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1646728                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       729194                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        15588                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        27029                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2418539                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     70023728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24695290                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        28464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        50044                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          94797526                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     371473                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples      1121639                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.173444                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.382865                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0            931586     82.96%     82.96% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            189734     16.90%     99.85% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              1680      0.15%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0            928905     82.82%     82.82% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            190926     17.02%     99.84% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              1808      0.16%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total       1123000                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1483438992                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total       1121639                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1469339490                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     80062850                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     79587436                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    839820234                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    828867751                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    323064197                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    323642126                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy      8585980                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy      8481980                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy     14617972                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy     14527980                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                31018                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               31018                       # Transaction distribution
@@ -2839,6 +2815,7 @@ system.iobus.trans_dist::WriteReq               59424                       # Tr
 system.iobus.trans_dist::WriteResp              59424                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56618                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
@@ -2854,16 +2831,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       107932                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  180884                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71562                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
@@ -2879,26 +2854,25 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       162812                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2484060                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             40405000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             40431500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               111500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                31500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               324000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                15500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                31500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                90500                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               581000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                15500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy                89500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer8.occupancy               582500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               22500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
@@ -2919,31 +2893,25 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6141000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6146000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              169500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            34110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            34081000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           186335542                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              124500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186321543                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               31500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84732000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36776000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36458                       # number of replacements
-system.iocache.tags.tagsinuse               14.554671                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               14.549511                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256310853000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.554671                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.909667                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.909667                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         256320229000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide    14.549511                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.909344                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.909344                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2957,14 +2925,14 @@ system.iocache.demand_misses::realview.ide          252                       #
 system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          252                       # number of overall misses
 system.iocache.overall_misses::total              252                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32664376                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32664376                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4736716167                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4736716167                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32664376                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32664376                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32664376                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32664376                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     32965876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     32965876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4737835666                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4737835666                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     32965876                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     32965876                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     32965876                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     32965876                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -2981,19 +2949,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 129620.539683                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 129620.539683                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130761.819981                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130761.819981                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 129620.539683                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 129620.539683                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 129620.539683                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 129620.539683                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           734                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 130816.968254                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 130816.968254                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130792.724879                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130792.724879                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130816.968254                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130816.968254                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130816.968254                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130816.968254                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           713                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                   91                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.065934                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     7.835165                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -3007,14 +2975,14 @@ system.iocache.demand_mshr_misses::realview.ide          252
 system.iocache.demand_mshr_misses::total          252                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          252                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          252                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     20064376                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     20064376                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2925516167                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2925516167                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     20064376                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     20064376                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     20064376                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     20064376                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     20365876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     20365876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2926635666                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2926635666                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     20365876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     20365876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     20365876                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     20365876                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -3023,602 +2991,602 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79620.539683                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 79620.539683                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80761.819981                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80761.819981                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 79620.539683                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 79620.539683                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 79620.539683                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 79620.539683                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80816.968254                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 80816.968254                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80792.724879                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80792.724879                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 80816.968254                       # average overall mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::realview.ide 80816.968254                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 80816.968254                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   124125                       # number of replacements
-system.l2c.tags.tagsinuse                63228.123175                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     440353                       # Total number of references to valid blocks.
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-system.l2c.tags.avg_refs                     2.339739                       # Average number of references to valid blocks.
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+system.l2c.tags.tagsinuse                63152.978828                       # Cycle average of tags in use
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 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
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-system.l2c.tags.occ_blocks::cpu0.itb.walker     1.063314                       # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu0.data     2863.958869                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34966.595872                       # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu1.inst     1640.209162                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      501.782314                       # Average occupied blocks per requestor
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+system.l2c.WritebackDirty_hits::total          264718                       # number of WritebackDirty hits
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-system.l2c.UpgradeReq_miss_latency::cpu1.data      5718000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     36390500                       # number of UpgradeReq miss cycles
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-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      4014500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      9625000                       # number of SCUpgradeReq miss cycles
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-system.l2c.ReadExReq_miss_latency::total   2757796000                       # number of ReadExReq miss cycles
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 system.l2c.demand_miss_latency::cpu0.itb.walker       388000                       # number of demand (read+write) miss cycles
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 system.l2c.overall_miss_latency::cpu0.itb.walker       388000                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::total    28839065081                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       259490                       # number of WritebackDirty accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::total       0.261870                       # miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_miss_rate::total     0.412743                       # miss rate for SCUpgradeReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.157197                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.732038                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.133333                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.151510                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::total     0.532610                       # miss rate for ReadSharedReq accesses
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-system.l2c.demand_miss_rate::cpu1.inst       0.256715                       # miss rate for demand accesses
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-system.l2c.overall_miss_rate::cpu0.data      0.275999                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.133333                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.083333                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.256715                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.564944                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.678692                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.549759                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3150.097566                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2311.236863                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2980.140857                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6523.837209                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  3034.391534                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  4409.070087                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151701.923077                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133108.138377                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 143905.030265                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 147428.571429                       # average ReadSharedReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst   2598359001                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   3072845000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  21242920310                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       929500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker       133000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    386572500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1389545500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher   1271879384                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    29968413195                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks       264718                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total       264718                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        42212                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4683                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           46895                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         2961                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data         2171                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          5132                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data        15793                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        10121                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            25914                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker          215                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           77                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst        54554                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data        58049                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       181294                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           37                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           16                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.inst        10995                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data         7755                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher        10086                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total       323078                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker          215                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker           77                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst           54554                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data           73842                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.l2cache.prefetcher       181294                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker           37                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker           16                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           10995                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           17876                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher        10086                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              348992                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker          215                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker           77                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst          54554                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data          73842                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       181294                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker           37                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker           16                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          10995                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          17876                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher        10086                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             348992                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.228134                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.491138                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.254398                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.266464                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.565638                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.393024                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.745204                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.889438                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.801536                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.148837                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.038961                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.358764                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.159813                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.189189                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.062500                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.259482                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.173179                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.540696                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.148837                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.038961                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.358764                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.285014                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.189189                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.062500                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.259482                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.578709                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.560064                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.148837                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.038961                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.358764                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.285014                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.189189                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.062500                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.259482                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.578709                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.560064                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2587.123572                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2582.826087                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2586.295054                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  5210.392902                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2245.928339                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  3405.552801                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 151124.309627                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133639.524550                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 143546.531221                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 151281.250000                       # average ReadSharedReq miss latency
 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132528.009464                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138226.416128                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 156825.506022                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 135166.666667                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker       132500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134034.192825                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140717.030114                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 180077.143394                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 153381.335676                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 147428.571429                       # average overall miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132758.992489                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139513.096906                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132785.714286                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker       133000                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 135496.845426                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138884.959047                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 154486.642939                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 151281.250000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 132528.009464                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 145629.795112                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 156825.506022                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 135166.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker       132500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 134034.192825                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 133922.380264                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 180077.143394                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 152421.514545                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 147428.571429                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 132758.992489                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 146006.129431                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132785.714286                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 135496.845426                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 134320.492992                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 153324.055270                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 151281.250000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker 129333.333333                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 132528.009464                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 145629.795112                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 156825.506022                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 135166.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker       132500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 134034.192825                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 133922.380264                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 180077.143394                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 152421.514545                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.overall_avg_miss_latency::cpu0.inst 132758.992489                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 146006.129431                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 157831.968542                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132785.714286                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 135496.845426                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 134320.492992                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181515.539318                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 153324.055270                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs               244                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        3                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     81.333333                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               97681                       # number of writebacks
-system.l2c.writebacks::total                    97681                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            3                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            5                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  8                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 8                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         3022                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         3022                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         9737                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         2474                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        12211                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          860                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data         1323                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         2183                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        11128                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         8036                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         19164                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker           28                       # number of ReadSharedReq MSHR misses
+system.l2c.writebacks::writebacks              102794                       # number of writebacks
+system.l2c.writebacks::total                   102794                       # number of writebacks
+system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           23                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu1.inst            8                       # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total           31                       # number of ReadSharedReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst             23                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 31                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst            23                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                31                       # number of overall MSHR hits
+system.l2c.CleanEvict_mshr_misses::writebacks         3318                       # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total         3318                       # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         9630                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         2300                       # number of UpgradeReq MSHR misses
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 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.570046                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.261870                       # mshr miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.574468                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.412743                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.726039                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.839444                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.769639                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.102564                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.021739                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.353853                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.157197                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.732038                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.133333                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.083333                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.256236                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.151510                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.678692                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.532585                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.102564                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.021739                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.353853                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.275999                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.732038                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.133333                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.083333                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.256236                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.564944                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.678692                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.549735                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.102564                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.021739                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.353853                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.275999                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.732038                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.133333                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.083333                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.256236                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.564944                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.678692                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.549735                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75545.445209                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75297.493937                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75495.209238                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77613.373256                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76659.486017                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77035.273019                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141701.923077                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123108.138377                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 133905.030265                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.228134                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.491138                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.254398                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.266464                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.565638                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.393024                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.745204                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.889438                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.801536                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.148837                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.038961                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.358342                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.159813                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.189189                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.062500                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.258754                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.173179                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.540600                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.148837                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.038961                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.358342                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.285014                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.189189                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.062500                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.258754                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.578709                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.559976                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.148837                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.038961                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.358342                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.285014                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.742396                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.189189                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.062500                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.258754                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.578709                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.694725                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.559976                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75438.058152                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75180.217391                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75388.348701                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77541.192649                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76586.319218                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76959.841844                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141124.309627                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123639.524550                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 133546.531221                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122524.560018                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128226.416128                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124118.869337                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130717.030114                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143383.206188                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122782.827817                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129513.096906                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125656.590510                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128884.959047                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144495.643980                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122524.560018                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135629.795112                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124118.869337                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123922.380264                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 142423.155007                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122782.827817                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136006.129431                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125656.590510                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124320.492992                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 143331.915216                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122524.560018                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135629.795112                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124118.869337                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123922.380264                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 142423.155007                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122782.827817                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136006.129431                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125656.590510                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124320.492992                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 143331.915216                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182200.248131                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182221.195259                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116137.868852                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171355.441505                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164737.386413                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100066.751244                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159690.942802                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116692.922374                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171386.248749                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164734.444881                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100401.287433                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159715.442726                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173952.160203                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173958.617260                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109040.919810                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 166122.879936                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109521.271499                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 166150.430305                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               37995                       # Transaction distribution
-system.membus.trans_dist::ReadResp             208280                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30910                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30910                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       133887                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            14956                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            74359                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          40536                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14484                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             38707                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            19074                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        170286                       # Transaction distribution
+system.membus.trans_dist::ReadReq               37982                       # Transaction distribution
+system.membus.trans_dist::ReadResp             212889                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30904                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30904                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       139000                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            16061                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            72768                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          40424                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           14027                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             40474                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            20691                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        174908                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107932                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           40                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13724                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       655631                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       777327                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13686                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       672318                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       793976                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108934                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108934                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 886261                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 902910                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162812                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27448                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18402504                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18593084                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27372                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     19129032                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     19319536                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20911228                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           120617                       # Total snoops (count)
-system.membus.snoop_fanout::samples            578108                       # Request fanout histogram
+system.membus.pkt_size::total                21637680                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           119522                       # Total snoops (count)
+system.membus.snoop_fanout::samples            588990                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  578108    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  588990    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              578108                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            81934000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              588990                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            81993500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               27500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11360491                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11365991                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           977870256                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          1011151356                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1121733386                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1153249220                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64044757                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64060493                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3661,56 +3629,56 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests       989446                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       534228                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       146104                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          20085                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        19207                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops          878                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              37998                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            475278                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30910                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30910                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       393382                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           89983                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          108688                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         43642                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         152330                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           15                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           15                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50244                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50244                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       437296                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests       995943                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       537996                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       143832                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          21510                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        20627                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops          883                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              37985                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            476927                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30904                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30904                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       403719                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           92623                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          107653                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         43539                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         151192                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           23                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           23                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50791                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50791                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       438958                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1240411                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       256111                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1496522                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34963008                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3945788                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               38908796                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          440874                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           905624                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.341764                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.476341                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1238290                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       270024                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1508314                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     35030546                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      4521886                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               39552432                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          444179                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           913848                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.335282                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.474132                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 596992     65.92%     65.92% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 307754     33.98%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    878      0.10%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 608334     66.57%     66.57% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 304631     33.33%     99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    883      0.10%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             905624                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          871666747                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             913848                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          880459353                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           356120                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           356618                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         657174901                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         654259891                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         205942747                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         211427270                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1875                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                    1860                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2747                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    2725                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index cabf2a62b..8e4de7f55 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -749,10 +749,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -779,7 +778,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -906,12 +905,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -1004,16 +1000,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1029,7 +1024,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1192,13 +1187,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1208,9 +1203,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1252,7 +1246,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1333,14 +1327,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1357,7 +1350,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1372,7 +1365,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1495,17 +1488,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1557,7 +1552,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1572,7 +1567,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
index 22e00c78f..c059ed755 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 17:56:31
-gem5 executing on e104799-lin, pid 4788
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 13:05:09
+gem5 executing on e104799-lin, pid 8022
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2832917624000 because m5_exit instruction encountered
+Exiting @ tick 2832912592000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index a6a7b9a57..aa70a7365 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.832918                       # Number of seconds simulated
-sim_ticks                                2832917624000                       # Number of ticks simulated
-final_tick                               2832917624000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.832913                       # Number of seconds simulated
+sim_ticks                                2832912592000                       # Number of ticks simulated
+final_tick                               2832912592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  92147                       # Simulator instruction rate (inst/s)
-host_op_rate                                   111765                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2308459523                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 585884                       # Number of bytes of host memory used
-host_seconds                                  1227.19                       # Real time elapsed on the host
-sim_insts                                   113081477                       # Number of instructions simulated
-sim_ops                                     137157144                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  98871                       # Simulator instruction rate (inst/s)
+host_op_rate                                   119922                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2476970660                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 585504                       # Number of bytes of host memory used
+host_seconds                                  1143.70                       # Real time elapsed on the host
+sim_insts                                   113079343                       # Number of instructions simulated
+sim_ops                                     137154534                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker         1344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1316032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9392488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1316096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9383208                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10711336                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1316032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1316032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8002368                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10702120                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1316096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1316096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7997312                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8019892                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8014836                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker           21                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            8                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              22810                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             147278                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              22811                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             147133                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                170132                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          125037                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                169988                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124958                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               129418                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               129339                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            474                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker            181                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               464550                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3315482                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               464573                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3312212                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3781026                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          464550                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             464550                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2824780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3777780                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          464573                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             464573                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2823000                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6186                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2830965                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2824780                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2829186                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2823000                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           474                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker           181                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              464550                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3321668                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              464573                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3318398                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6611992                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        170133                       # Number of read requests accepted
-system.physmem.writeReqs                       129418                       # Number of write requests accepted
-system.physmem.readBursts                      170133                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     129418                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10877696                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10816                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8031936                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10711400                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8019892                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      169                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6606966                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        169989                       # Number of read requests accepted
+system.physmem.writeReqs                       129339                       # Number of write requests accepted
+system.physmem.readBursts                      169989                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     129339                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10867584                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     11712                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8027584                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10702184                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8014836                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      183                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          48557                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11298                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10506                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10925                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11199                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12883                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10202                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               10845                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11219                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10577                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10527                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10037                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8948                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9970                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10631                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9988                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10209                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8496                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7860                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8364                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8532                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7663                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7568                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8029                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8274                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8070                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7909                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7508                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6646                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7551                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8006                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7465                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7558                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          48490                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11395                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10615                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11052                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11362                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12761                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10093                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10904                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11084                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10554                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10523                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10030                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8841                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9967                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10661                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9878                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10086                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8599                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7964                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8486                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8679                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7544                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7468                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8077                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8182                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8055                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7911                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7496                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6568                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7556                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8042                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7357                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7447                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2832917392000                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2832912360000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                    2996                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166581                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166437                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 125037                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    150592                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     16496                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      2133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       726                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 124958                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    150468                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     16446                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2150                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       725                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
@@ -159,156 +159,156 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2033                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5707                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7704                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8224                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8301                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9858                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7922                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6870                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6611                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6539                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       47                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2028                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6673                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6911                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7819                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9948                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7795                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7406                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6937                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6529                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      304                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      260                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       20                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::59                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       36                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        62145                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      304.281406                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.810971                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.663684                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          23300     37.49%     37.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14989     24.12%     61.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6559     10.55%     72.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3523      5.67%     77.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2511      4.04%     81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1609      2.59%     84.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1592      2.56%     87.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1065      1.71%     88.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6997     11.26%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          62145                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6266                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        27.121768                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      563.971651                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6265     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::60                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        62097                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      304.283685                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.850271                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     324.574400                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          23280     37.49%     37.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14997     24.15%     61.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6479     10.43%     72.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3584      5.77%     77.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2530      4.07%     81.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1603      2.58%     84.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1574      2.53%     87.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1048      1.69%     88.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7002     11.28%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          62097                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6262                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.116097                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      564.155612                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6261     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6266                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6266                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.028567                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.454463                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.210745                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5460     87.14%     87.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             110      1.76%     88.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              30      0.48%     89.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             168      2.68%     92.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              26      0.41%     92.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             137      2.19%     94.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              53      0.85%     95.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              15      0.24%     95.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              11      0.18%     95.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              21      0.34%     96.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               6      0.10%     96.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               7      0.11%     96.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             165      2.63%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.08%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              23      0.37%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.03%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            12      0.19%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.03%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6266                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2116809750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5303634750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    849820000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12454.46                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6262                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6262                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.030501                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.464444                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.039261                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5446     86.97%     86.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             116      1.85%     88.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              36      0.57%     89.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             167      2.67%     92.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              22      0.35%     92.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             138      2.20%     94.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              54      0.86%     95.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              12      0.19%     95.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              19      0.30%     95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              16      0.26%     96.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.10%     96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               3      0.05%     96.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             160      2.56%     98.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.10%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               9      0.14%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              25      0.40%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               2      0.03%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.05%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.02%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.21%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6262                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2134847750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5318710250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    849030000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12572.28                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31204.46                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31322.28                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.84                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.84                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.83                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.78                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.83                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.52                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     139542                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93775                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.70                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9457212.27                       # Average gap between requests
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.05                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     139313                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93826                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.04                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.79                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9464241.10                       # Average gap between requests
 system.physmem.pageHitRate                      78.96                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  246546720                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  134524500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 694792800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                419813280                       # Energy for write commands per rank (pJ)
+system.physmem_0.actEnergy                  247680720                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  135143250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 696267000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                421193520                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           185031927600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            83588992920                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1626422631000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1896539228820                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.466691                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2705562728250                       # Time in different power states
+system.physmem_0.actBackEnergy            83693103705                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1626331305750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1896556621545                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.472831                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2705407276500                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     94597100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     32757782250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     32908202000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  223269480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  121823625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 630918600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                393420240                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                  221772600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  121006875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 628212000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                391599360                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           185031927600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            81878542335                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1627923026250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1896202928130                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.347979                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2708066096500                       # Time in different power states
+system.physmem_1.actBackEnergy            81799663455                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1627992218250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1896186400140                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.342145                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2708183660500                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     94597100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     30247332250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     30129768250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          128                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           128                       # Number of bytes read from this memory
@@ -328,15 +328,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                46858822                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          24018425                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1233385                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             29501817                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21322160                       # Number of BTB hits
+system.cpu.branchPred.lookups                46857763                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          24018162                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1233841                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             29502900                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                21322687                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             72.274057                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                11724285                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              33905                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             72.273190                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                11723693                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              33902                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -367,84 +367,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                     71435                       # Table walker walks requested
-system.cpu.dtb.walker.walksShort                71435                       # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29241                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22400                       # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore        19794                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples        51641                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean   426.153638                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev  2576.445985                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-4095        49864     96.56%     96.56% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::4096-8191          585      1.13%     97.69% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::8192-12287          525      1.02%     98.71% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::12288-16383          340      0.66%     99.37% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                     71876                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                71876                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1        29748                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2        22357                       # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore        19771                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples        52105                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean   423.395068                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev  2574.283993                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-4095        50327     96.59%     96.59% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::4096-8191          585      1.12%     97.71% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::8192-12287          525      1.01%     98.72% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::12288-16383          339      0.65%     99.37% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::16384-20479           52      0.10%     99.47% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::20480-24575          220      0.43%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::20480-24575          221      0.42%     99.89% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::24576-28671           14      0.03%     99.92% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::28672-32767           10      0.02%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::32768-36863            8      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::36864-40959            5      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::32768-36863            8      0.02%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::36864-40959            5      0.01%     99.96% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::40960-45055            3      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::45056-49151           11      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::45056-49151           12      0.02%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::49152-53247            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::53248-57343            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::57344-61439            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::61440-65535            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total        51641                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples        17522                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11533.700491                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean  9159.086359                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  8173.463802                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767        17339     98.96%     98.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkWaitTime::total        52105                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples        17499                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 11526.115778                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean  9158.153521                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8139.378931                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767        17316     98.95%     98.95% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::32768-65535          177      1.01%     99.97% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::131072-163839            5      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total        17522                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 131382086816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.616564                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.493575                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  131327318816     99.96%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3      37570000      0.03%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5       7000000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7       6185500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9       1198500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total        17499                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 131377054816                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.616890                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.493493                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  131322424316     99.96%     99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3      37436500      0.03%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5       7011000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7       6169000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9       1200000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::10-11       643000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::12-13      1366500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::14-15       794500      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::16-17        10000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 131382086816                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K          6381     82.69%     82.69% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M          1336     17.31%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total         7717                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71435                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walksPending::total 131377054816                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6345     82.32%     82.32% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1363     17.68%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7708                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        71876                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71435                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7717                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        71876                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7708                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7717                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total        79152                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7708                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        79584                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     25445516                       # DTB read hits
-system.cpu.dtb.read_misses                      61525                       # DTB read misses
-system.cpu.dtb.write_hits                    19906341                       # DTB write hits
-system.cpu.dtb.write_misses                      9910                       # DTB write misses
+system.cpu.dtb.read_hits                     25445789                       # DTB read hits
+system.cpu.dtb.read_misses                      61974                       # DTB read misses
+system.cpu.dtb.write_hits                    19906281                       # DTB write hits
+system.cpu.dtb.write_misses                      9902                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     4317                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                       358                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.align_faults                       357                       # Number of TLB faults due to alignment restrictions
 system.cpu.dtb.prefetch_faults                   2185                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                      1330                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 25507041                       # DTB read accesses
-system.cpu.dtb.write_accesses                19916251                       # DTB write accesses
+system.cpu.dtb.read_accesses                 25507763                       # DTB read accesses
+system.cpu.dtb.write_accesses                19916183                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          45351857                       # DTB hits
-system.cpu.dtb.misses                           71435                       # DTB misses
-system.cpu.dtb.accesses                      45423292                       # DTB accesses
+system.cpu.dtb.hits                          45352070                       # DTB hits
+system.cpu.dtb.misses                           71876                       # DTB misses
+system.cpu.dtb.accesses                      45423946                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -474,55 +474,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                     11899                       # Table walker walks requested
-system.cpu.itb.walker.walksShort                11899                       # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1         3941                       # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walks                     11893                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                11893                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1         3935                       # Level at which table walker walks with short descriptors terminate
 system.cpu.itb.walker.walksShortTerminationLevel::Level2         7737                       # Level at which table walker walks with short descriptors terminate
 system.cpu.itb.walker.walksSquashedBefore          221                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples        11678                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean   616.629560                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  2880.318774                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-4095        11122     95.24%     95.24% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::samples        11672                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean   618.017478                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev  2885.502200                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-4095        11116     95.24%     95.24% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::4096-8191          159      1.36%     96.60% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::8192-12287          193      1.65%     98.25% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::12288-16383           62      0.53%     98.78% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::16384-20479           98      0.84%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::20480-24575           32      0.27%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::8192-12287          192      1.64%     98.24% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::12288-16383           62      0.53%     98.77% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::16384-20479           98      0.84%     99.61% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::20480-24575           33      0.28%     99.90% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::24576-28671            2      0.02%     99.91% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::28672-32767            7      0.06%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::45056-49151            1      0.01%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::49152-53247            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::57344-61439            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total        11678                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples         3549                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 12870.386024                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 10191.624224                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev  8688.844550                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-16383         2600     73.26%     73.26% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-32767          892     25.13%     98.39% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-49151           55      1.55%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkWaitTime::total        11672                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples         3547                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 12874.259938                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 10191.545390                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev  8701.526273                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-16383         2599     73.27%     73.27% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-32767          890     25.09%     98.36% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-49151           56      1.58%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::131072-147455            2      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total         3549                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples  24007842416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.962955                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.189019                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0       889977000      3.71%      3.71% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1     23117314916     96.29%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::total         3547                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples  24002810416                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.962951                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.189029                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0       889895500      3.71%      3.71% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1     23112364416     96.29%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::2          493000      0.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::3           57500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total  24007842416                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K          3008     90.38%     90.38% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M           320      9.62%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total         3328                       # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total  24002810416                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          3008     90.44%     90.44% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           318      9.56%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3326                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11899                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total        11899                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst        11893                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total        11893                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3328                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total         3328                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total        15227                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                     66219818                       # ITB inst hits
-system.cpu.itb.inst_misses                      11899                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3326                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3326                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total        15219                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                     66221269                       # ITB inst hits
+system.cpu.itb.inst_misses                      11893                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -531,98 +531,98 @@ system.cpu.itb.flush_tlb                           64                       # Nu
 system.cpu.itb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     3095                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     3094                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2205                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2209                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 66231717                       # ITB inst accesses
-system.cpu.itb.hits                          66219818                       # DTB hits
-system.cpu.itb.misses                           11899                       # DTB misses
-system.cpu.itb.accesses                      66231717                       # DTB accesses
-system.cpu.numCycles                        278809396                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 66233162                       # ITB inst accesses
+system.cpu.itb.hits                          66221269                       # DTB hits
+system.cpu.itb.misses                           11893                       # DTB misses
+system.cpu.itb.accesses                      66233162                       # DTB accesses
+system.cpu.numCycles                        278796094                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          104752228                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      184594753                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    46858822                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33046445                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     161837102                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6149420                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     189977                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 9772                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        357687                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       560902                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          181                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  66220013                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1133469                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5179                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          270782559                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.831431                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.217897                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          104750737                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      184597310                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    46857763                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33046380                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     161828011                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6150220                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     189816                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                10180                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        357136                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       560173                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          186                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  66221459                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1133676                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5180                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          270771349                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.831471                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.217911                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                171565839     63.36%     63.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29222654     10.79%     74.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14067780      5.20%     79.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 55926286     20.65%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                171553381     63.36%     63.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 29224188     10.79%     74.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14067085      5.20%     79.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 55926695     20.65%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            270782559                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.168068                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.662082                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 77849645                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             121907615                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  64584092                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3844418                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                2596789                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3423202                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                486322                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              157325754                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3698413                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                2596789                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 83693975                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11775859                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       76672657                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  62585691                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              33457588                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              146699029                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                957260                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents                452831                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  63761                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                  16550                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30707740                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           150373398                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             678238170                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        164317610                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            270771349                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.168072                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.662123                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 77850364                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             121893157                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  64586539                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3844068                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                2597221                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3423151                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                486287                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              157328219                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3698916                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                2597221                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 83695488                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11783440                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       76673328                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  62587040                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              33434832                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              146701505                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                957116                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents                452960                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  63776                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                  16375                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30685156                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           150380164                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             678249075                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        164321181                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups             10889                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             141712294                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8661101                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2840653                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2644485                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13863116                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26394295                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            21292545                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1689185                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2215742                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  143439670                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2121732                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 143229007                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            270292                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         8404254                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     14686510                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         125844                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     270782559                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.528945                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.865530                       # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps             141709271                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  8670890                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2840534                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2644382                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13862021                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26394587                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21292605                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1688978                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2214312                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  143440731                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2121629                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 143228275                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            270765                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         8407822                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     14697300                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         125774                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     270771349                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.528964                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.865543                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           182544969     67.41%     67.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            45137079     16.67%     84.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            32020155     11.83%     95.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            10269839      3.79%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4              810484      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           182535287     67.41%     67.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            45134238     16.67%     84.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32022031     11.83%     95.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            10269230      3.79%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4              810530      0.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                  33      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -630,9 +630,9 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       270782559                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       270771349                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 7336568     32.74%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 7336420     32.74%     32.74% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                     32      0.00%     32.74% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.74% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.74% # attempts to use FU when none available
@@ -661,13 +661,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.74% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.74% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.74% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5631848     25.13%     57.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               9441706     42.13%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5631672     25.13%     57.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               9443165     42.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2337      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              95930740     66.98%     66.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               113813      0.08%     67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              95929589     66.98%     66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               113798      0.08%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.06% # Type of FU issued
@@ -695,95 +695,95 @@ system.cpu.iq.FU_type_0::SimdFloatMisc           8576      0.01%     67.06% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.06% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             26175663     18.28%     85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            20997878     14.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             26176168     18.28%     85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            20997807     14.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              143229007                       # Type of FU issued
-system.cpu.iq.rate                           0.513717                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    22410154                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.156464                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          579885434                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         153971015                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    140120635                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              143228275                       # Type of FU issued
+system.cpu.iq.rate                           0.513738                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    22411289                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.156473                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          579874368                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         153975557                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    140119306                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads               35585                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes              13122                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses        11367                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              165613479                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              165613882                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                   23345                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           322744                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads           322775                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1495175                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses          502                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18526                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       703988                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1495918                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          503                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18543                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       704297                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        87827                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          6407                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        87804                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          6457                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                2596789                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1243570                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                532137                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           145762333                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                2597221                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1240950                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                535645                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           145763292                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26394295                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             21292545                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1096246                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  17995                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                497968                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18526                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         317449                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       471196                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               788645                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             142286885                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25773498                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            870795                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26394587                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21292605                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1096200                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  17982                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                501480                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18543                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         317940                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       471176                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               789116                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             142285522                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25773547                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            870984                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        200931                       # number of nop insts executed
-system.cpu.iew.exec_refs                     46642508                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 26501737                       # Number of branches executed
-system.cpu.iew.exec_stores                   20869010                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.510337                       # Inst execution rate
-system.cpu.iew.wb_sent                      141900432                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     140132002                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  63223126                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95712973                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.502609                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.660549                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         7603118                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1995888                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            755464                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    267848804                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.512648                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.117834                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        200932                       # number of nop insts executed
+system.cpu.iew.exec_refs                     46642466                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 26501161                       # Number of branches executed
+system.cpu.iew.exec_stores                   20868919                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.510357                       # Inst execution rate
+system.cpu.iew.wb_sent                      141899022                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     140130673                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  63222272                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95712658                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.502628                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.660542                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         7606616                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1995855                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            755952                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    267837215                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.512660                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.117818                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    194453826     72.60%     72.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     43232556     16.14%     88.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15468323      5.78%     94.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4394328      1.64%     96.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6341907      2.37%     98.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1685586      0.63%     99.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       800919      0.30%     99.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       412081      0.15%     99.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1059278      0.40%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    194442706     72.60%     72.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     43232016     16.14%     88.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15468771      5.78%     94.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4394333      1.64%     96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6341721      2.37%     98.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1685699      0.63%     99.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       801066      0.30%     99.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       412117      0.15%     99.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1058786      0.40%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    267848804                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            113236382                       # Number of instructions committed
-system.cpu.commit.committedOps              137312049                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    267837215                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            113234248                       # Number of instructions committed
+system.cpu.commit.committedOps              137309439                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       45487677                       # Number of memory references committed
-system.cpu.commit.loads                      24899120                       # Number of loads committed
-system.cpu.commit.membars                      814929                       # Number of memory barriers committed
-system.cpu.commit.branches                   26016406                       # Number of branches committed
+system.cpu.commit.refs                       45486977                       # Number of memory references committed
+system.cpu.commit.loads                      24898669                       # Number of loads committed
+system.cpu.commit.membars                      814916                       # Number of memory barriers committed
+system.cpu.commit.branches                   26015904                       # Number of branches committed
 system.cpu.commit.fp_insts                      11364                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 120142081                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              4881652                       # Number of function calls committed.
+system.cpu.commit.int_insts                 120139692                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              4881505                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu         91703052     66.78%     66.78% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          112745      0.08%     66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu         91701155     66.78%     66.78% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          112732      0.08%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     66.87% # Class of committed instruction
@@ -811,36 +811,36 @@ system.cpu.commit.op_class_0::SimdFloatMisc         8575      0.01%     66.87% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.87% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.87% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        24899120     18.13%     85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       20588557     14.99%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        24898669     18.13%     85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       20588308     14.99%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         137312049                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               1059278                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    389547304                       # The number of ROB reads
-system.cpu.rob.rob_writes                   292761659                       # The number of ROB writes
-system.cpu.timesIdled                          892855                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         8026837                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   5387025853                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   113081477                       # Number of Instructions Simulated
-system.cpu.committedOps                     137157144                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               2.465562                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.465562                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.405587                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.405587                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                155726558                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88564579                       # number of integer regfile writes
+system.cpu.commit.op_class_0::total         137309439                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               1058786                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    389537878                       # The number of ROB reads
+system.cpu.rob.rob_writes                   292763814                       # The number of ROB writes
+system.cpu.timesIdled                          892824                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         8024745                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   5387029091                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   113079343                       # Number of Instructions Simulated
+system.cpu.committedOps                     137154534                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               2.465491                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.465491                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.405599                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.405599                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                155725297                       # number of integer regfile reads
+system.cpu.int_regfile_writes                88564293                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                      9527                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                     2716                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 502647570                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 53157224                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               348272878                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1521665                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            837515                       # number of replacements
+system.cpu.cc_regfile_reads                 502644821                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 53156150                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               348441241                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1521640                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements            837355                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.925653                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40092431                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            838027                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             47.841455                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            40093226                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            837867                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             47.851540                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         441954500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.925653                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999855                       # Average percentage of cache occupancy
@@ -850,190 +850,190 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          120
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          369                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         179262738                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        179262738                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23296604                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23296604                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     15545032                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       15545032                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       345927                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        345927                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       441660                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       441660                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460331                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460331                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      38841636                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         38841636                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     39187563                       # number of overall hits
-system.cpu.dcache.overall_hits::total        39187563                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       708765                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        708765                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3602792                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3602792                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       177926                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       177926                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        27128                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        27128                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         179262562                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        179262562                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23296906                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23296906                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     15545467                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       15545467                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       345973                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        345973                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       441682                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       441682                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460325                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460325                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      38842373                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         38842373                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     39188346                       # number of overall hits
+system.cpu.dcache.overall_hits::total        39188346                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       708692                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        708692                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3602140                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3602140                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       177879                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       177879                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        27097                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        27097                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            7                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      4311557                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4311557                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4489483                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4489483                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11704891500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11704891500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 232547539185                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 232547539185                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    374670000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    374670000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      4310832                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4310832                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4488711                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4488711                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11726844500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11726844500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 232349107178                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 232349107178                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    373049000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    373049000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       305000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       305000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 244252430685                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 244252430685                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 244252430685                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 244252430685                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24005369                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24005369                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19147824                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19147824                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       523853                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       523853                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468788                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       468788                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     43153193                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     43153193                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43677046                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43677046                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029525                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.029525                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188157                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.188157                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339649                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.339649                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057868                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057868                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 244075951678                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 244075951678                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 244075951678                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 244075951678                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24005598                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24005598                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19147607                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19147607                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       523852                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       523852                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       468779                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       468779                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460332                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460332                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     43153205                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     43153205                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43677057                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43677057                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.029522                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.029522                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.188125                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.188125                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.339560                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.339560                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.057803                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.057803                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000015                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000015                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.099913                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.099913                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.102788                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.102788                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16514.488582                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16514.488582                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64546.479282                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64546.479282                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13811.191389                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13811.191389                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.099896                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.099896                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.102770                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.102770                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.166470                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.166470                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64503.075166                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64503.075166                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13767.169797                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13767.169797                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 56650.632401                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 56650.632401                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54405.469557                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54405.469557                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       871729                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56619.221458                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56619.221458                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54375.510403                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54375.510403                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       870696                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              6864                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              6851                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.000146                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs   127.090352                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       695593                       # number of writebacks
-system.cpu.dcache.writebacks::total            695593                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295624                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       295624                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3303164                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3303164                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18735                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        18735                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3598788                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3598788                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3598788                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3598788                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       413141                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       413141                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299628                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299628                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119644                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       119644                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8393                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8393                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       695416                       # number of writebacks
+system.cpu.dcache.writebacks::total            695416                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       295634                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       295634                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3302552                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3302552                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        18703                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        18703                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3598186                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3598186                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3598186                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3598186                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       413058                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       413058                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299588                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       299588                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       119604                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       119604                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8394                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8394                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            7                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       712769                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       712769                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       832413                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       832413                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       712646                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       712646                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       832250                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       832250                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27585                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58714                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6386936500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6386936500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19975151483                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19975151483                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1701142500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1701142500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126808000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126808000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6391901000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6391901000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19972155480                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19972155480                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1700460500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1700460500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    126799500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    126799500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       298000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       298000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26362087983                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26362087983                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28063230483                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28063230483                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6277199000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6277199000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075698951                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075698951                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11352897951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11352897951                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017210                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017210                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015648                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015648                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228392                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228392                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017904                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017904                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26364056480                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26364056480                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28064516980                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28064516980                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6276327500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6276327500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5075770951                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5075770951                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11352098451                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11352098451                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.017207                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.017207                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015646                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015646                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.228316                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.228316                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017906                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017906                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000015                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000015                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016517                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016517                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019058                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.019058                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15459.459361                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15459.459361                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66666.504743                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66666.504743                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14218.368660                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14218.368660                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15108.781127                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15108.781127                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016514                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016514                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019055                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.019055                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15474.584683                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15474.584683                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66665.405423                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66665.405423                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.421658                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.421658                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15105.968549                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15105.968549                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36985.458098                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36985.458098                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33713.109338                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33713.109338                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201651.161297                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201651.161297                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.137067                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.137067                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193359.300184                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193359.300184                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36994.603885                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36994.603885                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33721.258011                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33721.258011                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.164894                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.164894                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184004.747181                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184004.747181                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193345.683329                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193345.683329                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1886833                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.154154                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            64237730                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1887345                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             34.036029                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1886675                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.154168                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            64239376                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1887187                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             34.039751                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       16318088500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.154154                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.154168                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998348                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -1042,272 +1042,272 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          197
 system.cpu.icache.tags.age_task_id_blocks_1024::2          209                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          68104377                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         68104377                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     64237730                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        64237730                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      64237730                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         64237730                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     64237730                       # number of overall hits
-system.cpu.icache.overall_hits::total        64237730                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1979279                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1979279                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1979279                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1979279                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1979279                       # number of overall misses
-system.cpu.icache.overall_misses::total       1979279                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  28148050491                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  28148050491                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  28148050491                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  28148050491                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  28148050491                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  28148050491                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66217009                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66217009                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66217009                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66217009                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66217009                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66217009                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029891                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.029891                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.029891                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.029891                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.029891                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.029891                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14221.365705                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14221.365705                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14221.365705                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14221.365705                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14221.365705                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14221.365705                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4340                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          68105664                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         68105664                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     64239376                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        64239376                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      64239376                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         64239376                       # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total        64239376                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1979079                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1979079                       # number of ReadReq misses
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+system.cpu.icache.demand_misses::total        1979079                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1979079                       # number of overall misses
+system.cpu.icache.overall_misses::total       1979079                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  28144068491                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  28144068491                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  28144068491                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  28144068491                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  28144068491                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  28144068491                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66218455                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66218455                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66218455                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66218455                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66218455                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66218455                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.029887                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.029887                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.029887                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.029887                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.029887                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.029887                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14220.790828                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14220.790828                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14220.790828                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14220.790828                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14220.790828                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14220.790828                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         5080                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               160                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               162                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    27.125000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    31.358025                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1886833                       # number of writebacks
-system.cpu.icache.writebacks::total           1886833                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91909                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        91909                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        91909                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        91909                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        91909                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        91909                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1887370                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1887370                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1887370                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1887370                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1887370                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1887370                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks      1886675                       # number of writebacks
+system.cpu.icache.writebacks::total           1886675                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        91868                       # number of ReadReq MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1887211                       # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::cpu.inst      1887211                       # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::cpu.inst      1887211                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1887211                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         3004                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25183213993                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  25183213993                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25183213993                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  25183213993                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25183213993                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  25183213993                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  25180995493                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  25180995493                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  25180995493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  25180995493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  25180995493                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  25180995493                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    377667500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    377667500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    377667500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    377667500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028503                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028503                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028503                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.028503                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028503                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.028503                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13343.019118                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13343.019118                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13343.019118                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13343.019118                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.028500                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.028500                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.028500                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.028500                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.028500                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.028500                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13342.967741                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13342.967741                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13342.967741                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13342.967741                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13342.967741                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13342.967741                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96631                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65023.762629                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4997690                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           161869                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            30.874905                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            96487                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65023.312748                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4997676                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           161725                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            30.902309                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 49540.037548                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.058123                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     1.836532                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 10328.574212                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5143.256214                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.755921                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000153                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 49475.678025                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.897856                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     1.835471                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 10343.602046                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5191.299351                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.754939                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000166                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000028                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.157602                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.078480                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_task_id_blocks::1023           12                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65226                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2892                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2890                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6640                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55528                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55530                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995270                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         44234795                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        44234795                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        54117                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        11847                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          65964                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       695593                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       695593                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1846839                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1846839                       # number of WritebackClean hits
+system.cpu.l2cache.tags.tag_accesses         44233161                       # Number of tag accesses
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+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        54581                       # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_hits::total          66422                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       695416                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       695416                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1846676                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1846676                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           33                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           33                       # number of UpgradeReq hits
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-system.cpu.l2cache.demand_avg_miss_latency::total 130600.303222                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139071.428571                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 142562.500000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132379.302525                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130361.519254                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 130600.303222                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130019.424933                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130019.424933                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132353.456964                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132353.456964                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135340.300506                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135340.300506                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 146714.285714                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       132750                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132353.456964                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130500.043672                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 130720.170707                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 146714.285714                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       132750                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132353.456964                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130500.043672                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 130720.170707                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1316,41 +1316,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        88877                       # number of writebacks
-system.cpu.l2cache.writebacks::total            88877                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        88798                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88798                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           26                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           26                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          112                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          112                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          113                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          113                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           26                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          112                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          138                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          139                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           26                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          112                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          138                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          139                       # number of overall MSHR hits
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           21                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            8                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total           29                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2723                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2723                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2721                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2721                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135531                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       135531                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19817                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19817                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13338                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13338                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       135393                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       135393                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        19818                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        19818                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        13331                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        13331                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           21                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            8                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        19817                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       148869                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       168715                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        19818                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       148724                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168571                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           21                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            8                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        19817                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       148869                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168715                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        19818                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       148724                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168571                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         3004                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31129                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        34133                       # number of ReadReq MSHR uncacheable
@@ -1359,146 +1359,146 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27585
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         3004                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58714                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        61718                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker      1060500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3771000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    192695000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    192695000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      2871000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       982000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      3853000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    192556500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    192556500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       212500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       212500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16252241500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16252241500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2425990000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2425990000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1667259500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1667259500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker      1060500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2425990000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17919501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20349262000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2710500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker      1060500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2425990000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17919501000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20349262000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16249790000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16249790000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2425294500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2425294500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1672223500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1672223500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      2871000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       982000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2425294500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17922013500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20351161000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      2871000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       982000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2425294500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17922013500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20351161000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    340117000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888077000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6228194000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4756881000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4756881000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5887205500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6227322500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4756953000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4756953000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    340117000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10644958000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10985075000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10644158500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10984275500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000385                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000439                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.988026                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.988026                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000436                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.988017                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.988017                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.428571                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.428571                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.456330                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.456330                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010500                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024652                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024652                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.455929                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.455929                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010501                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010501                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.024645                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024645                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000385                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177637                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060442                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000388                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010501                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.177498                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060387                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000385                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000675                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010500                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177637                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060442                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130034.482759                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70765.699596                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70765.699596                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010501                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.177498                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060387                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132862.068966                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70766.813671                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70766.813671                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119915.307199                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119915.307199                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122419.639703                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125000.712251                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125000.712251                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120370.936864                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120613.235338                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 132562.500000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122419.639703                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120370.936864                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120613.235338                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120019.424933                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120019.424933                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122378.368150                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122378.368150                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125438.714275                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125438.714275                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122378.368150                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120505.187461                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120727.533206                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       122750                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122378.368150                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120505.187461                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120727.533206                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189150.856115                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182468.403012                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172444.480696                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172444.480696                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.859713                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.870536                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.090810                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.090810                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181301.870082                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177988.188211                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.253228                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.234129                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5484076                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2758688                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        47112                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          381                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          381                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5483387                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2758318                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        47114                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          382                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          382                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         127589                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2556141                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         128004                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2556278                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27585                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27585                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       820637                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1846839                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       142823                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2757                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       820384                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1846676                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       142776                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2755                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            7                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2763                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       297002                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       297002                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1887370                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       541297                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2761                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       296961                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       296961                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1887211                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       541178                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        36194                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5627539                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2629603                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31270                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       128179                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8416591                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    239034368                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98344937                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        47420                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       216552                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          337643277                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      197136                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3052848                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.025905                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.158851                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5627062                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2629120                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        31258                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       129064                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8416504                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    239014016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     98323369                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        47396                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       218408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          337603189                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      196948                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3052801                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025889                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.158805                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2973765     97.41%     97.41% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              79083      2.59%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2973766     97.41%     97.41% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              79035      2.59%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3052848                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5400072997                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3052801                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5399625997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       264877                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2834880345                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2834640846                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1303595064                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1303359054                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19421986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      19415986                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74092896                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      74513896                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iobus.trans_dist::ReadReq                30198                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30198                       # Transaction distribution
@@ -1506,6 +1506,7 @@ system.iobus.trans_dist::WriteReq               59014                       # Tr
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
@@ -1521,16 +1522,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  178424                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
@@ -1546,26 +1545,25 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480349                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             43091000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             43090500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                99500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                29000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               325000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                29000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                91000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               647500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                14500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy                91000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer8.occupancy               648000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
@@ -1582,35 +1580,29 @@ system.iobus.reqLayer18.occupancy                9000                       # La
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy                3000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy                9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer20.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6192000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6193500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              167000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            33084000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            33054500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           186380025                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              126000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186395016                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               31500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36770000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36409                       # number of replacements
-system.iocache.tags.tagsinuse                1.005392                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.005380                       # Cycle average of tags in use
 system.iocache.tags.total_refs                     30                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36425                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000824                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         256608771000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.005392                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.062837                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.062837                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         256605907000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.005380                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.062836                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.062836                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1626,14 +1618,14 @@ system.iocache.demand_misses::realview.ide          249                       #
 system.iocache.demand_misses::total               249                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          249                       # number of overall misses
 system.iocache.overall_misses::total              249                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     31311876                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     31311876                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4715518140                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4715518140                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     31311876                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     31311876                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     31311876                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     31311876                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     31316876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31316876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4717082149                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4717082149                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     31316876                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     31316876                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     31316876                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     31316876                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          249                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            249                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1650,19 +1642,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.506024                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125750.506024                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130280.926647                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130280.926647                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 125750.506024                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125750.506024                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 125750.506024                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125750.506024                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           725                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 125770.586345                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125770.586345                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130324.137284                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130324.137284                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125770.586345                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125770.586345                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125770.586345                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125770.586345                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           902                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   77                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   96                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.415584                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.395833                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1676,14 +1668,14 @@ system.iocache.demand_mshr_misses::realview.ide          249
 system.iocache.demand_mshr_misses::total          249                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          249                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          249                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     18861876                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     18861876                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2905768140                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2905768140                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     18861876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     18861876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     18861876                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     18861876                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     18866876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     18866876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2907332149                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2907332149                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     18866876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     18866876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     18866876                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     18866876                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999199                       # mshr miss rate for WriteLineReq accesses
@@ -1692,68 +1684,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.506024                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.506024                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.926647                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80280.926647                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.506024                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75750.506024                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.506024                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75750.506024                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75770.586345                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75770.586345                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80324.137284                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80324.137284                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 75770.586345                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75770.586345                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 75770.586345                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75770.586345                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               34133                       # Transaction distribution
-system.membus.trans_dist::ReadResp              67565                       # Transaction distribution
+system.membus.trans_dist::ReadResp              67559                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27585                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27585                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       125037                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             7766                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4596                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       124958                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             7701                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4594                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4599                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            133659                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           133659                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         33433                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4597                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            133521                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           133521                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         33427                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36194                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36194                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           16                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2076                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       455099                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562669                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       454663                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       562233                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108826                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108826                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 671495                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 671059                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          128                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16416028                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16579433                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16401756                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     16565161                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2315200                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2315200                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                18894633                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                18880361                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              513                       # Total snoops (count)
-system.membus.snoop_fanout::samples            402650                       # Request fanout histogram
+system.membus.snoop_fanout::samples            402363                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  402650    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  402363    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              402650                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            83677500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              402363                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            83709500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               10000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1748500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1749000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           874312374                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           873720378                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          988164899                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          987389399                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64093300                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64116283                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
index b52f4e770..087862053 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -1612,10 +1612,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -1642,7 +1641,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1806,12 +1805,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -1904,16 +1900,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1929,7 +1924,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -2092,13 +2087,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -2108,9 +2103,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -2152,7 +2146,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -2233,14 +2227,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -2257,7 +2250,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -2272,7 +2265,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -2395,17 +2388,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -2457,7 +2452,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -2472,7 +2467,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
index d121ecdb1..a6b78f915 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 18:10:16
-gem5 executing on e104799-lin, pid 6288
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 13:54:35
+gem5 executing on e104799-lin, pid 12868
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
 
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index e15135031..8cd4c8c91 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.824799                       # Nu
 sim_ticks                                2824799320500                       # Number of ticks simulated
 final_tick                               2824799320500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 238793                       # Simulator instruction rate (inst/s)
-host_op_rate                                   289676                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5483857198                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 587432                       # Number of bytes of host memory used
-host_seconds                                   515.11                       # Real time elapsed on the host
+host_inst_rate                                 252554                       # Simulator instruction rate (inst/s)
+host_op_rate                                   306369                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5799873287                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 587696                       # Number of bytes of host memory used
+host_seconds                                   487.05                       # Real time elapsed on the host
 sim_insts                                   123005008                       # Number of instructions simulated
 sim_ops                                     149215388                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -2055,6 +2055,7 @@ system.iobus.trans_dist::WriteReq               59010                       # Tr
 system.iobus.trans_dist::WriteResp              59010                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54148                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
@@ -2070,16 +2071,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105436                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72946                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72946                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  178382                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67865                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
@@ -2095,10 +2094,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159093                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321224                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321224                       # Cumulative packet size per connected master and slave (bytes)
@@ -2107,10 +2103,12 @@ system.iobus.reqLayer0.occupancy             27670500                       # La
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               101500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                20000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               205000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                16500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                20000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                16500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               12500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               40500                       # Layer occupancy (ticks)
@@ -2121,14 +2119,10 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer23.occupancy             3858000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy               90500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            22212000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            22212000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy            78391042                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              114500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy            78391042                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            48071000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            15512000                       # Layer occupancy (ticks)
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
index 6ed4cac0e..996e7dc32 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -1261,10 +1261,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -1291,7 +1290,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1455,12 +1454,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -1553,16 +1549,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1578,7 +1573,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1741,13 +1736,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1757,9 +1752,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1801,7 +1795,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1882,14 +1876,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1906,7 +1899,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1921,7 +1914,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -2044,17 +2037,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -2106,7 +2101,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -2121,7 +2116,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
index c832ed926..6ccdf8861 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
@@ -43,11 +43,17 @@ warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
 warn: CP14 unimplemented crn[3], opc1[0], crm[0], opc2[0]
 warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
 warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
+warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
 warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2]
 warn: CP14 unimplemented crn[12], opc1[0], crm[12], opc2[0]
 warn: CP14 unimplemented crn[12], opc1[0], crm[12], opc2[1]
 warn: CP14 unimplemented crn[12], opc1[0], crm[0], opc2[3]
 warn: 	instruction 'mcr bpiall' unimplemented
+warn: CP14 unimplemented crn[2], opc1[2], crm[4], opc2[1]
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
index 7f6fb346f..1e617f520 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 18:14:24
-gem5 executing on e104799-lin, pid 6415
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 12:17:01
+gem5 executing on e104799-lin, pid 3291
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
 
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 1264a2585..ceb2dbc54 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
@@ -1,138 +1,138 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.823500                       # Number of seconds simulated
-sim_ticks                                2823500156000                       # Number of ticks simulated
-final_tick                               2823500156000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                2823500372500                       # Number of ticks simulated
+final_tick                               2823500372500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 106175                       # Simulator instruction rate (inst/s)
-host_op_rate                                   128867                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2564438881                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 588796                       # Number of bytes of host memory used
-host_seconds                                  1101.02                       # Real time elapsed on the host
-sim_insts                                   116900784                       # Number of instructions simulated
-sim_ops                                     141885276                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 115105                       # Simulator instruction rate (inst/s)
+host_op_rate                                   139706                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2779881687                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 588972                       # Number of bytes of host memory used
+host_seconds                                  1015.69                       # Real time elapsed on the host
+sim_insts                                   116911425                       # Number of instructions simulated
+sim_ops                                     141898519                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker         3904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         3648                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           658624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5296736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         4992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           714240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4509448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           660992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5280544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         5120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           712768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4516872                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11188968                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       658624                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       714240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1372864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8441728                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11180968                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       660992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       712768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1373760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8429056                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8459252                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker           61                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8446580                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker           57                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             10291                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             83280                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           78                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             11160                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             70462                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             10328                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             83027                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           80                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             11137                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             70578                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                175348                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          131902                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                175223                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          131704                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               136283                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1383                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               136085                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1292                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              233265                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1875947                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              252963                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1597113                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              234104                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1870212                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1813                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              252441                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1599742                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3962801                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         233265                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         252963                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             486228                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2989810                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3959967                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         234104                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         252441                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             486545                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2985321                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6204                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2996016                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2989810                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1383                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2991528                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2985321                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1292                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             233265                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1882150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             252963                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1597116                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             234104                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1876416                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1813                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             252441                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1599745                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6958817                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        175349                       # Number of read requests accepted
-system.physmem.writeReqs                       136283                       # Number of write requests accepted
-system.physmem.readBursts                      175349                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     136283                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11214592                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7744                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8471552                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11189032                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8459252                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      121                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6951495                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        175224                       # Number of read requests accepted
+system.physmem.writeReqs                       136085                       # Number of write requests accepted
+system.physmem.readBursts                      175224                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     136085                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11205440                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8896                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8458688                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11181032                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8446580                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      139                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3887                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          49584                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11393                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10987                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11434                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11274                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11014                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10539                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11403                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11330                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               11251                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11289                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10499                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10072                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10665                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11522                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10554                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10002                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8625                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8280                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8885                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8791                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7852                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7876                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8450                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8527                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8486                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8687                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7873                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7718                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8233                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8873                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7886                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7326                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          49641                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11401                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10979                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11428                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11300                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11019                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10545                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               11444                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11405                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11225                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11073                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10490                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10075                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10628                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11391                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10678                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10004                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8636                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8268                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8882                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8813                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7855                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7878                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8477                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8545                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8487                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8481                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7867                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7716                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8202                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8761                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7974                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7325                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2823499978000                       # Total gap between requests
+system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2823500194500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     542                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  174793                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  174668                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 131902                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    107531                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     59234                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      6725                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1718                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 131704                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    107487                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     59144                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      6664                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1770                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
@@ -161,175 +161,178 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        97                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        95                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                        92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                        92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                        92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        92                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                        89                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       85                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6274                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6970                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7272                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     8094                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8577                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8030                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7392                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      320                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       96                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65648                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      299.873263                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     177.206399                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.323909                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24801     37.78%     37.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        16133     24.58%     62.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6704     10.21%     72.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3735      5.69%     78.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2850      4.34%     82.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1672      2.55%     85.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1116      1.70%     86.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1095      1.67%     88.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7542     11.49%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65648                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6665                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        26.286122                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      483.294559                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6663     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7012                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     8145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7696                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8524                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8763                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8680                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    10155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      246                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      259                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      238                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      134                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       73                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      103                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       17                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        65624                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      299.646471                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     177.275715                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     322.864593                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24692     37.63%     37.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        16213     24.71%     62.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6759     10.30%     72.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3713      5.66%     78.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2878      4.39%     82.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1688      2.57%     85.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1064      1.62%     86.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1117      1.70%     88.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7500     11.43%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65624                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6648                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.331227                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      483.912144                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6646     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-8191            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::36864-38911            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6665                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6665                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        19.860165                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.266089                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.031195                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                16      0.24%      0.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 4      0.06%      0.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                5      0.08%      0.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              10      0.15%      0.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5719     85.81%     86.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             154      2.31%     88.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              55      0.83%     89.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             202      3.03%     92.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              36      0.54%     93.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             143      2.15%     95.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              45      0.68%     95.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               9      0.14%     95.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              15      0.23%     96.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              23      0.35%     96.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               4      0.06%     96.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               6      0.09%     96.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             162      2.43%     99.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.08%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.06%     99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              18      0.27%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               1      0.02%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.58% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            6648                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6648                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.880716                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.279022                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.177011                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                14      0.21%      0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 3      0.05%      0.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                5      0.08%      0.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              11      0.17%      0.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5692     85.62%     86.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             171      2.57%     88.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              60      0.90%     89.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             185      2.78%     92.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              34      0.51%     92.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             150      2.26%     95.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              50      0.75%     95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              10      0.15%     96.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              23      0.35%     96.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              19      0.29%     96.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               7      0.11%     96.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               8      0.12%     96.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             143      2.15%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.08%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               7      0.11%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              20      0.30%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.02%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.02%     99.58% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::96-99               1      0.02%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.03%     99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.03%     99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            17      0.26%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6665                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2742857501                       # Total ticks spent queuing
-system.physmem.totMemAccLat                6028382501                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    876140000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15653.08                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.20%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.03%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.05%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6648                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2744374251                       # Total ticks spent queuing
+system.physmem.totMemAccLat                6027218001                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    875425000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       15674.53                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34403.08                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  34424.53                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.97                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.96                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.00                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.99                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.46                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        13.09                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     144250                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97697                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.32                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.79                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9060366.00                       # Average gap between requests
-system.physmem.pageHitRate                      78.65                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  255936240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  139647750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 697117200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                436013280                       # Energy for write commands per rank (pJ)
+system.physmem.avgWrQLen                        12.80                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144084                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97542                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.29                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.78                       # Row buffer hit rate for writes
+system.physmem.avgGap                      9069767.32                       # Average gap between requests
+system.physmem.pageHitRate                      78.63                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  256420080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  139911750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 698263800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                436453920                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           184417078560                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80003561535                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1623919600500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1889868955065                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.336286                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2701419954000                       # Time in different power states
+system.physmem_0.actBackEnergy            80050894335                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1623878080500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1889877102945                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.339172                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2701352401000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     94282760000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     27794238500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     27861791500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  240362640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  131150250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 669653400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                421731360                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                  239697360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  130787250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 667383600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                419988240                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           184417078560                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            79168489875                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1624652119500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1889700585585                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.276655                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2702647601500                       # Time in different power states
+system.physmem_1.actBackEnergy            79252079805                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1624578795000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1889705809815                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.278505                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2702525049250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     94282760000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     26569784000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     26691828250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           704                       # Number of bytes read from this memory
@@ -349,15 +352,15 @@ system.cf0.dma_read_txs                             1                       # Nu
 system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               26581187                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         13736110                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           501433                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            16012084                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               12431439                       # Number of BTB hits
+system.cpu0.branchPred.lookups               26559789                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         13713833                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           501635                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            15976864                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               12419776                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            77.637858                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                6636300                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             27516                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            77.736006                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                6636189                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             27705                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -388,88 +391,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    56625                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort               56625                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17270                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        13837                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore        25518                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples        31107                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean   865.432218                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev  5323.916597                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-16383        30633     98.48%     98.48% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-32767          331      1.06%     99.54% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-49151           76      0.24%     99.78% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-65535           30      0.10%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-81919           18      0.06%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                    56617                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort               56617                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1        17206                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2        13819                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore        25592                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        31025                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean   854.665592                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev  5277.318433                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-16383        30569     98.53%     98.53% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-32767          316      1.02%     99.55% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-49151           76      0.24%     99.79% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-65535           28      0.09%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-81919           17      0.05%     99.94% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::81920-98303            4      0.01%     99.95% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::98304-114687            5      0.02%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::114688-131071            5      0.02%     99.98% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::131072-147455            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        31107                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        12481                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 13577.197340                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 10994.614021                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  9335.319316                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         9132     73.17%     73.17% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767         3098     24.82%     97.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151          222      1.78%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535            8      0.06%     99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-81919            4      0.03%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-147455           14      0.11%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkWaitTime::total        31025                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        12676                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 13504.851688                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 10947.656823                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  9228.518750                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         9308     73.43%     73.43% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767         3112     24.55%     97.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151          228      1.80%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535           10      0.08%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-81919            2      0.02%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-147455           13      0.10%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::147456-163839            3      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        12481                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples  91900460244                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.603534                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.511861                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1  91817471744     99.91%     99.91% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3     56263000      0.06%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5     12793000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7      5164500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9      2519500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11      1396500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13      1020000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15      2514500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       435000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19       355500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-21        97000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::22-23        44500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-25       171000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::26-27        35500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-29        18000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::30-31       161000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total  91900460244                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3454     69.05%     69.05% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1548     30.95%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         5002                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        56625                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total        12676                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  91900678744                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.634073                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.504786                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1  91817596744     99.91%     99.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3     56432500      0.06%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5     12685500      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7      5058000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9      2486500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11      1667000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13       978500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15      2452500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       399500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19       440000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-21        77000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::22-23        47000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-25       115000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::26-27        26500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-29        31000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::30-31       185500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  91900678744                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3474     69.04%     69.04% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1558     30.96%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5032                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        56617                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        56625                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5002                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        56617                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5032                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5002                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        61627                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5032                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        61649                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    13967095                       # DTB read hits
-system.cpu0.dtb.read_misses                     47255                       # DTB read misses
-system.cpu0.dtb.write_hits                   10501947                       # DTB write hits
-system.cpu0.dtb.write_misses                     9370                       # DTB write misses
+system.cpu0.dtb.read_hits                    13956888                       # DTB read hits
+system.cpu0.dtb.read_misses                     47161                       # DTB read misses
+system.cpu0.dtb.write_hits                   10502014                       # DTB write hits
+system.cpu0.dtb.write_misses                     9456                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva                     479                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3287                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      776                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1257                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    3284                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      763                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  1265                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      595                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                14014350                       # DTB read accesses
-system.cpu0.dtb.write_accesses               10511317                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      602                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                14004049                       # DTB read accesses
+system.cpu0.dtb.write_accesses               10511470                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         24469042                       # DTB hits
-system.cpu0.dtb.misses                          56625                       # DTB misses
-system.cpu0.dtb.accesses                     24525667                       # DTB accesses
+system.cpu0.dtb.hits                         24458902                       # DTB hits
+system.cpu0.dtb.misses                          56617                       # DTB misses
+system.cpu0.dtb.accesses                     24515519                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -499,803 +502,800 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     7362                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                7362                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2261                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         4952                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore          149                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples         7213                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1612.505199                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  6472.144246                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-8191         6729     93.29%     93.29% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-16383          210      2.91%     96.20% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-24575          172      2.38%     98.59% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-32767           48      0.67%     99.25% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-40959           20      0.28%     99.53% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::40960-49151           11      0.15%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::49152-57343            8      0.11%     99.79% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::57344-65535            3      0.04%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-73727            4      0.06%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::81920-90111            3      0.04%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::90112-98303            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::106496-114687            2      0.03%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         7213                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2374                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 13966.512216                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11737.528521                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  8158.100835                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         1734     73.04%     73.04% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          597     25.15%     98.19% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           40      1.68%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-65535            2      0.08%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                     7529                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                7529                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1         2281                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         5094                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore          154                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples         7375                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean         1792                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev  7463.239883                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-16383         7070     95.86%     95.86% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-32767          234      3.17%     99.04% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-49151           37      0.50%     99.54% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::49152-65535           16      0.22%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-81919            7      0.09%     99.85% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::81920-98303            5      0.07%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-114687            1      0.01%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::114688-131071            2      0.03%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-147455            3      0.04%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         7375                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2396                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 13984.557596                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11758.733193                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  8144.466175                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         1749     73.00%     73.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          606     25.29%     98.29% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           39      1.63%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2374                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples  23180714008                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.929856                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.256422                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     1630643500      7.03%      7.03% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1    21546495508     92.95%     99.98% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2        2812000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3         517500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         174500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5          71000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total  23180714008                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1663     74.74%     74.74% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          562     25.26%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2225                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total         2396                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples  23180931508                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.845594                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.362375                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0     3585102000     15.47%     15.47% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1    19591754508     84.52%     99.98% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2        3051000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3         602000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4         249500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5          48000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6         124500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total  23180931508                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1680     74.93%     74.93% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          562     25.07%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2242                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7362                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7362                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         7529                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         7529                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2225                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2225                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         9587                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    20128372                       # ITB inst hits
-system.cpu0.itb.inst_misses                      7362                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2242                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2242                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         9771                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    20127989                       # ITB inst hits
+system.cpu0.itb.inst_misses                      7529                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     478                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva                     479                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2149                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2165                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1237                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1248                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                20135734                       # ITB inst accesses
-system.cpu0.itb.hits                         20128372                       # DTB hits
-system.cpu0.itb.misses                           7362                       # DTB misses
-system.cpu0.itb.accesses                     20135734                       # DTB accesses
-system.cpu0.numCycles                       111789846                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                20135518                       # ITB inst accesses
+system.cpu0.itb.hits                         20127989                       # DTB hits
+system.cpu0.itb.misses                           7529                       # DTB misses
+system.cpu0.itb.accesses                     20135518                       # DTB accesses
+system.cpu0.numCycles                       111773750                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          39393717                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     103942274                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   26581187                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          19067739                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     67197572                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                3104883                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                    120313                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles                4808                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles              429                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles       187538                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       119721                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          669                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 20127335                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               349524                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   3480                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         108577171                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.150570                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.270138                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          39404734                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     103901347                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   26559789                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          19055965                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     67172503                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                3105480                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                    123475                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles                4254                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles              446                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles       188702                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       117718                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          813                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 20126932                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               348923                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   3603                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         108565347                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.150440                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.270106                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                80014629     73.69%     73.69% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                 3810733      3.51%     77.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 2393612      2.20%     79.41% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 7999548      7.37%     86.78% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1536045      1.41%     88.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 1088578      1.00%     89.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 6047569      5.57%     94.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 1035127      0.95%     95.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4651330      4.28%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                80009058     73.70%     73.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                 3809201      3.51%     77.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 2394359      2.21%     79.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 7998409      7.37%     86.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1537996      1.42%     88.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 1087909      1.00%     89.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 6040532      5.56%     94.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 1033019      0.95%     95.71% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4654864      4.29%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           108577171                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.237778                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.929801                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                26873328                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             63362554                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 15407826                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles              1524257                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1408897                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1872466                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred               145547                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              86353471                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               470061                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1408897                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                27727925                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                6705409                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      45853663                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 16073761                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             10807193                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              82639232                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 2272                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1128991                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                256935                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents               8662593                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands           84875469                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            381763695                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        92641306                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             5587                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             72346979                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                12528482                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1562352                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts       1465023                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  8851459                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            14739399                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           11667463                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          2112364                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         2804310                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  79594677                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1116242                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 76600031                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            88073                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       10385869                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     23123923                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        102217                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    108577171                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.705489                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.406693                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           108565347                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.237621                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.929568                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26883025                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             63349855                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 15403629                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles              1519503                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1408994                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1872503                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred               145749                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              86293156                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               470873                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1408994                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                27735944                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                6700023                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      45856628                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 16066730                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             10796686                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              82579979                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 2391                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               1108634                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                252112                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents               8668459                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands           84779937                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            381537510                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        92587970                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             5626                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             72263854                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                12516075                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1563295                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts       1465928                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  8829402                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            14730052                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           11675597                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          2115179                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         2832097                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  79532292                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1117477                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 76533618                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            87406                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       10386047                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     23162950                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        102669                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    108565347                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.704954                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.405780                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           77873399     71.72%     71.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10449451      9.62%     81.35% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            7708887      7.10%     88.45% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            6446636      5.94%     94.38% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2344597      2.16%     96.54% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1520287      1.40%     97.94% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6            1484500      1.37%     99.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             489237      0.45%     99.76% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             260177      0.24%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           77871483     71.73%     71.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10453105      9.63%     81.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            7708495      7.10%     88.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            6443405      5.94%     94.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2343404      2.16%     96.55% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1520676      1.40%     97.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6            1477584      1.36%     99.31% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             486752      0.45%     99.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8             260443      0.24%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      108577171                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      108565347                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                 112335      9.77%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     1      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      9.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                528670     45.98%     55.75% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               508787     44.25%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                 112393      9.83%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     1      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      9.83% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                527099     46.11%     55.94% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               503655     44.06%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass              225      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             51038212     66.63%     66.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               57114      0.07%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          4060      0.01%     66.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            14356873     18.74%     85.45% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           11143544     14.55%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             50981056     66.61%     66.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               56862      0.07%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              1      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          4067      0.01%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            14347373     18.75%     85.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           11144026     14.56%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              76600031                       # Type of FU issued
-system.cpu0.iq.rate                          0.685215                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1149793                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.015010                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         263002604                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         91143035                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     74349830                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              12495                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              6612                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         5504                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              77742883                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   6716                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          356237                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              76533618                       # Type of FU issued
+system.cpu0.iq.rate                          0.684719                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1143148                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.014937                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         262850677                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         91081899                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     74283043                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              12460                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              6644                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         5511                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              77669867                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   6674                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          356195                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1997626                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2287                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        54048                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      1072719                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1995192                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2360                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        53884                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      1081117                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads       202075                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       121659                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads       202683                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       121039                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1408897                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                5279939                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              1209588                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           80840958                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           118727                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             14739399                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            11667463                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            570481                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 45640                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              1151814                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         54048                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        221570                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       202811                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              424381                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             76042804                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             14136234                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           500738                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1408994                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                5274240                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              1210190                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           80780073                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           118682                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             14730052                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            11675597                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            571348                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 46022                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              1152002                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         53884                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        221496                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       202557                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              424053                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             75976302                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             14126659                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           500836                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       130039                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    25177582                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                14081958                       # Number of branches executed
-system.cpu0.iew.exec_stores                  11041348                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.680230                       # Inst execution rate
-system.cpu0.iew.wb_sent                      75486871                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     74355334                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 38977390                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 68370260                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.665135                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.570093                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       10422774                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls        1014025                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.iew.exec_nop                       130304                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    25168197                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                14063788                       # Number of branches executed
+system.cpu0.iew.exec_stores                  11041538                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.679733                       # Inst execution rate
+system.cpu0.iew.wb_sent                      75420123                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     74288554                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 38930485                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 68286780                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.664633                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.570103                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       10422530                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls        1014808                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu0.commit.branchMispredicts           357851                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    106178823                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.663049                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.560671                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::samples    106167071                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.662547                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.559914                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     78820889     74.23%     74.23% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     12387005     11.67%     85.90% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      6099262      5.74%     91.64% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2661518      2.51%     94.15% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1365099      1.29%     95.44% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       835592      0.79%     96.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      1729906      1.63%     97.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       422537      0.40%     98.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1857015      1.75%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     78816600     74.24%     74.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     12394656     11.67%     85.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      6095585      5.74%     91.65% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2659364      2.50%     94.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1364551      1.29%     95.44% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       834490      0.79%     96.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      1723865      1.62%     97.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       420734      0.40%     98.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1857226      1.75%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    106178823                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            58051307                       # Number of instructions committed
-system.cpu0.commit.committedOps              70401754                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    106167071                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            57989505                       # Number of instructions committed
+system.cpu0.commit.committedOps              70340708                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      23336517                       # Number of memory references committed
-system.cpu0.commit.loads                     12741773                       # Number of loads committed
-system.cpu0.commit.membars                     415885                       # Number of memory barriers committed
-system.cpu0.commit.branches                  13388774                       # Number of branches committed
+system.cpu0.commit.refs                      23329340                       # Number of memory references committed
+system.cpu0.commit.loads                     12734860                       # Number of loads committed
+system.cpu0.commit.membars                     416180                       # Number of memory barriers committed
+system.cpu0.commit.branches                  13372532                       # Number of branches committed
 system.cpu0.commit.fp_insts                      5482                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 61799925                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls             2627242                       # Number of function calls committed.
+system.cpu0.commit.int_insts                 61754724                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls             2627334                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu        47005628     66.77%     66.77% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult          55549      0.08%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc         4060      0.01%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.85% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       12741773     18.10%     84.95% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      10594744     15.05%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu        46951986     66.75%     66.75% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult          55316      0.08%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv               0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc         4066      0.01%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.83% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       12734860     18.10%     84.94% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      10594480     15.06%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total         70401754                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events              1857015                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                   172799952                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  164051440                       # The number of ROB writes
-system.cpu0.timesIdled                         381792                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                        3212675                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2095454483                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   57974599                       # Number of Instructions Simulated
-system.cpu0.committedOps                     70325046                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.928256                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.928256                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.518603                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.518603                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                83013564                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               47348236                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    16364                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   13356                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                268593239                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes                27791636                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads              149451268                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                777954                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements           855224                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.968896                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           42357273                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           855736                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            49.498061                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total         70340708                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events              1857226                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                   172725039                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  163928651                       # The number of ROB writes
+system.cpu0.timesIdled                         382167                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                        3208403                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2095470503                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   57912515                       # Number of Instructions Simulated
+system.cpu0.committedOps                     70263718                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.930045                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.930045                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.518123                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.518123                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                82944906                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               47313800                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    16399                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   13366                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                268363191                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes                27733780                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads              150032753                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                778510                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements           855432                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.968774                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           42360074                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           855944                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            49.489305                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        186702500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   250.010146                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   261.958750                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.488301                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.511638                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   250.285909                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   261.682865                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.488840                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.511099                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999939                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        189272310                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       189272310                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     12310382                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     12874546                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       25184928                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      7941393                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      7958196                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      15899589                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       183968                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       180294                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       364262                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       229947                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       216143                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       446090                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236320                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       222981                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       459301                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20251775                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     20832742                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41084517                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20435743                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     21013036                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       41448779                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       435921                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       404886                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       840807                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1879167                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1817887                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      3697054                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       117369                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        66831                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       184200                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13653                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        14181                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        27834                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data           33                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data           38                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           71                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      2315088                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      2222773                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4537861                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      2432457                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      2289604                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      4722061                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7255753500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   7425105000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  14680858500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137676029415                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 114829611127                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 252505640542                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    218997000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    196633500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    415630500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       943000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data      1495500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      2438500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 144931782915                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 122254716127                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 267186499042                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 144931782915                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 122254716127                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 267186499042                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     12746303                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     13279432                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     26025735                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9820560                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9776083                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19596643                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       301337                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       247125                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       548462                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       243600                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       230324                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       473924                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236353                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       223019                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       459372                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     22566863                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     23055515                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     45622378                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     22868200                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     23302640                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     46170840                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034200                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030490                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.032307                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.191350                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.185952                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.188658                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.389494                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.270434                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.335848                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056047                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061570                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058731                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000140                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000170                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000155                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102588                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096410                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.099466                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106369                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.098255                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.102274                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16644.652357                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18338.754612                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17460.438008                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 73264.392901                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63166.528572                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 68299.148604                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16040.210943                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13865.982653                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14932.474671                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28575.757576                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 39355.263158                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 34345.070423                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 62603.142047                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 55000.990262                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 58879.392525                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 59582.464527                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 53395.572390                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 56582.602182                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1675298                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       341272                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            52888                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           3016                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.676335                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   113.153846                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses        189283631                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       189283631                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     12299336                       # number of ReadReq hits
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034282                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.030400                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.032300                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.191355                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.185900                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.188633                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.389850                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.270836                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.336214                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056190                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.061769                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.058899                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000148                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000157                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000152                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.102665                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.096310                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.099452                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.106452                       # miss rate for overall accesses
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+system.cpu0.dcache.overall_miss_rate::total     0.102265                       # miss rate for overall accesses
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18297.876263                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17387.155215                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 73266.696044                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 63239.423111                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 68336.247884                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15931.142753                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13837.835936                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14865.025619                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25771.428571                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 33585.714286                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 29678.571429                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 62571.883886                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 55066.401253                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 58896.805445                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 59550.183162                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 53455.159070                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 56595.889681                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      1672747                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       343360                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            52819                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           3007                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    31.669418                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   114.186897                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       704987                       # number of writebacks
-system.cpu0.dcache.writebacks::total           704987                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       227007                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       186874                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       413881                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1727391                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1670069                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3397460                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         8885                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9612                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18497                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1954398                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1856943                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3811341                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1954398                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1856943                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3811341                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       208914                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       218012                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       426926                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       151776                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       147818                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       299594                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74095                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48646                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       122741                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4768                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4569                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9337                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           33                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           38                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           71                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       360690                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       365830                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       726520                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       434785                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       414476                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       849261                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14744                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16385                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.writebacks::writebacks       705176                       # number of writebacks
+system.cpu0.dcache.writebacks::total           705176                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       227433                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       186404                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       413837                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1727395                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1669692                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3397087                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         8981                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9780                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        18761                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1954828                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1856096                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3810924                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1954828                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1856096                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3810924                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       209183                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       217648                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       426831                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       151680                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       148044                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       299724                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        74197                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        48897                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       123094                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         4714                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4434                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9148                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           35                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data           35                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           70                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       360863                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       365692                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       726555                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       435060                       # number of overall MSHR misses
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+system.cpu0.dcache.overall_mshr_misses::total       849649                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14753                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16376                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31129                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15212                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12376                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15226                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        12362                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27588                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        29956                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28761                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        29979                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        28738                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58717                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3330300500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3396411500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6726712000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11231056881                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9824685455                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  21055742336                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1111837000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    752623000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1864460000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     96489000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     61648000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    158137000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       910000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1457500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2367500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14561357381                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13221096955                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  27782454336                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15673194381                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  13973719955                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  29646914336                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2960669500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3341308500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6301978000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2589197924                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2495038452                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5084236376                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5549867424                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5836346952                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11386214376                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016390                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016417                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016404                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015455                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015120                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015288                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.245887                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.196848                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.223791                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.019573                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019837                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019701                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000140                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000170                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000155                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015983                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015867                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.015925                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019013                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017787                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018394                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15941.011612                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15579.011706                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15756.154462                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73997.581179                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66464.743502                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70280.921300                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15005.560429                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15471.426222                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15190.197245                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20236.786913                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13492.667980                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16936.596337                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27575.757576                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 38355.263158                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33345.070423                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40370.837509                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36140.002064                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38240.453581                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36048.148811                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33714.183584                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34909.073107                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200805.039338                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203924.839792                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202447.171448                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170207.594268                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201602.977699                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184291.589677                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185267.306182                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202925.731094                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193916.827767                       # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3331281500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   3387836500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6719118000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11202793385                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9855220460                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  21058013845                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1114883500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    753687500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1868571000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     93837000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     59852000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    153689000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       867000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      1140500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      2007500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  14534074885                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  13243056960                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  27777131845                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  15648958385                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  13996744460                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  29645702845                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2963039000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3337977000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6301016000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2592772424                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2491429952                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5084202376                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5555811424                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5829406952                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11385218376                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.016425                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016375                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016399                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015446                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015140                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015294                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.246170                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.197749                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.224348                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.019341                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019268                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.019306                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000148                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000157                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000152                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.015999                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.015852                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.015924                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019034                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.017781                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.018401                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15925.201857                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15565.667959                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15741.869733                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73858.078751                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66569.536489                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70258.016859                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15025.991617                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15413.777941                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15180.033145                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 19906.024608                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13498.421290                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16800.284215                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24771.428571                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 32585.714286                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 28678.571429                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40275.880002                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36213.690647                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38231.285787                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35969.655645                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33760.530212                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34891.705687                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200843.150546                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203833.475818                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202416.267789                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170285.854722                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201539.391037                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184290.357257                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185323.440542                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202846.647366                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193899.865048                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1936787                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.471074                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           38830098                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1937299                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            20.043420                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1935670                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.471469                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           38837356                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1936182                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            20.058732                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      11154875500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   205.082456                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   306.388618                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.400552                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.598415                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998967                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   205.076991                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   306.394478                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.400541                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.598427                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998968                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          229                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          143                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          139                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          230                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          140                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         42853283                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        42853283                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     19119269                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     19710829                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       38830098                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     19119269                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     19710829                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        38830098                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     19119269                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     19710829                       # number of overall hits
-system.cpu0.icache.overall_hits::total       38830098                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1007396                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1078417                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      2085813                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1007396                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1078417                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       2085813                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1007396                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1078417                       # number of overall misses
-system.cpu0.icache.overall_misses::total      2085813                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14294314981                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15434234486                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  29728549467                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  14294314981                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  15434234486                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  29728549467                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  14294314981                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  15434234486                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  29728549467                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     20126665                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     20789246                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     40915911                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     20126665                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     20789246                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     40915911                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     20126665                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     20789246                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     40915911                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050053                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.051874                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.050978                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050053                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.051874                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.050978                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050053                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.051874                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.050978                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14189.370398                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14311.935444                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14252.739563                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14189.370398                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14311.935444                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14252.739563                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14189.370398                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14311.935444                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14252.739563                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        19244                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         42857903                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        42857903                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     19118560                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     19718796                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       38837356                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     19118560                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     19718796                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        38837356                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     19118560                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     19718796                       # number of overall hits
+system.cpu0.icache.overall_hits::total       38837356                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1007700                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      1076592                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      2084292                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1007700                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      1076592                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       2084292                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1007700                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      1076592                       # number of overall misses
+system.cpu0.icache.overall_misses::total      2084292                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  14294399976                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  15401560487                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  29695960463                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  14294399976                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  15401560487                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  29695960463                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  14294399976                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  15401560487                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  29695960463                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     20126260                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     20795388                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     40921648                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     20126260                       # number of demand (read+write) accesses
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+system.cpu0.icache.demand_accesses::total     40921648                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     20126260                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     20795388                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     40921648                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.050069                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.051771                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.050934                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.050069                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.051771                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.050934                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.050069                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.051771                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.050934                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14185.174135                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14305.847050                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14247.504890                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14185.174135                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14305.847050                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14247.504890                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14185.174135                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14305.847050                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14247.504890                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        21497                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              808                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              838                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.816832                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    25.652745                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1936787                       # number of writebacks
-system.cpu0.icache.writebacks::total          1936787                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71558                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76882                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       148440                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        71558                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        76882                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       148440                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        71558                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        76882                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       148440                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       935838                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1001535                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1937373                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       935838                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      1001535                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1937373                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       935838                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      1001535                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1937373                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1935670                       # number of writebacks
+system.cpu0.icache.writebacks::total          1935670                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        71379                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        76657                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       148036                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        71379                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        76657                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       148036                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        71379                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        76657                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       148036                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       936321                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       999935                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1936256                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       936321                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       999935                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1936256                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       936321                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       999935                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1936256                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst          668                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total          668                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst          668                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total          668                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12537948486                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13509677989                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  26047626475                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12537948486                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13509677989                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  26047626475                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12537948486                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13509677989                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  26047626475                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12542067979                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  13487008993                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  26029076972                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12542067979                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  13487008993                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  26029076972                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12542067979                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  13487008993                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  26029076972                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst     86506500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total     86506500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst     86506500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total     86506500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046497                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048176                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047350                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046497                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048176                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.047350                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046497                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048176                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.047350                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13397.562918                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13488.972416                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13444.817531                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13397.562918                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13488.972416                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13444.817531                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13397.562918                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13488.972416                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13444.817531                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.046522                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.048084                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.047316                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.046522                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.048084                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.047316                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.046522                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.048084                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.047316                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13395.051461                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13487.885706                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13442.993577                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13395.051461                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13487.885706                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13442.993577                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13395.051461                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13487.885706                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13442.993577                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups               27828831                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         14541667                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           548498                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            17325081                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               13118302                       # Number of BTB hits
+system.cpu1.branchPred.lookups               27854639                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         14561380                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           548025                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            17333975                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               13131194                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            75.718561                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                6848129                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             29493                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            75.754084                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                6850254                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             29025                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1325,86 +1325,85 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    57586                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort               57586                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19035                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13643                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore        24908                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        32678                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean   702.995899                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev  4885.704946                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-16383        32257     98.71%     98.71% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-32767          309      0.95%     99.66% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-49151           56      0.17%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::49152-65535           25      0.08%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-81919           12      0.04%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::81920-98303            4      0.01%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::98304-114687            5      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::114688-131071            5      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-147455            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    58019                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort               58019                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1        19126                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2        13648                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore        25245                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        32774                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean   718.053945                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev  4822.223013                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-16383        32332     98.65%     98.65% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-32767          325      0.99%     99.64% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-49151           64      0.20%     99.84% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::49152-65535           24      0.07%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-81919           11      0.03%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::81920-98303            5      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-114687            5      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::114688-131071            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::147456-163839            4      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        32678                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        13208                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 14797.811932                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 12463.368567                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  8508.122633                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        12903     97.69%     97.69% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535          300      2.27%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303            3      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        13208                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  91471142744                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.733221                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.463957                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1  91384673244     99.91%     99.91% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3     60550000      0.07%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5     13658500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7      4816000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9      2368000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11      1256000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13       753000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15      2182000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       292000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19       158000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-21        50500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::22-23        28500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-25       277000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::26-27        11000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-29         7500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::30-31        61500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  91471142744                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3746     68.55%     68.55% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         1719     31.45%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         5465                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        57586                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total        32774                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        13276                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 14765.931003                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 12384.741759                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  8664.538551                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        12938     97.45%     97.45% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535          331      2.49%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303            4      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839            2      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        13276                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  91470687244                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.764325                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.447298                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1  91383080744     99.90%     99.90% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3     61332500      0.07%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5     13710000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7      4721500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9      2367000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11      1504000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13       818000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15      2160000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       464000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19       210500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21        81000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23        75000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-25        60500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::26-27        14500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-29        18500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::30-31        69500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  91470687244                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3730     68.50%     68.50% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1715     31.50%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5445                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        58019                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        57586                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5465                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        58019                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5445                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5465                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        63051                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5445                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        63464                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    14412138                       # DTB read hits
-system.cpu1.dtb.read_misses                     49815                       # DTB read misses
-system.cpu1.dtb.write_hits                   10474078                       # DTB write hits
-system.cpu1.dtb.write_misses                     7771                       # DTB write misses
+system.cpu1.dtb.read_hits                    14422648                       # DTB read hits
+system.cpu1.dtb.read_misses                     50091                       # DTB read misses
+system.cpu1.dtb.write_hits                   10474825                       # DTB write hits
+system.cpu1.dtb.write_misses                     7928                       # DTB write misses
 system.cpu1.dtb.flush_tlb                         185                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva                     438                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    3611                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      776                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1282                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    3615                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      797                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  1273                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      647                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                14461953                       # DTB read accesses
-system.cpu1.dtb.write_accesses               10481849                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      633                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                14472739                       # DTB read accesses
+system.cpu1.dtb.write_accesses               10482753                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         24886216                       # DTB hits
-system.cpu1.dtb.misses                          57586                       # DTB misses
-system.cpu1.dtb.accesses                     24943802                       # DTB accesses
+system.cpu1.dtb.hits                         24897473                       # DTB hits
+system.cpu1.dtb.misses                          58019                       # DTB misses
+system.cpu1.dtb.accesses                     24955492                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1434,388 +1433,388 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     7940                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                7940                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2768                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         4984                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore          188                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples         7752                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1436.661507                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  6120.056353                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-8191         7301     94.18%     94.18% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-16383          193      2.49%     96.67% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-24575          153      1.97%     98.65% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-32767           37      0.48%     99.12% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-40959           27      0.35%     99.47% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::40960-49151           16      0.21%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::49152-57343           11      0.14%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::57344-65535            4      0.05%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-73727            5      0.06%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::73728-81919            1      0.01%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::81920-90111            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::90112-98303            1      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-106495            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         7752                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         2623                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 14933.282501                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 12692.719494                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  8120.359954                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-8191          585     22.30%     22.30% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-16383         1248     47.58%     69.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-24575          629     23.98%     93.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-32767          104      3.96%     97.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-40959           23      0.88%     98.70% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-49151           26      0.99%     99.70% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-57343            4      0.15%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::57344-65535            3      0.11%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::73728-81919            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         2623                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples  31327211100                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.898331                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.302824                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     3189472000     10.18%     10.18% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1    28134324100     89.81%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2        2583000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3         637000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         160000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5          35000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total  31327211100                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1850     75.98%     75.98% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          585     24.02%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2435                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                     7961                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                7961                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1         2709                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         5049                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore          203                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples         7758                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1605.503996                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev  7035.957070                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-8191         7284     93.89%     93.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-16383          191      2.46%     96.35% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::16384-24575          155      2.00%     98.35% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-32767           42      0.54%     98.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-40959           32      0.41%     99.30% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::40960-49151           13      0.17%     99.47% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::49152-57343           14      0.18%     99.65% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::57344-65535            8      0.10%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-73727            6      0.08%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::73728-81919            4      0.05%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::81920-90111            5      0.06%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::90112-98303            1      0.01%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-106495            2      0.03%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::106496-114687            1      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         7758                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         2633                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 14904.291682                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 12612.038197                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  8468.527051                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-16383         1843     70.00%     70.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-32767          736     27.95%     97.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-49151           45      1.71%     99.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-65535            6      0.23%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-81919            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::81920-98303            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         2633                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples  35622983396                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.863018                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.344487                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     4885377500     13.71%     13.71% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1    30733731396     86.28%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2        2597000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3         833500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4         365000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5          79000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  35622983396                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1847     76.01%     76.01% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          583     23.99%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2430                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7940                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7940                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         7961                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         7961                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2435                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2435                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        10375                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    20791300                       # ITB inst hits
-system.cpu1.itb.inst_misses                      7940                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2430                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2430                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        10391                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    20797463                       # ITB inst hits
+system.cpu1.itb.inst_misses                      7961                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                         185                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     439                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva                     438                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2403                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2393                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                     1472                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                20799240                       # ITB inst accesses
-system.cpu1.itb.hits                         20791300                       # DTB hits
-system.cpu1.itb.misses                           7940                       # DTB misses
-system.cpu1.itb.accesses                     20799240                       # DTB accesses
-system.cpu1.numCycles                       114309908                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                20805424                       # ITB inst accesses
+system.cpu1.itb.hits                         20797463                       # DTB hits
+system.cpu1.itb.misses                           7961                       # DTB misses
+system.cpu1.itb.accesses                     20805424                       # DTB accesses
+system.cpu1.numCycles                       114307464                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          41263279                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     107226594                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                   27828831                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          19966431                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     67413560                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3261213                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                    132884                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles                6791                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles              371                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles       251452                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       126014                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          455                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 20789251                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               378310                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3605                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         110825375                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.163723                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.274017                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          41243432                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     107322713                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                   27854639                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          19981448                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     67441487                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3261241                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                    132708                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles                6649                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles              428                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles       247804                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       128164                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          421                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 20795394                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               377977                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3632                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         110831676                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.164555                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.274676                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                81246984     73.31%     73.31% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                 3970774      3.58%     76.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 2468449      2.23%     79.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 8233318      7.43%     86.55% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1681631      1.52%     88.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 1117562      1.01%     89.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 6321498      5.70%     94.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 1162226      1.05%     95.83% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4622933      4.17%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                81234051     73.29%     73.29% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                 3972250      3.58%     76.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 2466525      2.23%     79.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 8240157      7.43%     86.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1682835      1.52%     88.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 1118017      1.01%     89.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 6328104      5.71%     94.78% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 1164123      1.05%     95.83% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4625614      4.17%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           110825375                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.243451                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.938034                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                28317279                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             63485741                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 15848519                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles              1697419                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1476110                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1966949                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               156570                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              88997857                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               507653                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1476110                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                29247785                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                7012026                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      46712417                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 16603449                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              9773269                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              85151296                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 3883                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               1655595                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                301575                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents               7069337                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands           88292342                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            391615779                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        94636441                       # Number of integer rename lookups
+system.cpu1.fetch.rateDist::total           110831676                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.243682                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.938895                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                28301754                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             63497891                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 15850723                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles              1704776                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1476204                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1967399                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               156467                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              89087170                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               506464                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1476204                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                29234593                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                7013474                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      46686266                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 16610559                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              9810257                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              85239039                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 4158                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               1678441                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                295156                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents               7089576                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands           88402024                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            391987455                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        94729150                       # Number of integer rename lookups
 system.cpu1.rename.fp_rename_lookups             6205                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             74317970                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13974372                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts           1570590                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts       1473246                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  9761371                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            15285949                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           11554817                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          2153118                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         2760852                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  81958519                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1096065                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 78473689                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            91016                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       11494354                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     25135429                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        116024                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    110825375                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.708084                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.398689                       # Number of insts issued each cycle
+system.cpu1.rename.CommittedMaps             74414781                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                13987243                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts           1570718                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts       1473274                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  9797771                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            15295971                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           11557906                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          2126909                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         2757513                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  82041945                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1095184                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 78547336                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            91731                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       11502328                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     25183489                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        115903                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    110831676                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.708708                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.399992                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           79269169     71.53%     71.53% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           10544902      9.51%     81.04% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            8143493      7.35%     88.39% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            6684211      6.03%     94.42% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            2457263      2.22%     96.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1495236      1.35%     97.99% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1542850      1.39%     99.38% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             479172      0.43%     99.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8             209079      0.19%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           79311031     71.56%     71.56% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           10467239      9.44%     81.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            8143760      7.35%     88.35% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            6716432      6.06%     94.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            2458249      2.22%     96.63% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1495385      1.35%     97.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1551990      1.40%     99.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             479300      0.43%     99.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8             208290      0.19%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      110825375                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      110831676                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                 101177      9.01%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                523345     46.61%     55.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               498385     44.38%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                 101407      9.05%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     6      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      9.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                524965     46.83%     55.88% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               494582     44.12%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass             2112      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             52572793     66.99%     67.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               59372      0.08%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  1      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          4520      0.01%     67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            14812673     18.88%     85.95% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           11022213     14.05%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             52635037     67.01%     67.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               59537      0.08%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  1      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          4516      0.01%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            14823039     18.87%     85.97% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           11023089     14.03%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              78473689                       # Type of FU issued
-system.cpu1.iq.rate                          0.686499                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    1122913                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.014309                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         268972635                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         94593002                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     76135780                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              14047                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              7316                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         6000                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              79586882                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   7608                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          356462                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              78547336                       # Type of FU issued
+system.cpu1.iq.rate                          0.687158                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    1120960                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.014271                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         269124936                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         94683536                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     76208716                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              14103                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              7328                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         6023                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              79658545                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   7639                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          355195                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2228793                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2378                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        52565                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1113544                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2229396                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         2459                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        52609                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1115131                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads       209799                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        80325                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads       209977                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        80421                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1476110                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                5644573                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              1066657                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           83187752                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           132087                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             15285949                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            11554817                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            564046                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 44633                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              1008979                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         52565                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        252953                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       220957                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              473910                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             77870409                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             14572543                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           545823                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1476204                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                5662909                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              1045252                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           83270672                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           132429                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             15295971                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            11557906                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            563484                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 44736                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents               987233                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         52609                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        252467                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       221077                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              473544                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             77944038                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             14582258                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           545399                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       133168                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    25490059                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                14772585                       # Number of branches executed
-system.cpu1.iew.exec_stores                  10917516                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.681222                       # Inst execution rate
-system.cpu1.iew.wb_sent                      77325591                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     76141780                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 39859971                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 69277952                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.666100                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.575363                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       11469730                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         980041                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           393964                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    108246213                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.661810                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.544617                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       133543                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    25500080                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                14792660                       # Number of branches executed
+system.cpu1.iew.exec_stores                  10917822                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.681881                       # Inst execution rate
+system.cpu1.iew.wb_sent                      77398935                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     76214739                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 39907228                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 69371500                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.666752                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.575268                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       11478700                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         979281                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           393571                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    108251137                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.662466                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.546689                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     80231551     74.12%     74.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     12503324     11.55%     85.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      6520168      6.02%     91.69% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      2652912      2.45%     94.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1399925      1.29%     95.44% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       915869      0.85%     96.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1908410      1.76%     98.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       405906      0.37%     98.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1708148      1.58%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     80272291     74.15%     74.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     12448333     11.50%     85.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      6524108      6.03%     91.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      2657086      2.45%     94.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1374916      1.27%     95.40% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       919571      0.85%     96.25% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1942028      1.79%     98.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       407210      0.38%     98.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1705594      1.58%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    108246213                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            59004382                       # Number of instructions committed
-system.cpu1.commit.committedOps              71638427                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    108251137                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            59076825                       # Number of instructions committed
+system.cpu1.commit.committedOps              71712716                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      23498429                       # Number of memory references committed
-system.cpu1.commit.loads                     13057156                       # Number of loads committed
-system.cpu1.commit.membars                     398159                       # Number of memory barriers committed
-system.cpu1.commit.branches                  13983983                       # Number of branches committed
+system.cpu1.commit.refs                      23509350                       # Number of memory references committed
+system.cpu1.commit.loads                     13066575                       # Number of loads committed
+system.cpu1.commit.membars                     397868                       # Number of memory barriers committed
+system.cpu1.commit.branches                  14004120                       # Number of branches committed
 system.cpu1.commit.fp_insts                      5946                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 62620951                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls             2707521                       # Number of function calls committed.
+system.cpu1.commit.int_insts                 62678118                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls             2708748                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu        48077932     67.11%     67.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult          57547      0.08%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc         4519      0.01%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       13057156     18.23%     85.43% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      10441273     14.57%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu        48141082     67.13%     67.13% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult          57769      0.08%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv               0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     67.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc         4515      0.01%     67.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     67.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       13066575     18.22%     85.44% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      10442775     14.56%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total         71638427                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events              1708148                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                   176890222                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  168799668                       # The number of ROB writes
-system.cpu1.timesIdled                         412724                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        3484533                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3325413921                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   58926185                       # Number of Instructions Simulated
-system.cpu1.committedOps                     71560230                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.939883                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.939883                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.515495                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.515495                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                84497448                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               48483083                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    17003                       # number of floating regfile reads
+system.cpu1.commit.op_class_0::total         71712716                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events              1705594                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                   176973973                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  168967567                       # The number of ROB writes
+system.cpu1.timesIdled                         411783                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        3475788                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3325418218                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   58998910                       # Number of Instructions Simulated
+system.cpu1.committedOps                     71634801                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.937450                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.937450                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.516142                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.516142                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                84572142                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               48524924                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    17041                       # number of floating regfile reads
 system.cpu1.fp_regfile_writes                   13376                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                275324862                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes                29228214                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads              152523655                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                741987                       # number of misc regfile writes
+system.cpu1.cc_regfile_reads                275577121                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes                29280900                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads              152549282                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                741444                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30172                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30172                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
@@ -1831,16 +1830,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72894                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72894                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  178372                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
@@ -1856,27 +1853,26 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321016                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321016                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480141                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             49500500                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             49495000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               100500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                28500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               333500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                28500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                88000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               613500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                12000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy                86000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               19500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy               612500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer10.occupancy               19000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
@@ -1896,31 +1892,25 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6444000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6442000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              168000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            38187000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            38204000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           186272549                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              128000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186303033                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               37000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36718000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36413                       # number of replacements
-system.iocache.tags.tagsinuse                1.069629                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.069649                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36429                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         236545551000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.069629                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.066852                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.066852                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         236542797000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.069649                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.066853                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.066853                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1934,14 +1924,14 @@ system.iocache.demand_misses::realview.ide          223                       #
 system.iocache.demand_misses::total               223                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          223                       # number of overall misses
 system.iocache.overall_misses::total              223                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28112876                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28112876                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4718729157                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4718729157                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28112876                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28112876                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28112876                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28112876                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     28108377                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28108377                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4720216172                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4720216172                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28108377                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28108377                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28108377                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28108377                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          223                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            223                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1958,19 +1948,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 126066.708520                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126066.708520                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130265.270456                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130265.270456                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 126066.708520                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 126066.708520                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 126066.708520                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 126066.708520                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           790                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 126046.533632                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126046.533632                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130306.321003                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130306.321003                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 126046.533632                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 126046.533632                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 126046.533632                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 126046.533632                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           748                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   84                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   92                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.404762                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     8.130435                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1984,14 +1974,14 @@ system.iocache.demand_mshr_misses::realview.ide          223
 system.iocache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          223                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16962876                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16962876                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2907529157                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2907529157                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16962876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16962876                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16962876                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16962876                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     16958377                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     16958377                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2909016172                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2909016172                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     16958377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     16958377                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     16958377                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     16958377                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2000,274 +1990,274 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76066.708520                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76066.708520                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80265.270456                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80265.270456                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 76066.708520                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 76066.708520                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 76066.708520                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 76066.708520                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76046.533632                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76046.533632                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80306.321003                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80306.321003                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 76046.533632                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76046.533632                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76046.533632                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76046.533632                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104414                       # number of replacements
-system.l2c.tags.tagsinuse                65108.520896                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5146190                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   169727                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    30.320397                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   48973.831139                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    38.132682                       # Average occupied blocks per requestor
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 system.l2c.UpgradeReq_accesses::cpu1.data         1355                       # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.965314                       # miss rate for UpgradeReq accesses
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 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       132500                       # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1499.617737                       # average UpgradeReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140236.842105                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker       132500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 133797.749896                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 133719.091137                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 135403.846154                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 132776.981549                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 134039.269572                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 133795.423112                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 133084.942683                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 133749.317921                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 134668.750000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 132746.476887                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 134141.751859                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 133811.771239                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2276,251 +2266,251 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95712                       # number of writebacks
-system.l2c.writebacks::total                    95712                       # number of writebacks
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-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           65                       # number of ReadSharedReq MSHR hits
+system.l2c.writebacks::writebacks               95514                       # number of writebacks
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 system.l2c.ReadSharedReq_mshr_hits::cpu1.data           80                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          145                       # number of ReadSharedReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu1.data             80                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                157                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
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 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1308                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2737                       # number of UpgradeReq MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst          668                       # number of ReadReq MSHR uncacheable
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+system.l2c.WriteReq_mshr_uncacheable_latency::total   4764749500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst     76007997                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5188496500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5489105000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  10753609497                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001773                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000135                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.002120                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.001612                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.967502                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.965314                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.966455                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.212121                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.368421                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.295775                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.502508                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.440850                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.472077                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010299                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011145                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010736                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.028562                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.025910                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027275                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001773                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000135                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010299                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.191186                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.002120                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011145                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.171429                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.061220                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001773                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000135                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010299                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.191186                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.002120                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011145                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.171429                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.061220                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 126131.147541                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5194162000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5482447500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  10752617497                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001660                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000131                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.002169                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.001583                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.970688                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.964576                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.967753                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.171429                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.285714                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.228571                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.501275                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.441059                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.471524                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.010333                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011139                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010750                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.028461                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.025878                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.027209                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001660                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000131                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010333                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.190515                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.002169                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011139                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.171711                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.061189                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001660                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000131                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010333                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.190515                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.002169                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011139                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.171711                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.061189                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 130236.842105                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total       125700                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70801.959412                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70787.077982                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70794.847643                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71142.857143                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70857.142857                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70952.380952                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123570.232343                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123537.033309                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 123554.931055                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123843.000934                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122785.887007                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123275.736837                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125187.249057                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128821.830084                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126862.455726                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126131.147541                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 124668.750000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 126952.898551                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70823.384831                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70782.707728                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70803.917613                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        71250                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70600                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70843.750000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123598.871257                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123721.764597                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 123655.666341                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123142.753773                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122754.960851                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122935.226515                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125259.726796                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128143.111808                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126588.915916                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130236.842105                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123843.000934                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123728.914440                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122785.887007                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124055.667281                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 123809.733679                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126131.147541                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123142.753773                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123761.945536                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124668.750000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122754.960851                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124154.047798                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 123826.407292                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130236.842105                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       122500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123843.000934                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123728.914440                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122785.887007                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124055.667281                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 123809.733679                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123142.753773                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123761.945536                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124668.750000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122754.960851                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124154.047798                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 123826.407292                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188303.818502                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191423.314007                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188345.771519                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158568.564291                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190096.477052                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172712.012469                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188341.659324                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191332.162921                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188315.501368                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158646.886904                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190033.327940                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172710.943164                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173203.915743                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190852.369528                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 181082.924931                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173260.015344                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190773.453267                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 181066.220376                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               31797                       # Transaction distribution
-system.membus.trans_dist::ReadResp              68202                       # Transaction distribution
+system.membus.trans_dist::ReadResp              68179                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27588                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27588                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       131902                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8715                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4626                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq             21                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4647                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            138223                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           138223                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         36406                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       131704                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8781                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4622                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq             16                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4638                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            138120                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           138120                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         36383                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           22                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2082                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       473420                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       581002                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       473019                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       580601                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108889                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108889                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 689891                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 689490                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          704                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4164                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17331100                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     17495093                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17310428                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     17474421                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                19812213                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              495                       # Total snoops (count)
-system.membus.snoop_fanout::samples            415719                       # Request fanout histogram
+system.membus.pkt_size::total                19791541                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              494                       # Total snoops (count)
+system.membus.snoop_fanout::samples            415457                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  415719    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  415457    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              415719                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            95454500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              415457                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            95427000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               17812                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1728500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1716000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           923427409                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           922382161                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1018310336                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1017668838                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64109029                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64149362                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2563,60 +2553,60 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      5625045                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2831932                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        48184                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5623218                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2831016                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        48178                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops            419                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops          419                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq             147963                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2644441                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq             148339                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2643775                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27588                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27588                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       836893                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1896241                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          151625                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2832                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            71                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2903                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           296799                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296799                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1937373                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       559190                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       836888                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1895159                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          151681                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2822                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            70                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2892                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           296933                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          296933                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1936256                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       559265                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5772018                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2682598                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        40560                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       162458                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8657634                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    245374528                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    100080181                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        62636                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       284772                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              345802117                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          207035                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          3148875                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.027211                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.162698                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5768715                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2683173                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        41220                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       162488                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8655596                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    245234624                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    100105653                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        63776                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       284888                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              345688941                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          206956                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          3148204                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.027216                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.162713                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                3063191     97.28%     97.28% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  85684      2.72%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                3062522     97.28%     97.28% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  85682      2.72%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            3148875                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         5537375493                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            3148204                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         5535720994                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           269876                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           269377                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2909027051                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2907347058                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1330509019                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1330807539                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          24943913                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          25313424                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          91705109                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          91701122                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    3037                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
index ee909a18b..f4750f909 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -1615,10 +1615,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -1645,7 +1644,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1809,12 +1808,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -1907,16 +1903,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1932,7 +1927,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -2095,13 +2090,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -2111,9 +2106,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -2155,7 +2149,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -2236,14 +2230,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -2260,7 +2253,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -2275,7 +2268,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -2398,17 +2391,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -2460,7 +2455,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -2475,7 +2470,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
index 7b7bd2fbd..207c42573 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 18:19:04
-gem5 executing on e104799-lin, pid 6711
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 12:36:35
+gem5 executing on e104799-lin, pid 5221
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 47381662864000 because m5_exit instruction encountered
+Exiting @ tick 47381683294000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
index 331b8e7fb..b300e6060 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
@@ -1,169 +1,169 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.381663                       # Number of seconds simulated
-sim_ticks                                47381662864000                       # Number of ticks simulated
-final_tick                               47381662864000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.381683                       # Number of seconds simulated
+sim_ticks                                47381683294000                       # Number of ticks simulated
+final_tick                               47381683294000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 132815                       # Simulator instruction rate (inst/s)
-host_op_rate                                   156205                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7502885455                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 760860                       # Number of bytes of host memory used
-host_seconds                                  6315.13                       # Real time elapsed on the host
-sim_insts                                   838745469                       # Number of instructions simulated
-sim_ops                                     986455629                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 169119                       # Simulator instruction rate (inst/s)
+host_op_rate                                   198983                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9178439782                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 757568                       # Number of bytes of host memory used
+host_seconds                                  5162.28                       # Real time elapsed on the host
+sim_insts                                   873041938                       # Number of instructions simulated
+sim_ops                                    1027205539                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker        42368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        41792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          6976384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         35367624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      9096640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        59520                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        61888                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3056960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         12429456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher      7583744                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        432640                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             75149016                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      6976384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3056960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total        10033344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     59523200                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        85568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        75648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          7273408                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         37833736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     11654720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       106816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        96448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3691584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         15254352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     10772160                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        424448                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             87268888                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      7273408                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3691584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10964992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     68656704                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          59543784                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker          662                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker          653                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst            109006                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            552632                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       142135                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          930                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          967                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             47765                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            194223                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       118496                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6760                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1174229                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          930050                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          68677288                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1337                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1182                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst            113647                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            591165                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       182105                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1669                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1507                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             57681                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            238362                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       168315                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6632                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1363602                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1072761                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               932624                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           894                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           882                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              147238                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              746441                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       191987                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1256                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          1306                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               64518                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              262326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       160057                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9131                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1586036                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         147238                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          64518                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             211756                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1256250                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1075335                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1806                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1597                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              153507                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              798489                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       245975                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2254                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2036                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               77912                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              321946                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       227349                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8958                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1841828                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         153507                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          77912                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             231418                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1449014                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1256684                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1256250                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          894                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          882                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             147238                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             746876                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       191987                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1256                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         1306                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              64518                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             262326                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       160057                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9131                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2842720                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1174229                       # Number of read requests accepted
-system.physmem.writeReqs                       932624                       # Number of write requests accepted
-system.physmem.readBursts                     1174229                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     932624                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 75113152                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     37504                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  59543040                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  75149016                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               59543784                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      586                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1449448                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1449014                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1806                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1597                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             153507                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             798923                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       245975                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2254                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2036                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              77912                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             321946                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       227349                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8958                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3291276                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1363603                       # Number of read requests accepted
+system.physmem.writeReqs                      1075335                       # Number of write requests accepted
+system.physmem.readBursts                     1363603                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1075335                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 87237120                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     33472                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  68675712                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  87268952                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               68677288                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      523                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         448232                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               71067                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               73380                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               69314                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               74537                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               66547                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               79030                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               66275                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               68082                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               68948                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              127738                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              63222                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              73993                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              67075                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              69321                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              63089                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              72025                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               57427                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61393                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               59144                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61303                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               56823                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63517                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               54876                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               56576                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               56101                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               62480                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              54750                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              61148                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              54574                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              57375                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              53605                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              59268                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         497625                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               80650                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               88729                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               73569                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               80330                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               79168                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               89219                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               76757                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               80146                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               80110                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              145487                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              85462                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              91495                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              74671                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              80575                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              75276                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              81436                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               65415                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               72062                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               62920                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               67234                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               65543                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               71204                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               63108                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65618                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               64627                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               73983                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              67070                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              71654                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              63584                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              67795                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              63419                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              67822                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47381660751500                       # Total gap between requests
+system.physmem.numWrRetry                          20                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47381681282500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1174199                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1363573                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 930050                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    756841                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    295232                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     26539                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     19834                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                     17154                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     15837                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     14079                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     12670                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     10425                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1820                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      989                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      647                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      492                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      324                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      175                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      157                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      142                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      119                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       92                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       62                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1072761                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    866656                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    332331                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     37458                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     26767                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                     22591                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     20794                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     18575                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     16649                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     13953                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2927                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1423                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      882                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      650                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      423                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      256                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      225                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      182                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      162                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       96                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -188,164 +188,164 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::16                    18671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    35561                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    45390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    50223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    52287                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    55018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    55938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    58169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    58483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    59754                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    64501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    60072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    59690                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    64110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    58190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    54561                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    52990                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      888                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      738                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::38                      526                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      421                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::41                      365                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::44                      397                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::46                      327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      308                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      322                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::53                      214                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::57                       93                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::58                       83                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::60                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       70                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       709891                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      189.684557                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     114.673344                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     252.164844                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         431942     60.85%     60.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       132623     18.68%     79.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        44376      6.25%     85.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        24102      3.40%     89.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        15088      2.13%     91.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         9957      1.40%     92.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7669      1.08%     93.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7642      1.08%     94.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        36492      5.14%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         709891                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         51534                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.773974                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      380.344580                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          51531     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::59                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      121                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       57                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       845070                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      184.496716                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     112.937858                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     245.074486                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         518646     61.37%     61.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       158346     18.74%     80.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        53030      6.28%     86.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        28124      3.33%     89.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18210      2.15%     91.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11789      1.40%     93.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         8638      1.02%     94.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8488      1.00%     95.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        39799      4.71%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         845070                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60101                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.679190                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      352.199560                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          60098    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::81920-86015            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           51534                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         51534                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.053324                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.386136                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.764507                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           48029     93.20%     93.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            1359      2.64%     95.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             210      0.41%     96.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             316      0.61%     96.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              77      0.15%     97.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             304      0.59%     97.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             196      0.38%     97.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              89      0.17%     98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             103      0.20%     98.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              90      0.17%     98.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              42      0.08%     98.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              57      0.11%     98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             406      0.79%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              44      0.09%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              34      0.07%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             103      0.20%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              21      0.04%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.01%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             3      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            20      0.04%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             6      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           51534                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    26583019130                       # Total ticks spent queuing
-system.physmem.totMemAccLat               48588825380                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5868215000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       22650.00                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           60101                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60101                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.854245                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.273539                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.223401                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           56328     93.72%     93.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            1584      2.64%     96.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             235      0.39%     96.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             339      0.56%     97.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              81      0.13%     97.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             304      0.51%     97.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             166      0.28%     98.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             108      0.18%     98.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              84      0.14%     98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             101      0.17%     98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              39      0.06%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              59      0.10%     98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             433      0.72%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              41      0.07%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              33      0.05%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              91      0.15%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              21      0.03%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             4      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            26      0.04%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           60101                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    33864601554                       # Total ticks spent queuing
+system.physmem.totMemAccLat               59422351554                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6815400000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       24844.18                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  41400.00                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.59                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.26                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.59                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.26                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  43594.18                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.84                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.45                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.84                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.45                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.83                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     952385                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    441721                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.15                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  47.48                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22489305.50                       # Average gap between requests
-system.physmem.pageHitRate                      66.26                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2710380960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1478878500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4432209600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3052442880                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3094739659440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1177500235590                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27396100823250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31680014630220                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.613444                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45575607610794                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1582177740000                       # Time in different power states
+system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.94                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1093420                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    497646                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.22                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  46.38                       # Row buffer hit rate for writes
+system.physmem.avgGap                     19427177.44                       # Average gap between requests
+system.physmem.pageHitRate                      65.31                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3178488600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1734294375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5058697800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3454513920                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3094741185120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1187868500820                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27387019861500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31683055542135                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.677294                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45560417443643                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1582178520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    223874273456                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    239087007607                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2656364760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1449405375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4722003000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               2976166800                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3094739659440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1182079758375                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27392083725750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31680707083500                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.628058                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45568857815114                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1582177740000                       # Time in different power states
+system.physmem_1.actEnergy                 3210233040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1751615250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5573178000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3498901920                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3094741185120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1203743481615                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27373094439750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31685613034695                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.731270                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45537111526279                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1582178520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    230624127636                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    262392956221                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -379,15 +379,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              125258409                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         88001025                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5802079                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            93100413                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               67841086                       # Number of BTB hits
+system.cpu0.branchPred.lookups              132357688                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         93633614                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5912907                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            98988393                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               72530253                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.868727                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               15085862                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect           1028654                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            73.271472                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               15763072                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect           1049472                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -418,61 +418,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   252652                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               252652                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         7537                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        66702                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples       252652                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         252652    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       252652                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        74239                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22181.016716                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 20809.120487                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 13879.929548                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535        73678     99.24%     99.24% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          179      0.24%     99.49% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          332      0.45%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           14      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           15      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215            8      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        74239                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                   265700                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               265700                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         9033                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        73083                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples       265700                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         265700    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       265700                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        82116                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22524.489746                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 20895.928471                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16961.244602                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        81335     99.05%     99.05% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          195      0.24%     99.29% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          500      0.61%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           20      0.02%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           22      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           13      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           15      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        82116                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples   -909613592                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0     -909613592    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total   -909613592                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        66702     89.85%     89.85% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M         7537     10.15%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        74239                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       252652                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K        73083     89.00%     89.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M         9033     11.00%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        82116                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       265700                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       252652                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        74239                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       265700                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        82116                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        74239                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       326891                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        82116                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       347816                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    81678885                       # DTB read hits
-system.cpu0.dtb.read_misses                    209727                       # DTB read misses
-system.cpu0.dtb.write_hits                   70936828                       # DTB write hits
-system.cpu0.dtb.write_misses                    42925                       # DTB write misses
+system.cpu0.dtb.read_hits                    86394812                       # DTB read hits
+system.cpu0.dtb.read_misses                    220998                       # DTB read misses
+system.cpu0.dtb.write_hits                   74903999                       # DTB write hits
+system.cpu0.dtb.write_misses                    44702                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              37374                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1001                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   33720                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1491                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  8048                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              39659                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1029                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   37665                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1452                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  8673                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9709                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                81888612                       # DTB read accesses
-system.cpu0.dtb.write_accesses               70979753                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    10301                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                86615810                       # DTB read accesses
+system.cpu0.dtb.write_accesses               74948701                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        152615713                       # DTB hits
-system.cpu0.dtb.misses                         252652                       # DTB misses
-system.cpu0.dtb.accesses                    152868365                       # DTB accesses
+system.cpu0.dtb.hits                        161298811                       # DTB hits
+system.cpu0.dtb.misses                         265700                       # DTB misses
+system.cpu0.dtb.accesses                    161564511                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -502,191 +505,191 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    57977                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                57977                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          503                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        46742                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        57977                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          57977    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        57977                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        47245                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 24873.087099                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23068.832563                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 17067.215870                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767        43882     92.88%     92.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535         2853      6.04%     98.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303           11      0.02%     98.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839          288      0.61%     99.55% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607          169      0.36%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375            7      0.01%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143            6      0.01%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911            4      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679           13      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    59769                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                59769                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          498                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        49758                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        59769                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          59769    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        59769                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        50256                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25230.221267                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23083.004989                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 19430.494891                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767        46691     92.91%     92.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535         2859      5.69%     98.60% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303            7      0.01%     98.61% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839          383      0.76%     99.37% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607          254      0.51%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375            9      0.02%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143            4      0.01%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911            6      0.01%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679           25      0.05%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447            8      0.02%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        47245                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::425984-458751            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        50256                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   -910742092                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     -910742092    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total   -910742092                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        46742     98.94%     98.94% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          503      1.06%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        47245                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        49758     99.01%     99.01% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          498      0.99%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        50256                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57977                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57977                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        59769                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        59769                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        47245                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        47245                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       105222                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   224840362                       # ITB inst hits
-system.cpu0.itb.inst_misses                     57977                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        50256                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        50256                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       110025                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   238646690                       # ITB inst hits
+system.cpu0.itb.inst_misses                     59769                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              37374                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1001                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   24328                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              39659                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1029                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   27225                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   193753                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   203945                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               224898339                       # ITB inst accesses
-system.cpu0.itb.hits                        224840362                       # DTB hits
-system.cpu0.itb.misses                          57977                       # DTB misses
-system.cpu0.itb.accesses                    224898339                       # DTB accesses
-system.cpu0.numCycles                       954325944                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               238706459                       # ITB inst accesses
+system.cpu0.itb.hits                        238646690                       # DTB hits
+system.cpu0.itb.misses                          59769                       # DTB misses
+system.cpu0.itb.accesses                    238706459                       # DTB accesses
+system.cpu0.numCycles                      1007854766                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                  417810947                       # Number of instructions committed
-system.cpu0.committedOps                    490605107                       # Number of ops (including micro ops) committed
-system.cpu0.discardedOps                     41344261                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends                     4694                       # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles                 93809718025                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi                              2.284109                       # CPI: cycles per instruction
-system.cpu0.ipc                              0.437807                       # IPC: instructions per cycle
+system.cpu0.committedInsts                  441362500                       # Number of instructions committed
+system.cpu0.committedOps                    518398273                       # Number of ops (including micro ops) committed
+system.cpu0.discardedOps                     43962057                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends                     5117                       # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles                 93756283149                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi                              2.283508                       # CPI: cycles per instruction
+system.cpu0.ipc                              0.437923                       # IPC: instructions per cycle
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4756                       # number of quiesce instructions executed
-system.cpu0.tickCycles                      674001287                       # Number of cycles that the object actually ticked
-system.cpu0.idleCycles                      280324657                       # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements          5190067                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          482.757722                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          144829115                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5190578                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            27.902310                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                    5202                       # number of quiesce instructions executed
+system.cpu0.tickCycles                      710760418                       # Number of cycles that the object actually ticked
+system.cpu0.idleCycles                      297094348                       # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements          5529190                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          480.574807                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          153025870                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5529699                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            27.673454                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       7690769000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   482.757722                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.942886                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.942886                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           45                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        307937411                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       307937411                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     74836049                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       74836049                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     65744025                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      65744025                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       248898                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       248898                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       135683                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       135683                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1688860                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1688860                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1659238                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1659238                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    140580074                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       140580074                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    140828972                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      140828972                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3204136                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3204136                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      2171939                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2171939                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       583430                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       583430                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       728874                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       728874                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       150550                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       150550                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       178568                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       178568                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      5376075                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       5376075                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5959505                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5959505                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  51043675000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  51043675000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  55065851500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  55065851500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  67163849000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  67163849000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2254990500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2254990500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5008928500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   5008928500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5076500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5076500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 106109526500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 106109526500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 106109526500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 106109526500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     78040185                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     78040185                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     67915964                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     67915964                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       832328                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       832328                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       864557                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       864557                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1839410                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      1839410                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1837806                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1837806                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    145956149                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    145956149                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    146788477                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    146788477                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.041058                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.041058                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.031980                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.031980                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.700962                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.700962                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.843061                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.843061                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.081847                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.081847                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.097164                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.097164                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.036833                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.036833                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.040599                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.040599                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15930.558191                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15930.558191                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25353.314020                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 25353.314020                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92147.406822                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92147.406822                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14978.349386                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14978.349386                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28050.538170                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28050.538170                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.574807                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938623                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.938623                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          387                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        325514940                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       325514940                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     79084139                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       79084139                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     69445340                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      69445340                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       251787                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       251787                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       143392                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       143392                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1790882                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1790882                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1762255                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1762255                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    148529479                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       148529479                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    148781266                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      148781266                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      3438422                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      3438422                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      2286291                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2286291                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       632969                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       632969                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       749661                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       749661                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       167888                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       167888                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       194810                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       194810                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      5724713                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       5724713                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      6357682                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      6357682                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  57301041000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  57301041000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  58503452500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  58503452500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  69078584500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  69078584500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2562226000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2562226000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5482087500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   5482087500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      5099500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      5099500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 115804493500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 115804493500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 115804493500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 115804493500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     82522561                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     82522561                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     71731631                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     71731631                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       884756                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       884756                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       893053                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       893053                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1958770                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1958770                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1957065                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1957065                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    154254192                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    154254192                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    155138948                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    155138948                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.041666                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.041666                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.031873                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.031873                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.715416                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.715416                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.839436                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.839436                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.085711                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.085711                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.099542                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.099542                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.037112                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.037112                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.040981                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.040981                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16664.923910                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 16664.923910                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25588.804094                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 25588.804094                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92146.429519                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92146.429519                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15261.519584                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15261.519584                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28140.688363                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28140.688363                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19737.359784                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19737.359784                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17805.090607                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17805.090607                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20228.873220                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 20228.873220                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18214.892393                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18214.892393                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -695,161 +698,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      5190079                       # number of writebacks
-system.cpu0.dcache.writebacks::total          5190079                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       389569                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       389569                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       893829                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       893829                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           64                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total           64                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        40085                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        40085                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           63                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total           63                       # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1283398                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1283398                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1283398                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1283398                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2814567                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      2814567                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1278110                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1278110                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       581694                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       581694                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       728810                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       728810                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       110465                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       110465                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       178505                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       178505                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4092677                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4092677                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4674371                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4674371                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16748                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16748                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18251                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18251                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34999                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34999                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  40095557000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  40095557000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32063318500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  32063318500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14032843000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14032843000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  66427837000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  66427837000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1488538500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1488538500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4826102000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4826102000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      4518500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      4518500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  72158875500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  72158875500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  86191718500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  86191718500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3021431000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3021431000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3257996500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3257996500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6279427500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6279427500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036066                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036066                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018819                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018819                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.698876                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.698876                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.842987                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.842987                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.060055                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060055                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.097129                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.097129                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028040                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028040                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031844                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031844                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.728384                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14245.728384                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25086.509377                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25086.509377                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24124.097893                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.097893                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91145.616827                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91145.616827                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13475.204816                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13475.204816                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27036.228677                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27036.228677                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5529208                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5529208                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       425438                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       425438                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data       937459                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       937459                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data           53                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total           53                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        41154                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        41154                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data           15                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.StoreCondReq_mshr_hits::total           15                       # number of StoreCondReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1362897                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1362897                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1362897                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1362897                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3012984                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3012984                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1348832                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1348832                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       631309                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       631309                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       749608                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       749608                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       126734                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       126734                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       194795                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       194795                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4361816                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4361816                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4993125                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4993125                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15485                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        15485                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16430                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16430                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31915                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        31915                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  44936822000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  44936822000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  34248227000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  34248227000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  15688131000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  15688131000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  68324152500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  68324152500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1728085500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1728085500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5286161500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5286161500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      5009500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      5009500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  79185049000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  79185049000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  94873180000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  94873180000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2777500000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2777500000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2891122000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2891122000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5668622000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5668622000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036511                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036511                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018804                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018804                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.713540                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.713540                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.839377                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.839377                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064701                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064701                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.099534                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.099534                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028277                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028277                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032185                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032185                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14914.391182                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14914.391182                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25391.024976                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25391.024976                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24850.162123                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24850.162123                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91146.509242                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91146.509242                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13635.531901                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13635.531901                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27137.049206                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27137.049206                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17631.216805                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17631.216805                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18439.212142                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18439.212142                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180405.481251                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180405.481251                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178510.574763                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 178510.574763                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179417.340495                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179417.340495                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18154.147034                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18154.147034                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19000.762048                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19000.762048                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179367.129480                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179367.129480                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175966.037736                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175966.037736                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177616.230613                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177616.230613                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          8911456                       # number of replacements
+system.cpu0.icache.tags.replacements          8961850                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.890744                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          215729294                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          8911968                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            24.206695                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.total_refs          229474819                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          8962362                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            25.604279                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      40343615000                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.890744                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999787                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999787                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          131                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          330                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        458194521                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       458194521                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    215729294                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      215729294                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    215729294                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       215729294                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    215729294                       # number of overall hits
-system.cpu0.icache.overall_hits::total      215729294                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      8911978                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      8911978                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      8911978                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       8911978                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      8911978                       # number of overall misses
-system.cpu0.icache.overall_misses::total      8911978                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  92482342000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  92482342000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  92482342000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  92482342000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  92482342000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  92482342000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    224641272                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    224641272                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    224641272                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    224641272                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    224641272                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    224641272                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.039672                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.039672                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.039672                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.039672                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.039672                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.039672                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10377.308158                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10377.308158                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10377.308158                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10377.308158                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10377.308158                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10377.308158                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        485836753                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       485836753                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    229474819                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      229474819                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    229474819                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       229474819                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    229474819                       # number of overall hits
+system.cpu0.icache.overall_hits::total      229474819                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      8962372                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      8962372                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      8962372                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       8962372                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      8962372                       # number of overall misses
+system.cpu0.icache.overall_misses::total      8962372                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  94471116000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  94471116000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  94471116000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  94471116000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  94471116000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  94471116000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    238437191                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    238437191                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    238437191                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    238437191                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    238437191                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    238437191                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.037588                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.037588                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.037588                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.037588                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.037588                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.037588                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10540.860835                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10540.860835                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10540.860835                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10540.860835                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10540.860835                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10540.860835                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -858,499 +861,491 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      8911456                       # number of writebacks
-system.cpu0.icache.writebacks::total          8911456                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8911978                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      8911978                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      8911978                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      8911978                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      8911978                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      8911978                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      8961850                       # number of writebacks
+system.cpu0.icache.writebacks::total          8961850                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8962372                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      8962372                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      8962372                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      8962372                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      8962372                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      8962372                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        52309                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        52309                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  88026353500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  88026353500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  88026353500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  88026353500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  88026353500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  88026353500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  89989930500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  89989930500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  89989930500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  89989930500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  89989930500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  89989930500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   7414627000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   7414627000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   7414627000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   7414627000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.039672                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.039672                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.039672                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.039672                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.039672                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.039672                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst  9877.308214                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total  9877.308214                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst  9877.308214                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total  9877.308214                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst  9877.308214                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total  9877.308214                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.037588                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.037588                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.037588                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.037588                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.037588                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.037588                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10040.860890                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10040.860890                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10040.860890                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10040.860890                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10040.860890                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10040.860890                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7009428                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7009488                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           54                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7773827                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7774021                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit          173                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       921168                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2475518                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16200.233462                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          22065601                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2491662                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            8.855776                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage      1015459                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2700718                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16213.055668                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          22438549                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2716794                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            8.259201                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle      9049945000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15248.600129                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    44.173698                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    44.219033                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   863.240603                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.930701                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002696                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.002699                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.052688                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.988784                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1264                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           48                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14832                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           13                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          796                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          176                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          279                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           32                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           10                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1045                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5479                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6042                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2161                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.077148                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.002930                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.905273                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       474836128                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      474836128                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       472021                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       147981                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        620002                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      3408595                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      3408595                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks     10690717                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total     10690717                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          115                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total          115                       # number of UpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       789207                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       789207                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8250320                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      8250320                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2605662                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2605662                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       165539                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       165539                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       472021                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       147981                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      8250320                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3394869                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       12265191                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       472021                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       147981                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      8250320                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3394869                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      12265191                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10450                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7208                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        17658                       # number of ReadReq misses
-system.cpu0.l2cache.WritebackClean_misses::writebacks            1                       # number of WritebackClean misses
-system.cpu0.l2cache.WritebackClean_misses::total            1                       # number of WritebackClean misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       242851                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       242851                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       178501                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       178501                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       254335                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       254335                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       661657                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       661657                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       900762                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       900762                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       561341                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       561341                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10450                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7208                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       661657                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1155097                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1834412                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10450                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7208                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       661657                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1155097                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1834412                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    323189500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    243712500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total    566902000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3278340000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   3278340000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1776981500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1776981500                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      4439499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      4439499                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  15942119997                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  15942119997                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  24805875000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  24805875000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  33147375490                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  33147375490                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  64101878000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total  64101878000                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    323189500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    243712500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  24805875000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  49089495487                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  74462272487                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    323189500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    243712500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  24805875000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  49089495487                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  74462272487                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       482471                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       155189                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       637660                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3408595                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total      3408595                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks     10690718                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total     10690718                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       242966                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       242966                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       178501                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       178501                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1043542                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1043542                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      8911977                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      8911977                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3506424                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      3506424                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       726880                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       726880                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       482471                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       155189                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      8911977                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      4549966                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     14099603                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       482471                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       155189                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      8911977                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      4549966                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     14099603                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.021659                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.046447                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.027692                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
-system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999527                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999527                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15223.315465                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    55.903430                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    54.295505                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   879.541268                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.929157                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003412                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003314                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.053683                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.989566                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1224                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           54                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14798                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           14                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          814                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          181                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          215                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           41                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          997                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5507                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6189                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2013                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.074707                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003296                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.903198                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       488653498                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      488653498                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       497387                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       151168                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        648555                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      3589798                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      3589798                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks     10898588                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total     10898588                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          348                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total          348                       # number of UpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       828045                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       828045                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      8251361                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      8251361                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2786170                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2786170                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       167822                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       167822                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       497387                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       151168                       # number of demand (read+write) hits
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+system.cpu0.l2cache.demand_hits::total       12514131                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       497387                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       151168                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      8251361                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3614215                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      12514131                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11281                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7561                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        18842                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       256026                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       256026                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       194786                       # number of SCUpgradeReq misses
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+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            9                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            9                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       272487                       # number of ReadExReq misses
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+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       711010                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       711010                       # number of ReadCleanReq misses
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+system.cpu0.l2cache.ReadSharedReq_misses::total       984601                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       580093                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       580093                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        11281                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7561                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       711010                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1257088                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      1986940                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11281                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7561                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       711010                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1257088                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      1986940                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    432507500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    322890000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total    755397500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3595898500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   3595898500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1942602000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1942602000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      4921998                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      4921998                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  17184690000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  17184690000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  26717037500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  26717037500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  38302477992                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  38302477992                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  65953326000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  65953326000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    432507500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    322890000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  26717037500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  55487167992                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  82959602992                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    432507500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    322890000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  26717037500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  55487167992                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  82959602992                       # number of overall miss cycles
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+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       158729                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       667397                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3589798                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      3589798                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks     10898588                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total     10898588                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       256374                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       256374                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       194786                       # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            9                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            9                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1100532                       # number of ReadExReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      8962371                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      8962371                       # number of ReadCleanReq accesses(hits+misses)
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+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       747915                       # number of InvalidateReq accesses(hits+misses)
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+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       508668                       # number of demand (read+write) accesses
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+system.cpu0.l2cache.overall_accesses::total     14501071                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.022178                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.047635                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.028232                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998643                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998643                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.243723                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.243723                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.074244                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.074244                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.256889                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.256889                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.772261                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.772261                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.021659                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.046447                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.074244                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.253869                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.130104                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.021659                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.046447                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.074244                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.253869                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.130104                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30927.224880                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33811.390122                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32104.541851                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13499.388514                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13499.388514                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9955.022661                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9955.022661                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1109874.750000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1109874.750000                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62681.581367                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62681.581367                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37490.535126                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37490.535126                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36799.260504                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36799.260504                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 114194.184996                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 114194.184996                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30927.224880                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33811.390122                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37490.535126                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42498.158585                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 40591.902194                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30927.224880                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33811.390122                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37490.535126                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42498.158585                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 40591.902194                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.247596                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.247596                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.079333                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.079333                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.261114                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.261114                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.775614                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.775614                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.022178                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.047635                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.079333                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.258060                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.137020                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.022178                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.047635                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.079333                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.258060                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.137020                       # miss rate for overall accesses
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+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42704.668695                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 40091.152744                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14045.052065                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14045.052065                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  9973.006274                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  9973.006274                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 546888.666667                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 546888.666667                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63066.091226                       # average ReadExReq miss latency
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+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37576.176847                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37576.176847                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38901.522538                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38901.522538                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 113694.400725                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 113694.400725                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38339.464586                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42704.668695                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37576.176847                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44139.446079                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 41752.444962                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38339.464586                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42704.668695                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37576.176847                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44139.446079                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 41752.444962                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           34                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           34                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1435569                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1435569                       # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks      1535075                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1535075                       # number of writebacks
 system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker            2                       # number of ReadReq MSHR hits
 system.cpu0.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         4123                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         4123                       # number of ReadExReq MSHR hits
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 system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker            2                       # number of overall MSHR hits
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   6996155000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2887260500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   9883415500                       # number of ReadReq MSHR uncacheable cycles
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 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   6996155000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   6008334000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  13004489000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.021659                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.046434                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.027689                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
-system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
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 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999527                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999527                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998643                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998643                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.239772                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.239772                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.074243                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.074243                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.256623                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.256623                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.772261                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.772261                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.021659                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.046434                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.074243                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.252758                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.129745                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.021659                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.046434                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.074243                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.252758                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.242429                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.242429                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.079332                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.079332                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.260815                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.260815                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.775614                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.775614                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.022178                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.047622                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.079332                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.256661                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.136550                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.022178                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.047622                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.079332                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.256661                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.178601                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26106.536022                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41102.047113                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30802.220271                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30802.220271                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19512.736623                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19512.736623                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1031874.750000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031874.750000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55487.890257                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.890257                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31490.545606                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31490.545606                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30754.680317                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30754.680317                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108194.184996                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108194.184996                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31490.545606                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36135.828071                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34358.895348                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31490.545606                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36135.828071                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36203.474366                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.189248                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34093.365180                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46802.000652                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31159.903678                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31159.903678                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19615.493408                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19615.493408                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       510222                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       510222                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55365.484012                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55365.484012                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31576.214868                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31576.214868                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32859.363553                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32859.363553                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107694.400725                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107694.400725                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31576.214868                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37662.039004                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35442.839203                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31576.214868                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37662.039004                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38605.937054                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172394.345594                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143119.676499                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171008.355707                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171008.355707                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171357.087504                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142337.367614                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168463.177115                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168463.177115                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171671.590617                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 148949.569341                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169867.288109                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 147433.860895                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests     29004574                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     14815953                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2223                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops      1990994                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1990568                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          426                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        781840                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     13286786                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        18251                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        18251                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      4847792                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean     10690718                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      2645908                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       891756                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       444613                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       320296                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       480335                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           85                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1119465                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1052013                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      8911978                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4503059                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       735449                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       726880                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     26838850                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     16809682                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       328338                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1022103                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         44998973                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1143972032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    629474552                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1241512                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      3859768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1778547864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    6630650                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     21811897                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.104823                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.306390                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests     29837081                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     15255646                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2671                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops      2145858                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2145409                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          449                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        816702                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     13639128                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        16430                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        16430                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5128977                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean     10898588                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2922524                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       983530                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       456186                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       346923                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       512261                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           65                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          111                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1174017                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1108975                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      8962372                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4744543                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       755832                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       747915                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     26989618                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17891664                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       337201                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1079102                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         46297585                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side   1150395968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    671911459                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1269832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4069344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1827646603                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    7092856                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     22718303                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.108382                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.310926                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          19525925     89.52%     89.52% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2285546     10.48%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               426      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          20256496     89.16%     89.16% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           2461358     10.83%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2               449      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      21811897                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   28866629481                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      22718303                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   29677749987                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    172367004                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    177431926                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy  13449935466                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy  13525621280                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   7428549534                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   7933800899                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    173196405                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    178529385                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    539756748                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    570584194                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              127068265                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         89752795                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6099791                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            94409743                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               68319168                       # Number of BTB hits
+system.cpu1.branchPred.lookups              131141392                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         92458444                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6313157                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            97645974                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               70218111                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            72.364531                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               15069899                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            999135                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            71.910913                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               15567912                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect           1046402                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1380,62 +1375,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   271482                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               271482                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         7964                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        78105                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples       271482                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0         271482    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       271482                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        86069                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 22755.010515                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21243.396519                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15660.005020                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        85331     99.14%     99.14% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          168      0.20%     99.34% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          495      0.58%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           14      0.02%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           20      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           15      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           22      0.03%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                   286101                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               286101                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         9457                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        80855                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples       286101                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         286101    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       286101                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        90312                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23344.699486                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21447.607691                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 19228.959334                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        89271     98.85%     98.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071          163      0.18%     99.03% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          728      0.81%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           35      0.04%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           43      0.05%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           28      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           30      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        86069                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        90312                       # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walksPending::samples    527505760                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0      527505760    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total    527505760                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        78105     90.75%     90.75% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         7964      9.25%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        86069                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       271482                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K        80855     89.53%     89.53% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         9457     10.47%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        90312                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       286101                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       271482                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        86069                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       286101                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        90312                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        86069                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       357551                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        90312                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       376413                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    82675138                       # DTB read hits
-system.cpu1.dtb.read_misses                    225741                       # DTB read misses
-system.cpu1.dtb.write_hits                   73180273                       # DTB write hits
-system.cpu1.dtb.write_misses                    45741                       # DTB write misses
+system.cpu1.dtb.read_hits                    84597106                       # DTB read hits
+system.cpu1.dtb.read_misses                    236435                       # DTB read misses
+system.cpu1.dtb.write_hits                   75395592                       # DTB write hits
+system.cpu1.dtb.write_misses                    49666                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              37374                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1001                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   37272                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     1666                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  8268                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              39659                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1029                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   35920                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     1878                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8819                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    11369                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                82900879                       # DTB read accesses
-system.cpu1.dtb.write_accesses               73226014                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    11434                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                84833541                       # DTB read accesses
+system.cpu1.dtb.write_accesses               75445258                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        155855411                       # DTB hits
-system.cpu1.dtb.misses                         271482                       # DTB misses
-system.cpu1.dtb.accesses                    156126893                       # DTB accesses
+system.cpu1.dtb.hits                        159992698                       # DTB hits
+system.cpu1.dtb.misses                         286101                       # DTB misses
+system.cpu1.dtb.accesses                    160278799                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1465,186 +1461,186 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    69604                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                69604                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          666                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        61994                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        69604                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          69604    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        69604                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        62660                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 25321.249601                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23483.555874                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 17582.582178                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        61881     98.76%     98.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071           12      0.02%     98.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          712      1.14%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           23      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           20      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    70499                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                70499                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          664                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        63113                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        70499                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          70499    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        70499                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        63777                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26275.796917                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23950.266979                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 21020.894290                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        62694     98.30%     98.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071            8      0.01%     98.31% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          977      1.53%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           22      0.03%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           42      0.07%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           28      0.04%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        62660                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        63777                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples    526611260                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0      526611260    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total    526611260                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        61994     98.94%     98.94% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          666      1.06%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        62660                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        63113     98.96%     98.96% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          664      1.04%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        63777                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        69604                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        69604                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        70499                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        70499                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        62660                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        62660                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       132264                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   226404999                       # ITB inst hits
-system.cpu1.itb.inst_misses                     69604                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        63777                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        63777                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       134276                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   232338774                       # ITB inst hits
+system.cpu1.itb.inst_misses                     70499                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              37374                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1001                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   26762                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              39659                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1029                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   25488                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   203402                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   208774                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               226474603                       # ITB inst accesses
-system.cpu1.itb.hits                        226404999                       # DTB hits
-system.cpu1.itb.misses                          69604                       # DTB misses
-system.cpu1.itb.accesses                    226474603                       # DTB accesses
-system.cpu1.numCycles                       896249910                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               232409273                       # ITB inst accesses
+system.cpu1.itb.hits                        232338774                       # DTB hits
+system.cpu1.itb.misses                          70499                       # DTB misses
+system.cpu1.itb.accesses                    232409273                       # DTB accesses
+system.cpu1.numCycles                       934140798                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                  420934522                       # Number of instructions committed
-system.cpu1.committedOps                    495850522                       # Number of ops (including micro ops) committed
-system.cpu1.discardedOps                     42911431                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends                     4588                       # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles                 93867828238                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi                              2.129191                       # CPI: cycles per instruction
-system.cpu1.ipc                              0.469662                       # IPC: instructions per cycle
+system.cpu1.committedInsts                  431679438                       # Number of instructions committed
+system.cpu1.committedOps                    508807266                       # Number of ops (including micro ops) committed
+system.cpu1.discardedOps                     44929639                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends                     4564                       # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles                 93829974504                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi                              2.163969                       # CPI: cycles per instruction
+system.cpu1.ipc                              0.462114                       # IPC: instructions per cycle
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   13511                       # number of quiesce instructions executed
-system.cpu1.tickCycles                      680922299                       # Number of cycles that the object actually ticked
-system.cpu1.idleCycles                      215327611                       # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements          4921419                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          458.899025                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          148299852                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          4921931                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            30.130421                       # Average number of references to valid blocks.
+system.cpu1.kern.inst.quiesce                   13472                       # number of quiesce instructions executed
+system.cpu1.tickCycles                      702823433                       # Number of cycles that the object actually ticked
+system.cpu1.idleCycles                      231317365                       # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements          5070717                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          459.449189                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          152180192                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5071229                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            30.008543                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     8388824602000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   458.899025                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.896287                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.896287                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   459.449189                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.897362                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.897362                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          348                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           40                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        313981831                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       313981831                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     76035057                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       76035057                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     68321160                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      68321160                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       232478                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       232478                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       184182                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       184182                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1549703                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1549703                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1524262                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1524262                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    144356217                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       144356217                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    144588695                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      144588695                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      3124160                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      3124160                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      2104338                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      2104338                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       561771                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       561771                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       510720                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       510720                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       156544                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       156544                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       180437                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       180437                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      5228498                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       5228498                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      5790269                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      5790269                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  48221817000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  48221817000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  44559226500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  44559226500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  19302885000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  19302885000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2427765500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2427765500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5104015500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   5104015500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      7589000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      7589000                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  92781043500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  92781043500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  92781043500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  92781043500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     79159217                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     79159217                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     70425498                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     70425498                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       794249                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       794249                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       694902                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       694902                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1706247                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1706247                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1704699                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1704699                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    149584715                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    149584715                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    150378964                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    150378964                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039467                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.039467                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029880                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.029880                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.707298                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.707298                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.734953                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.734953                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.091748                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.091748                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105847                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105847                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034953                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.034953                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.038505                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.038505                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15435.130403                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15435.130403                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21174.937914                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21174.937914                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37795.435855                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37795.435855                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15508.518372                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15508.518372                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28286.967196                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28286.967196                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses        322309894                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       322309894                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     77705355                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       77705355                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     70371137                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      70371137                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       247594                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       247594                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       180643                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       180643                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1624088                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1624088                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1588942                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1588942                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    148076492                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       148076492                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    148324086                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      148324086                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      3222913                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      3222913                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      2183254                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      2183254                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       592382                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       592382                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       513289                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       513289                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       153645                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       153645                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       187516                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       187516                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      5406167                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       5406167                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      5998549                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      5998549                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  52049628500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  52049628500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  47596189000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  47596189000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20614887000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  20614887000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2521232500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2521232500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5224495500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   5224495500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      4869500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      4869500                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  99645817500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  99645817500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  99645817500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  99645817500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     80928268                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     80928268                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     72554391                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     72554391                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       839976                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       839976                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       693932                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       693932                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1777733                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1777733                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1776458                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1776458                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    153482659                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    153482659                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    154322635                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    154322635                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.039824                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.039824                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030091                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030091                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.705237                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.705237                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.739682                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.739682                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.086427                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.086427                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.105556                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.105556                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.035223                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.035223                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.038870                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.038870                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16149.870785                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16149.870785                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21800.573364                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21800.573364                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 40162.339345                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 40162.339345                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16409.466628                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16409.466628                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27861.598477                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27861.598477                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17745.257529                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17745.257529                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16023.615397                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16023.615397                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18431.879278                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18431.879278                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16611.653502                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16611.653502                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1653,161 +1649,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      4921438                       # number of writebacks
-system.cpu1.dcache.writebacks::total          4921438                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       336855                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       336855                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       865157                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       865157                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data           99                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total           99                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        39963                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        39963                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           44                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total           44                       # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1202012                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1202012                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1202012                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1202012                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2787305                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2787305                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1239181                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1239181                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       561309                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       561309                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       510621                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       510621                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       116581                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       116581                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       180393                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       180393                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4026486                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4026486                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4587795                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4587795                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        20902                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        20902                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        19312                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        19312                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        40214                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        40214                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  38841507500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  38841507500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26434060500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26434060500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12644921000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12644921000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  18783135000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  18783135000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1568875000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1568875000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4920605000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4920605000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      7128000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      7128000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  65275568000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  65275568000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  77920489000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  77920489000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3868216000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3868216000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3618681000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3618681000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   7486897000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7486897000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035211                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035211                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017596                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017596                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.706717                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.706717                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.734810                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.734810                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.068326                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.068326                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105821                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105821                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026918                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026918                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030508                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.030508                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13935.147930                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13935.147930                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21331.880089                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21331.880089                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22527.557905                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22527.557905                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36784.885463                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36784.885463                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13457.381563                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13457.381563                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27277.139357                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27277.139357                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      5070732                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5070732                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       348629                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       348629                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       899898                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       899898                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data          110                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total          110                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        43396                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        43396                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data           20                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total           20                       # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1248527                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1248527                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1248527                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1248527                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2874284                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2874284                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1283356                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1283356                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       591957                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       591957                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       513179                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       513179                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       110249                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       110249                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       187496                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       187496                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4157640                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4157640                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4749597                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4749597                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        22695                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        22695                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        21647                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        21647                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        44342                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        44342                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  41633767000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  41633767000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  28169318500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  28169318500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  14402198000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  14402198000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  20089556500                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  20089556500                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1594381500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1594381500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5035777500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5035777500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      4638000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      4638000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  69803085500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  69803085500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  84205283500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  84205283500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   4145895000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   4145895000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   4016889500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   4016889500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   8162784500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   8162784500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035516                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035516                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017688                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017688                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.704731                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.704731                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.739523                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.739523                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062017                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.062017                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.105545                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.105545                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027089                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027089                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.030777                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.030777                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14484.917635                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14484.917635                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21949.730628                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21949.730628                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24329.804361                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24329.804361                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39147.269276                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 39147.269276                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14461.641375                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14461.641375                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26858.052972                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26858.052972                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16211.547240                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16211.547240                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16984.300519                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16984.300519                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185064.395752                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185064.395752                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187379.919221                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187379.919221                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186176.381360                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186176.381360                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16789.112453                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16789.112453                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17728.932265                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17728.932265                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182678.783873                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182678.783873                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 185563.334411                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 185563.334411                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184086.971720                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 184086.971720                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          9409188                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          506.684863                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          216784534                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          9409700                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            23.038411                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements          9965841                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          506.684865                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          222156193                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          9966353                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            22.290621                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle     8388652871500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.684863                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   506.684865                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.989619                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.989619                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          281                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          170                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        461798168                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       461798168                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    216784534                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      216784534                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    216784534                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       216784534                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    216784534                       # number of overall hits
-system.cpu1.icache.overall_hits::total      216784534                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      9409700                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      9409700                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      9409700                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       9409700                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      9409700                       # number of overall misses
-system.cpu1.icache.overall_misses::total      9409700                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  95979801000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  95979801000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  95979801000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  95979801000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  95979801000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  95979801000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    226194234                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    226194234                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    226194234                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    226194234                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    226194234                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    226194234                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.041600                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.041600                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.041600                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.041600                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.041600                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.041600                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10200.091501                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10200.091501                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10200.091501                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10200.091501                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10200.091501                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10200.091501                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        474211445                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       474211445                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    222156193                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      222156193                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    222156193                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       222156193                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    222156193                       # number of overall hits
+system.cpu1.icache.overall_hits::total      222156193                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      9966353                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      9966353                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      9966353                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       9966353                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      9966353                       # number of overall misses
+system.cpu1.icache.overall_misses::total      9966353                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 101175482500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 101175482500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 101175482500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 101175482500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 101175482500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 101175482500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    232122546                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    232122546                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    232122546                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    232122546                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    232122546                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    232122546                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.042936                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.042936                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.042936                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.042936                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.042936                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.042936                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10151.705694                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10151.705694                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10151.705694                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10151.705694                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10151.705694                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10151.705694                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1816,254 +1812,256 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks      9409188                       # number of writebacks
-system.cpu1.icache.writebacks::total          9409188                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9409700                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      9409700                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      9409700                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      9409700                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      9409700                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      9409700                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      9965841                       # number of writebacks
+system.cpu1.icache.writebacks::total          9965841                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      9966353                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      9966353                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      9966353                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      9966353                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      9966353                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      9966353                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           92                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           92                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           92                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           92                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  91274951000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  91274951000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  91274951000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  91274951000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  91274951000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  91274951000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  96192306000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  96192306000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  96192306000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  96192306000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  96192306000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  96192306000                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12950500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     12950500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     12950500                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total     12950500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.041600                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.041600                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.041600                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.041600                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.041600                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.041600                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9700.091501                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9700.091501                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9700.091501                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  9700.091501                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9700.091501                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  9700.091501                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.042936                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.042936                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.042936                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.042936                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.042936                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.042936                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  9651.705694                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  9651.705694                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  9651.705694                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  9651.705694                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  9651.705694                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  9651.705694                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      6599308                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      6600409                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit          970                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6510084                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6511152                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit          939                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       793623                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2151198                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13377.061252                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          23203065                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2166951                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           10.707702                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    9986150274500                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12523.259690                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    66.377906                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    74.184237                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   713.239419                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.764359                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004051                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004528                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.043533                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.816471                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          985                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023          109                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14659                       # Occupied blocks per task id
+system.cpu1.l2cache.prefetcher.pfSpanPage       783896                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2135895                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13423.461637                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          24573645                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2151628                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           11.420954                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    9991507442000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12589.805999                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    67.598025                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    73.072993                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   692.984620                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.768421                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004126                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004460                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.042296                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.819303                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          945                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           96                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14692                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            9                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          173                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          750                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          185                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          707                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1022::4           51                       # Occupied blocks per task id
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-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           59                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           46                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1249                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4750                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8044                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4          438                       # Occupied blocks per task id
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-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.894714                       # Percentage of cache occupancy per task id
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+system.cpu1.l2cache.demand_miss_latency::cpu1.data  47377989489                       # number of demand (read+write) miss cycles
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+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    470190500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    378267000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  25012449000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  47377989489                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  73238895989                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       562676                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       194962                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       757638                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3212997                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3212997                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks     11821046                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total     11821046                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       205064                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       205064                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       187493                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       187493                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            3                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1080983                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1080983                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      9966353                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      9966353                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3576103                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3576103                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       511224                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       511224                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       562676                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       194962                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      9966353                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4657086                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     15381077                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       562676                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       194962                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      9966353                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4657086                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     15381077                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.019210                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.041562                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.024962                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
+system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.998191                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.998191                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.230404                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.230404                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.073465                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.073465                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.248849                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.248849                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.523368                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.523368                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.019792                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.040652                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.073465                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.244594                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.123779                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.019792                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.040652                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.073465                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.244594                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.123779                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 34555.709773                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38428.284790                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36201.959058                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16465.235718                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16465.235718                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10064.222676                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10064.222676                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1400799.800000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1400799.800000                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48359.332503                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48359.332503                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35425.210080                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35425.210080                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35570.402027                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35570.402027                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 61213.942832                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 61213.942832                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 34555.709773                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38428.284790                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35425.210080                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38349.728559                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 37211.890229                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 34555.709773                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38428.284790                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35425.210080                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38349.728559                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 37211.890229                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.224294                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.224294                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.066850                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.066850                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.245513                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.245513                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.512572                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.512572                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.019210                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.041562                       # miss rate for demand accesses
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+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44863.446489                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15972.854470                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15972.854470                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9689.809753                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  9689.809753                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1517833                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1517833                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53384.408842                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53384.408842                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37541.911943                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37541.911943                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39220.200586                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39220.200586                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 66939.383069                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 66939.383069                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 43499.907485                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46682.339874                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37541.911943                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42285.277520                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 40562.015010                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 43499.907485                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46682.339874                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37541.911943                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42285.277520                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 40562.015010                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2072,236 +2070,239 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1042577                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1042577                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            1                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         4272                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         4272                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            7                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            7                       # number of ReadCleanReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         1142                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         1142                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker            1                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            7                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         5414                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         5422                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker            1                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            7                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         5414                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         5422                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10447                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7724                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        18171                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       679285                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       679285                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       203082                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       203082                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       180388                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       180388                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       235133                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       235133                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       691276                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       691276                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       861063                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       861063                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       266022                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       266022                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10447                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7724                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       691276                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1096196                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1805643                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10447                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7724                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       691276                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1096196                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       679285                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2484928                       # number of overall MSHR misses
+system.cpu1.l2cache.writebacks::writebacks      1050489                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1050489                       # number of writebacks
+system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker            3                       # number of ReadReq MSHR hits
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+system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            8                       # number of ReadCleanReq MSHR hits
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+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         7034                       # number of demand (read+write) MSHR hits
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+system.cpu1.l2cache.overall_mshr_hits::cpu1.data         7034                       # number of overall MSHR hits
+system.cpu1.l2cache.overall_mshr_hits::total         7045                       # number of overall MSHR hits
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        10809                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         8100                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.ReadReq_mshr_misses::total        18909                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            2                       # number of WritebackDirty MSHR misses
+system.cpu1.l2cache.WritebackDirty_mshr_misses::total            2                       # number of WritebackDirty MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       706258                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total       706258                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       204693                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.UpgradeReq_mshr_misses::total       204693                       # number of UpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       187493                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       187493                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            3                       # number of SCUpgradeFailReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       236605                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::total       236605                       # number of ReadExReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       666246                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       666246                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       876798                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       876798                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       262039                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       262039                       # number of InvalidateReq MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        10809                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         8100                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       666246                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1113403                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.demand_mshr_misses::total      1798558                       # number of demand (read+write) MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        10809                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         8100                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       666246                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1113403                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       706258                       # number of overall MSHR misses
+system.cpu1.l2cache.overall_mshr_misses::total      2504816                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           92                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        20902                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        20994                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        19312                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        19312                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        22695                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        22787                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        21647                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        21647                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           92                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        40214                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        40306                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    298321500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    250498000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    548819500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  24534893187                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  24534893187                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   6599396497                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   6599396497                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3563733500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3563733500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      6517999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      6517999                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   9585687998                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   9585687998                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  20341013500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  20341013500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  25423220980                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  25423220980                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  14688123500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  14688123500                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    298321500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    250498000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  20341013500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  35008908978                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  55898741978                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    298321500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    250498000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  20341013500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  35008908978                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  24534893187                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  80433635165                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        44342                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        44434                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    405336500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    329621500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    734958000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  32803670450                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  32803670450                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   6637113997                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   6637113997                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3625235500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3625235500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      4217499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4217499                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  10699007999                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  10699007999                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  21014773500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  21014773500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  29089304990                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  29089304990                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  15968495000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  15968495000                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    405336500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    329621500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  21014773500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  39788312989                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total  61538044489                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    405336500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    329621500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  21014773500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  39788312989                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  32803670450                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::total  94341714939                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     12214500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3700892500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3713107000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3473788500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3473788500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3964210500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3976425000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3854486000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3854486000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     12214500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7174681000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7186895500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.019792                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.040647                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.025312                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7818696500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7830911000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.019210                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.041547                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.024958                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.999031                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.999031                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.998191                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.998191                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.226292                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.226292                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.073464                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.073464                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.248519                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248519                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.523368                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.523368                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.019792                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.040647                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.073464                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.243392                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.123409                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.019792                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.040647                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.073464                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.243392                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.218879                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.218879                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.066850                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.066850                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.245183                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.245183                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.512572                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.512572                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.019210                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.041547                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.066850                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.239077                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.116933                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.019210                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.041547                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.066850                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.239077                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.169835                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30203.043311                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36118.703029                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32496.215800                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32496.215800                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19755.934430                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19755.934430                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1303599.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1303599.800000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 40767.089256                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 40767.089256                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29425.314202                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29425.314202                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29525.390105                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29525.390105                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55213.942832                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55213.942832                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29425.314202                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31936.723887                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30957.803939                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29425.314202                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31936.723887                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32368.597869                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.162850                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38868.158020                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46447.148846                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32424.723840                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32424.723840                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19335.311185                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19335.311185                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1405833                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1405833                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45218.858431                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45218.858431                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31542.063292                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31542.063292                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33176.746514                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33176.746514                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60939.383069                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60939.383069                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31542.063292                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35735.769518                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34215.212681                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31542.063292                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35735.769518                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37664.129796                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177059.252703                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176865.151948                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179877.200704                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179877.200704                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174673.298083                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174504.103217                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178060.978427                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178060.978427                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178412.518029                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178308.328785                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 176327.105228                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 176236.913175                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests     29428527                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     15006964                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         2768                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops      1972954                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1972589                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          365                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq        814249                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     13775310                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        19312                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        19312                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4142105                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean     11232116                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      2703238                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       874176                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       401941                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       322763                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       444037                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           57                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1114947                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1047219                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9409700                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4456605                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       514166                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       508289                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     28226960                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15947748                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       397923                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1113211                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         45685842                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1204298752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    609360975                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1520224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4222808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1819402759                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    6269077                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     21677519                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.104647                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.306153                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests     30858357                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     15723821                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         2528                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops      1980391                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1980008                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          383                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq        850137                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     14487242                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        21647                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        21647                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4268815                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean     11821046                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      2688015                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       913599                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       423664                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       342986                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       458900                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           58                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          111                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1168045                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1089891                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      9966353                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4640105                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       517058                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       511224                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     29897221                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16450144                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       405579                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1179409                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         47932353                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side   1275569664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    629289128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1559696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4501408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1910919896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    6428198                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     22587485                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.100846                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.301181                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          19409393     89.54%     89.54% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           2267761     10.46%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               365      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          20310003     89.92%     89.92% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2277099     10.08%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2               383      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      21677519                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   29325134974                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      22587485                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   30765191484                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    172530424                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    188815582                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy  14118247362                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy  14953353610                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7236066136                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7474900412                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    207955878                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    210684864                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    585496227                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    616864733                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40404                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40404                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136972                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136972                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47770                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40414                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40414                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136987                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136987                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47846                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2311,18 +2312,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122912                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231760                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231760                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122988                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231734                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231734                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354752                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47790                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354802                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47866                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2332,24 +2331,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155927                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355392                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7355392                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       156003                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355288                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7355288                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7513405                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             47202500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7513377                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             47239500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               315000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                 8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
@@ -2362,767 +2360,764 @@ system.iobus.reqLayer16.occupancy               15500                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25874502                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            26112500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              168500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36405000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            36406501                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           566670204                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              123500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           566812397                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               31500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92927000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92988000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148200000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           148174000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115872                       # number of replacements
-system.iocache.tags.tagsinuse               11.264501                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      6                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115888                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000052                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9145998133000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.414921                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     3.849581                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.463433                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.240599                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.704031                       # Average percentage of cache occupancy
+system.iocache.tags.replacements               115848                       # number of replacements
+system.iocache.tags.tagsinuse               11.264479                       # Cycle average of tags in use
+system.iocache.tags.total_refs                     11                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs               115864                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                 0.000095                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         9145999585000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.415083                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.849396                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.463443                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.240587                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.704030                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1043272                       # Number of tag accesses
-system.iocache.tags.data_accesses             1043272                       # Number of data accesses
-system.iocache.WriteLineReq_hits::realview.ide            2                       # number of WriteLineReq hits
-system.iocache.WriteLineReq_hits::total             2                       # number of WriteLineReq hits
+system.iocache.tags.tag_accesses              1043144                       # Number of tag accesses
+system.iocache.tags.data_accesses             1043144                       # Number of data accesses
+system.iocache.WriteLineReq_hits::realview.ide            6                       # number of WriteLineReq hits
+system.iocache.WriteLineReq_hits::total             6                       # number of WriteLineReq hits
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8896                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8933                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8883                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8920                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106982                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106982                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106978                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106978                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8896                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8936                       # number of demand (read+write) misses
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 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8896                       # number of overall misses
-system.iocache.overall_misses::total             8936                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5261000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1700094991                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1705355991                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8883                       # number of overall misses
+system.iocache.overall_misses::total             8923                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5243500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1665415552                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1670659052                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  14013428406                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  14013428406                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5630000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1700094991                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1705724991                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5630000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1700094991                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1705724991                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  14002624152                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  14002624152                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5612500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1665415552                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1671028052                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5612500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1665415552                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1671028052                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8896                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8933                       # number of ReadReq accesses(hits+misses)
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+system.iocache.ReadReq_accesses::total           8920                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8896                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8936                       # number of demand (read+write) accesses
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 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8896                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8936                       # number of overall (read+write) accesses
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+system.iocache.overall_accesses::total           8923                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide     0.999981                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total     0.999981                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide     0.999944                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total     0.999944                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142189.189189                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 191107.800247                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 190905.182022                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141716.216216                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 187483.457391                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 187293.615695                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130988.656092                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130988.656092                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       140750                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 191107.800247                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 190882.384848                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       140750                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 191107.800247                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 190882.384848                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         36149                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130892.558769                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130892.558769                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 140312.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 187483.457391                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 187271.999552                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 140312.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 187483.457391                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 187271.999552                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         35141                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3721                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3655                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.714862                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.614501                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106948                       # number of writebacks
-system.iocache.writebacks::total               106948                       # number of writebacks
+system.iocache.writebacks::writebacks          106943                       # number of writebacks
+system.iocache.writebacks::total               106943                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8896                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8933                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8883                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8920                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106982                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106982                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106978                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106978                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8896                       # number of demand (read+write) MSHR misses
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 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8896                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8936                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3411000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1255294991                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1258705991                       # number of ReadReq MSHR miss cycles
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+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3393500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1221265552                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1224659052                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8664328406                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8664328406                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3630000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1255294991                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1258924991                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3630000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1255294991                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1258924991                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8653724152                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8653724152                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3612500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1221265552                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1224878052                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3612500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1221265552                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1224878052                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999981                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.999981                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999944                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.999944                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92189.189189                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141107.800247                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 140905.182022                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91716.216216                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137483.457391                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 137293.615695                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80988.656092                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80988.656092                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        90750                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 141107.800247                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 140882.384848                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        90750                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 141107.800247                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 140882.384848                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80892.558769                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80892.558769                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90312.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 137483.457391                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 137271.999552                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90312.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 137483.457391                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 137271.999552                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1047057                       # number of replacements
-system.l2c.tags.tagsinuse                63052.180525                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6067910                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1106756                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     5.482609                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1253630                       # number of replacements
+system.l2c.tags.tagsinuse                63075.564404                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6221998                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1313632                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.736485                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   25661.598067                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    59.549817                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker    63.820457                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     6721.957431                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5596.771487                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  5304.396230                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   138.527549                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   206.635310                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     5419.027786                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     6651.679849                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  7228.216543                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.391565                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000909                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000974                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.102569                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.085400                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.080939                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002114                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003153                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.082688                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.101497                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.110294                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.962100                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022         9310                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          176                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        50213                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0           61                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1          427                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          684                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         1579                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         6559                       # Occupied blocks per task id
+system.l2c.tags.occ_blocks::writebacks   23067.685004                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   146.868876                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   206.473413                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5441.439609                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     6307.681817                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  8428.958067                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   140.047033                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   198.225362                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4720.872050                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     6856.377655                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  7560.935517                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.351985                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002241                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.003151                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.083030                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.096248                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.128616                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002137                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.003025                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.072035                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.104620                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.115371                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.962457                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022         9537                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          240                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        50225                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::0           45                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::1          233                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2          325                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3         1551                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         7383                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3           17                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          158                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          361                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2614                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3        11152                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        36045                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.142059                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.002686                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.766190                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 72230268                       # Number of tag accesses
-system.l2c.tags.data_accesses                72230268                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks      2478146                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         2478146                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data          154381                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          128604                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              282985                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         37860                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         40612                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             78472                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           167086                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           187378                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               354464                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5729                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3917                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       604815                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       555526                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       312245                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6550                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4876                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       643471                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       544206                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       332267                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          3013602                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          5729                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          3917                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              604815                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              722612                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       312245                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6550                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4876                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              643471                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              731584                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       332267                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 3368066                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         5729                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         3917                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             604815                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             722612                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       312245                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6550                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4876                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             643471                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             731584                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       332267                       # number of overall hits
-system.l2c.overall_hits::total                3368066                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         61102                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         58240                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            119342                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        10859                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        11400                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           22259                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         464077                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         119615                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             583692                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker          662                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker          653                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        56835                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data        93190                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       142344                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker          930                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker          967                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        47805                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data        79816                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       118522                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         541724                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker          662                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker          653                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             56835                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            557267                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       142344                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker          930                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker          967                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             47805                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            199431                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       118522                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1125416                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker          662                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker          653                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            56835                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           557267                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       142344                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker          930                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker          967                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            47805                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           199431                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       118522                       # number of overall misses
-system.l2c.overall_misses::total              1125416                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data   1103543500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data   1130362500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total   2233906000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data    187676500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data    195172500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    382849000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  64543141999                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  16037903000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  80581044999                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker     90596000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker     90566500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   7555639500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  12682874000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  22835971280                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    127343000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    132126000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   6369869500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  10891833000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  18778961423                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  79555780203                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker     90596000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker     90566500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   7555639500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  77226015999                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  22835971280                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    127343000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    132126000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   6369869500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  26929736000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  18778961423                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    160136825202                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker     90596000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker     90566500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   7555639500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  77226015999                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  22835971280                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    127343000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    132126000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   6369869500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  26929736000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  18778961423                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   160136825202                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      2478146                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      2478146                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       215483                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       186844                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          402327                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        48719                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        52012                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total        100731                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       631163                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       306993                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           938156                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         6391                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         4570                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       661650                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       648716                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       454589                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         7480                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5843                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       691276                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       624022                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       450789                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3555326                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         6391                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         4570                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          661650                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1279879                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       454589                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         7480                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5843                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          691276                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          931015                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       450789                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4493482                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         6391                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         4570                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         661650                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1279879                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       454589                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         7480                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5843                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         691276                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         931015                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       450789                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4493482                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.283558                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.311704                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.296629                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.222890                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.219180                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.220975                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.735273                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.389634                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.622169                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.103583                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.142888                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.085899                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.143653                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.124332                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.165497                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.069155                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.127906                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.152370                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.103583                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.142888                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.085899                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.435406                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.124332                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.165497                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.069155                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.214208                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.250455                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.103583                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.142888                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.085899                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.435406                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.124332                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.165497                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.069155                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.214208                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.250455                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18060.677228                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19408.696772                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 18718.523236                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17283.037112                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17120.394737                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 17199.739431                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139078.519295                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134079.362956                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 138054.050765                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136851.963746                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138692.955590                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 132939.904988                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136096.941732                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 136927.956989                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 136634.953464                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133246.930237                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 136461.774582                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 146856.665392                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136851.963746                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138692.955590                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 132939.904988                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 138579.919498                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136927.956989                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 136634.953464                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 133246.930237                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 135032.848454                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 142291.228490                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136851.963746                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138692.955590                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 132939.904988                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 138579.919498                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 160428.056539                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136927.956989                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 136634.953464                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 133246.930237                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 135032.848454                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 158442.832748                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 142291.228490                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs              1036                       # number of cycles access was blocked
+system.l2c.tags.age_task_id_blocks_1023::3           10                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          229                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          332                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2638                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        11674                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        35545                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.145523                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003662                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.766373                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 75571866                       # Number of tag accesses
+system.l2c.tags.data_accesses                75571866                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks      2585563                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2585563                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data          160084                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          122219                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              282303                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         41093                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         37320                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             78413                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           164973                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           176191                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               341164                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5942                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.itb.walker         3808                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.inst       649495                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       595249                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       326607                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         6405                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4811                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.inst       608519                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       523825                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       313790                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          3038451                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          5942                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          3808                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              649495                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              760222                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.l2cache.prefetcher       326607                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          6405                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          4811                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              608519                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              700016                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       313790                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 3379615                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         5942                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         3808                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             649495                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             760222                       # number of overall hits
+system.l2c.overall_hits::cpu0.l2cache.prefetcher       326607                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         6405                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         4811                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             608519                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             700016                       # number of overall hits
+system.l2c.overall_hits::cpu1.l2cache.prefetcher       313790                       # number of overall hits
+system.l2c.overall_hits::total                3379615                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         64947                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data         58762                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total            123709                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data        12100                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data        11098                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total           23198                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         478835                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data         137880                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             616715                       # number of ReadExReq misses
+system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1338                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1182                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.inst        61507                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data       116953                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       182171                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1669                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1507                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.inst        57727                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data       105504                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       168487                       # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total         698045                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1338                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker         1182                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             61507                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            595788                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.l2cache.prefetcher       182171                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker         1669                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker         1507                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst             57727                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data            243384                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.l2cache.prefetcher       168487                       # number of demand (read+write) misses
+system.l2c.demand_misses::total               1314760                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker         1338                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker         1182                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            61507                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           595788                       # number of overall misses
+system.l2c.overall_misses::cpu0.l2cache.prefetcher       182171                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker         1669                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker         1507                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst            57727                       # number of overall misses
+system.l2c.overall_misses::cpu1.data           243384                       # number of overall misses
+system.l2c.overall_misses::cpu1.l2cache.prefetcher       168487                       # number of overall misses
+system.l2c.overall_misses::total              1314760                       # number of overall misses
+system.l2c.UpgradeReq_miss_latency::cpu0.data   1164704000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data   1071145000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total   2235849000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data    211169000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data    187264500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total    398433500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data  66775651499                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data  18645271000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  85420922499                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    186837000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    167036500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.inst   8232186000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.data  16101034000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  29946000398                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    234710500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    209918500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   7713073500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data  14641394000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  27273747422                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total 104705937820                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    186837000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    167036500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst   8232186000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  82876685499                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  29946000398                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    234710500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    209918500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst   7713073500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data  33286665000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  27273747422                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    190126860319                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    186837000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    167036500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst   8232186000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  82876685499                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  29946000398                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    234710500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker    209918500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst   7713073500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data  33286665000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  27273747422                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   190126860319                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      2585563                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2585563                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data       225031                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data       180981                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          406012                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        53193                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        48418                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total        101611                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       643808                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       314071                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           957879                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         7280                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         4990                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.inst       711002                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       712202                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       508778                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         8074                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6318                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu1.data       629329                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       482277                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3736496                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         7280                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         4990                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu0.data         1356010                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu1.dtb.walker         8074                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         6318                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu1.data          943400                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       482277                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             4694375                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         7280                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         4990                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       508778                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         8074                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu1.data         943400                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.l2cache.prefetcher       482277                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            4694375                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.288614                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.324686                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.304693                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.227474                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.229212                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.228302                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.743754                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.439009                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.643834                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.183791                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.236874                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.086507                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.164213                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.358056                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.206713                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.238525                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.086645                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.167645                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.349357                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.186818                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.183791                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.236874                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.086507                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.439368                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.358056                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.206713                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.238525                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.086645                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.257986                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.349357                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.280071                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.183791                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.236874                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.086507                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.439368                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.358056                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.206713                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.238525                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.086645                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.257986                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.349357                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.280071                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17933.145488                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18228.532045                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 18073.454640                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17451.983471                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 16873.715985                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 17175.338391                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139454.408093                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 135228.249202                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 138509.558709                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 139639.013453                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141316.835871                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 133841.448941                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137670.978940                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 164384.015008                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140629.418814                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 139295.620438                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133612.928093                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138775.724143                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 161874.491338                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 149998.836493                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 139639.013453                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141316.835871                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 133841.448941                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 139104.321502                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 164384.015008                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140629.418814                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 139295.620438                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 133612.928093                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 136766.036387                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 161874.491338                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 144609.556359                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 139639.013453                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141316.835871                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 133841.448941                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 139104.321502                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 164384.015008                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140629.418814                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 139295.620438                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 133612.928093                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 136766.036387                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 161874.491338                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 144609.556359                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs              2084                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        8                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       32                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs    129.500000                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs     65.125000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              823102                       # number of writebacks
-system.l2c.writebacks::total                   823102                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst          112                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           15                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          123                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           13                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          263                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst            112                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             15                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst            123                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             13                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                263                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst           112                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            15                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst           123                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            13                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               263                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        35269                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        35269                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        61102                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        58240                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total       119342                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        10859                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11400                       # number of SCUpgradeReq MSHR misses
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+system.l2c.overall_mshr_miss_latency::cpu1.data  30842571500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  25588917422                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 176919924319                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   5897666000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2585611500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2374540500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     10279000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3324582500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  11818139000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2810539000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3145380500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5955919500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3555600500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  11838086000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2488343500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3486351500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5974695000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   5897666000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5396150500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4862884000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     10279000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6469963000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  17774058500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   7041952000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  17812781000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.283558                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.311704                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.296629                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.222890                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.219180                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.220975                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.735273                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.389634                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.622169                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.103583                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.142888                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.085730                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.143630                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.124332                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.165497                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.068977                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.127885                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.152296                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.103583                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.142888                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.085730                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.435394                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.124332                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.165497                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.068977                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.214194                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.250397                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.103583                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.142888                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.085730                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.435394                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.313127                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.124332                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.165497                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.068977                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.214194                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.262921                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.250397                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73405.101388                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73447.407332                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73425.747080                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76522.838199                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.421053                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76500.089851                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129078.519295                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124079.362956                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 128054.050765                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122985.737708                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126097.370539                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123319.428715                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 126467.494956                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 136875.285945                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122985.737708                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 128580.058033                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123319.428715                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125035.044479                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 132299.122166                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122985.737708                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 128580.058033                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123319.428715                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125035.044479                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 132299.122166                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.288614                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.324686                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.304693                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.227474                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.229212                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.228302                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.743754                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.439009                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.643834                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.183654                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.236874                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.086306                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.163993                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.358056                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.206713                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.238525                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.086452                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.167515                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.349357                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.186681                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.183654                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.236874                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.086306                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.439253                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.358056                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.206713                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.238525                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.086452                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.257899                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.349357                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.279962                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.183654                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.236874                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.086306                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.439253                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.358056                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.206713                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.238525                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.086452                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.257899                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.349357                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.279962                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73377.861964                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73523.799428                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73447.182525                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76403.760331                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76486.574158                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76443.378740                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129454.408093                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 125228.249202                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 128509.558709                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 123891.442866                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127658.044796                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123667.132539                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128778.627801                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140016.532293                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123891.442866                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129102.163083                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123667.132539                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 126766.617208                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 134616.848813                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123891.442866                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129102.163083                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123667.132539                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 126766.617208                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 134616.848813                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154383.299498                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153344.559251                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159070.933014                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131241.202012                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153993.698975                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162871.815452                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158558.142321                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156682.699511                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130693.494077                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151451.217285                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161054.718899                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156910.864827                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154180.133718                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152369.857434                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160896.324480                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 139282.030687                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 158817.140280                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 138452.781060                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               90049                       # Transaction distribution
-system.membus.trans_dist::ReadResp             640443                       # Transaction distribution
-system.membus.trans_dist::WriteReq              37563                       # Transaction distribution
-system.membus.trans_dist::WriteResp             37563                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       930050                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           190296                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           413026                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         280293                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          150977                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            593740                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           574320                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        550394                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        106981                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       106981                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122912                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               90579                       # Transaction distribution
+system.membus.trans_dist::ReadResp             797028                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38077                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38077                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1072761                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           234796                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           432847                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         303767                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          155875                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            628014                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           607752                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        706453                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106976                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106976                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122988                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           52                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        22290                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4211327                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4356581                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       343179                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       343179                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4699760                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155927                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        24302                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4826718                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4974060                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342886                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342886                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5316946                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156003                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         1324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        44580                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    127415488                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    127617319                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7277312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7277312                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               134894631                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           564682                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3194785                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        48604                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    148677184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    148883115                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7268800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7268800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               156151915                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           604039                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3616779                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3194785    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3616779    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3194785                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           109901497                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3616779                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           110163500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               33984                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            18632000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            20375999                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          6680198838                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7677665405                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6549107858                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7558802547                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          229362666                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          229140974                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3176,52 +3171,52 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     11369480                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      6166084                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1983565                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          99756                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        89163                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        10593                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              90051                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4379282                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             37563                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            37563                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      3408225                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1479469                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          686639                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        358765                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1045403                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          133                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1072017                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1072017                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4296486                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       106981                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8273345                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7109938                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              15383283                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    249443752                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    200422911                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              449866663                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2689125                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          7811601                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.375584                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.487066                       # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests     11857284                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6410159                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      2032721                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         132920                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       118959                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        13961                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              90581                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4604579                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38077                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38077                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      3658344                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1620073                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          706187                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        382180                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1088365                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          111                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          111                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1100091                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1100091                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4521240                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106976                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8903542                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7167245                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              16070787                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    267379155                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    202223448                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              469602603                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2985982                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          8314965                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.369241                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.486066                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4888281     62.58%     62.58% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                2912727     37.29%     99.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  10593      0.14%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                5258700     63.24%     63.24% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                3042304     36.59%     99.83% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  13961      0.17%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            7811601                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         8585712934                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8314965                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8970776631                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2584443                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2598924                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4648327252                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        5002984602                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4065319209                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4113788553                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
index e3cbb408a..d57761389 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
@@ -107,60 +107,60 @@
 [    2.145678] pci_bus 0000:00: bus scan returning with max=00

 [    2.145690] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc

 [    2.145712] pci 0000:00:00.0: fixup irq: got 33

-[    2.145721] pci 0000:00:00.0: assigning IRQ 33

+[    2.145720] pci 0000:00:00.0: assigning IRQ 33

 [    2.145731] pci 0000:00:01.0: fixup irq: got 34

 [    2.145740] pci 0000:00:01.0: assigning IRQ 34

 [    2.145752] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

 [    2.145765] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]

-[    2.145779] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

-[    2.145792] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

+[    2.145778] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

+[    2.145791] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

 [    2.145803] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]

-[    2.145815] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]

+[    2.145814] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]

 [    2.145826] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

 [    2.145838] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

-[    2.146510] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

-[    2.146790] ata_piix 0000:00:01.0: version 2.13

-[    2.146802] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

-[    2.146834] ata_piix 0000:00:01.0: enabling bus mastering

-[    2.147106] scsi0 : ata_piix

-[    2.147190] scsi1 : ata_piix

-[    2.147234] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

-[    2.147247] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

-[    2.147374] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

+[    2.146509] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

+[    2.146789] ata_piix 0000:00:01.0: version 2.13

+[    2.146800] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

+[    2.146833] ata_piix 0000:00:01.0: enabling bus mastering

+[    2.147105] scsi0 : ata_piix

+[    2.147189] scsi1 : ata_piix

+[    2.147233] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

+[    2.147246] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

+[    2.147373] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

 [    2.147386] e1000: Copyright (c) 1999-2006 Intel Corporation.

 [    2.147401] e1000 0000:00:00.0: enabling device (0000 -> 0002)

-[    2.147413] e1000 0000:00:00.0: enabling bus mastering

-[    2.290900] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66

-[    2.290911] ata1.00: 2096640 sectors, multi 0: LBA 

-[    2.290940] ata1.00: configured for UDMA/33

+[    2.147412] e1000 0000:00:00.0: enabling bus mastering

+[    2.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66

+[    2.290910] ata1.00: 2096640 sectors, multi 0: LBA 

+[    2.290939] ata1.00: configured for UDMA/33

 [    2.291006] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5

-[    2.291133] sd 0:0:0:0: Attached scsi generic sg0 type 0

+[    2.291132] sd 0:0:0:0: Attached scsi generic sg0 type 0

 [    2.291158] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)

 [    2.291199] sd 0:0:0:0: [sda] Write Protect is off

 [    2.291208] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00

 [    2.291229] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA

 [    2.291366]  sda: sda1

 [    2.291489] sd 0:0:0:0: [sda] Attached SCSI disk

-[    2.411160] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01

-[    2.411174] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection

+[    2.411161] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01

+[    2.411175] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection

 [    2.411196] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k

-[    2.411206] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.

+[    2.411207] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.

 [    2.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k

 [    2.411241] igb: Copyright (c) 2007-2014 Intel Corporation.

 [    2.411314] usbcore: registered new interface driver usb-storage

-[    2.411381] mousedev: PS/2 mouse device common for all mice

+[    2.411382] mousedev: PS/2 mouse device common for all mice

 [    2.411554] usbcore: registered new interface driver usbhid

 [    2.411564] usbhid: USB HID core driver

-[    2.411598] TCP: cubic registered

+[    2.411599] TCP: cubic registered

 [    2.411606] NET: Registered protocol family 17

 
-[    2.412103] devtmpfs: mounted

+[    2.412104] devtmpfs: mounted

 [    2.412177] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)

 
 
-[    2.450715] udevd[609]: starting version 182

+[    2.450669] udevd[609]: starting version 182

 Starting Bootlog daemon: bootlogd.


-[    2.523621] random: dd urandom read with 17 bits of entropy available

+[    2.523747] random: dd urandom read with 17 bits of entropy available

 Populating dev cache


 net.ipv4.conf.default.rp_filter = 1


 net.ipv4.conf.all.rp_filter = 1


@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory


 
INIT: Entering runlevel: 5



 Configuring network interfaces... udhcpc (v1.21.1) started


-[    2.651084] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

+[    2.651088] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

 Sending discover...


 Sending discover...


 Sending discover...


diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
index e682def54..06d6a4eac 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -845,10 +845,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -875,7 +874,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1002,12 +1001,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -1100,16 +1096,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1125,7 +1120,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1288,13 +1283,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1304,9 +1299,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1348,7 +1342,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1429,14 +1423,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1453,7 +1446,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1468,7 +1461,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1591,17 +1584,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1653,7 +1648,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1668,7 +1663,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
index 10a7235d6..38e9235d4 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 18:17:11
-gem5 executing on e104799-lin, pid 6674
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 13:24:25
+gem5 executing on e104799-lin, pid 9941
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 51667599599000 because m5_exit instruction encountered
+Exiting @ tick 51667481628000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
index 734594b87..46040b9b9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
@@ -1,138 +1,138 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.667600                       # Number of seconds simulated
-sim_ticks                                51667599599000                       # Number of ticks simulated
-final_tick                               51667599599000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.667482                       # Number of seconds simulated
+sim_ticks                                51667481628000                       # Number of ticks simulated
+final_tick                               51667481628000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 138912                       # Simulator instruction rate (inst/s)
-host_op_rate                                   163218                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7778954181                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 682524                       # Number of bytes of host memory used
-host_seconds                                  6641.97                       # Real time elapsed on the host
-sim_insts                                   922648651                       # Number of instructions simulated
-sim_ops                                    1084091117                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 173876                       # Simulator instruction rate (inst/s)
+host_op_rate                                   204307                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9745015544                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 682548                       # Number of bytes of host memory used
+host_seconds                                  5301.94                       # Real time elapsed on the host
+sim_insts                                   921877826                       # Number of instructions simulated
+sim_ops                                    1083223459                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       355648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       310272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           9988672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          94253512                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        413888                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            105321992                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      9988672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         9988672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     87921472                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       355328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       294720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst          10221184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          93611976                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        405568                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            104888776                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst     10221184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total        10221184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     87378688                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          87942052                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         5557                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         4848                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             156073                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1472724                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6467                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1645669                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1373773                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          87399268                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         5552                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         4605                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             159706                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1462700                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6337                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1638900                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1365292                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1376346                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           6883                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           6005                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               193326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1824229                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8011                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2038453                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          193326                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             193326                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1701675                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1367865                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           6877                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           5704                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               197826                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1811816                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7850                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2030073                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          197826                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             197826                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1691174                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1702073                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1701675                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          6883                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          6005                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              193326                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1824627                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8011                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3740527                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1645669                       # Number of read requests accepted
-system.physmem.writeReqs                      1376346                       # Number of write requests accepted
-system.physmem.readBursts                     1645669                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1376346                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                105266752                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     56064                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  87940608                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 105321992                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               87942052                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      876                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1691572                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1691174                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          6877                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          5704                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              197826                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1812214                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7850                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3721645                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1638900                       # Number of read requests accepted
+system.physmem.writeReqs                      1367865                       # Number of write requests accepted
+system.physmem.readBursts                     1638900                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1367865                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                104832704                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     56896                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  87398080                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 104888776                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               87399268                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      889                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2255                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         378251                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               98784                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              105100                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              100845                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               95977                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              103819                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              113338                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               98145                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               99955                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               93968                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              154563                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              98779                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             100711                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              92945                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              97659                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              91699                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              98506                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               83240                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               87253                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               86416                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               83797                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               90075                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               95693                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               84431                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               87097                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               83064                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               88599                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              84727                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              86277                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              82015                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              84756                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              80845                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              85787                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         381658                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               98450                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              107251                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               99188                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               95203                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               99955                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              109194                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               96838                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               98371                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               94736                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              155242                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              99865                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             104170                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              95009                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              96057                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              92133                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              96349                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               83734                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               87693                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               84639                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               83186                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               87134                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               92701                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               83787                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               85921                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               83051                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               88932                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              85543                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              89009                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              82580                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              83353                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              81127                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              83205                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          17                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51667597819500                       # Total gap between requests
+system.physmem.numWrRetry                          16                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51667479848500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1645654                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1638885                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1373773                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1321004                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    317364                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       977                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       363                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1365292                       # Write request sizes (log2)
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 system.physmem.rdQLenPdf::4                       478                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::6                       512                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20                        4                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -159,161 +159,160 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::57                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       31                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       648118                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      298.103938                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.284544                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.148793                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         253468     39.11%     39.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       156556     24.16%     63.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        60545      9.34%     72.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        34961      5.39%     78.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        26042      4.02%     82.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        18689      2.88%     84.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        14146      2.18%     87.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023        13035      2.01%     89.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        70676     10.90%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         648118                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         79768                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.619672                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      282.463170                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          79765    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    14965                       # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples       647624                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      296.824083                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     173.411154                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.640423                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         254912     39.36%     39.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       156143     24.11%     63.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        60053      9.27%     72.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        34984      5.40%     78.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        25631      3.96%     82.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        18733      2.89%     85.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        14068      2.17%     87.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        12825      1.98%     89.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        70275     10.85%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         647624                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         79231                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.673638                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      283.409553                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          79228    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           79768                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         79768                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.225855                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.793439                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.200790                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           77436     97.08%     97.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             326      0.41%     97.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              71      0.09%     97.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             315      0.39%     97.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              43      0.05%     98.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             360      0.45%     98.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             211      0.26%     98.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              25      0.03%     98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              65      0.08%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             125      0.16%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              20      0.03%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              34      0.04%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             501      0.63%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              33      0.04%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              30      0.04%     99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             120      0.15%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               8      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               3      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             4      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            23      0.03%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             4      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           79768                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    26467861730                       # Total ticks spent queuing
-system.physmem.totMemAccLat               57307730480                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8223965000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       16091.91                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           79231                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         79231                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.235615                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.796201                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.303380                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           76926     97.09%     97.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             319      0.40%     97.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              70      0.09%     97.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             321      0.41%     97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              45      0.06%     98.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             342      0.43%     98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             202      0.25%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              22      0.03%     98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              52      0.07%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             126      0.16%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              31      0.04%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              49      0.06%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             483      0.61%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              36      0.05%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              14      0.02%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             128      0.16%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              11      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             4      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             2      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            28      0.04%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           79231                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    26417109815                       # Total ticks spent queuing
+system.physmem.totMemAccLat               57129816065                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8190055000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       16127.55                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34841.91                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.04                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.70                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.04                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.70                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  34877.55                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.03                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.69                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.03                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.69                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.70                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1338706                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                   1032034                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.39                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.11                       # Row buffer hit rate for writes
-system.physmem.avgGap                     17097068.62                       # Average gap between requests
-system.physmem.pageHitRate                      78.53                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2524404960                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1377403500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6364503600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4523001120                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3374676002880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1325410671600                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29837914926750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34552790914410                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.751704                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49637080843701                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1725294480000                       # Time in different power states
+system.physmem.avgWrQLen                        25.24                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1331553                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                   1024428                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.29                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.02                       # Row buffer hit rate for writes
+system.physmem.avgGap                     17183743.94                       # Average gap between requests
+system.physmem.pageHitRate                      78.44                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2488253040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1357677750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6274663200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4463391600                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3374668374480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1321909933950                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29840915681250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34552077975270                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.739417                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49642099754241                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1725290580000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    305218373299                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    300090521259                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2375306640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1296050250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6464827200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4380881760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3374676002880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1318079999925                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29844345348750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34551618417405                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.729010                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49647781129555                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1725294480000                       # Time in different power states
+system.physmem_1.actEnergy                 2407784400                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1313771250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6501775800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4385664000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3374668374480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1318271769585                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29844107045250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34551656184765                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.731253                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49647373564820                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1725290580000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    294523106445                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    294812186430                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          704                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -337,15 +336,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               252640803                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         176566458                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          11942340                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            185523828                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               131623059                       # Number of BTB hits
+system.cpu.branchPred.lookups               252485837                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         176433570                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          11949823                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            185211535                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               131480802                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.946714                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30927608                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2129490                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             70.989532                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                30949299                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2133828                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -376,63 +375,63 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    561342                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                561342                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        20890                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       179371                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples       561342                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0          561342    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       561342                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       200261                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 26959.987217                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 22796.816332                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20928.483641                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       197960     98.85%     98.85% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071            3      0.00%     98.85% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         1973      0.99%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks                    560555                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                560555                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        20820                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       178520                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples       560555                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          560555    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       560555                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       199340                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 27109.310725                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 22940.792106                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20958.396260                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       197062     98.86%     98.86% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071            8      0.00%     98.86% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         1944      0.98%     99.84% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::196608-262143           53      0.03%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          114      0.06%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           41      0.02%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           90      0.04%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          116      0.06%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           50      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           75      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           14      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::655360-720895            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       200261                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       199340                       # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walksPending::samples  -1569959592                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0     -1569959592    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::total  -1569959592                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        179372     89.57%     89.57% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         20890     10.43%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       200262                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       561342                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K        178521     89.56%     89.56% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         20820     10.44%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       199341                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       560555                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       561342                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       200262                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       560555                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       199341                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       200262                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       761604                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       199341                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       759896                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    178417728                       # DTB read hits
-system.cpu.dtb.read_misses                     463663                       # DTB read misses
-system.cpu.dtb.write_hits                   158017805                       # DTB write hits
-system.cpu.dtb.write_misses                     97679                       # DTB write misses
+system.cpu.dtb.read_hits                    178230117                       # DTB read hits
+system.cpu.dtb.read_misses                     462749                       # DTB read misses
+system.cpu.dtb.write_hits                   157902959                       # DTB write hits
+system.cpu.dtb.write_misses                     97806                       # DTB write misses
 system.cpu.dtb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               45304                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_mva_asid               45299                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                    1089                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    77601                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      1384                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                  14410                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                    78363                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      1414                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                  14783                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     23069                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                178881391                       # DTB read accesses
-system.cpu.dtb.write_accesses               158115484                       # DTB write accesses
+system.cpu.dtb.perms_faults                     23068                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                178692866                       # DTB read accesses
+system.cpu.dtb.write_accesses               158000765                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         336435533                       # DTB hits
-system.cpu.dtb.misses                          561342                       # DTB misses
-system.cpu.dtb.accesses                     336996875                       # DTB accesses
+system.cpu.dtb.hits                         336133076                       # DTB hits
+system.cpu.dtb.misses                          560555                       # DTB misses
+system.cpu.dtb.accesses                     336693631                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -462,190 +461,184 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    135051                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                135051                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1071                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       117673                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       135051                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          135051    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       135051                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       118744                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 30328.088156                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 25835.192345                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 23534.472369                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-32767        58823     49.54%     49.54% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::32768-65535        57227     48.19%     97.73% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-98303            2      0.00%     97.73% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::98304-131071            5      0.00%     97.74% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-163839         2006      1.69%     99.43% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::163840-196607          464      0.39%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-229375           29      0.02%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::229376-262143           32      0.03%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-294911           88      0.07%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::294912-327679           29      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-360447           14      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::360448-393215           13      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-425983            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::425984-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       118744                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks                    134868                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                134868                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1077                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       117569                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       134868                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          134868    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       134868                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       118646                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 30429.546719                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 26050.717125                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 23099.528150                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       116148     97.89%     97.89% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071            8      0.01%     97.90% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607         2266      1.91%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143           70      0.06%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679          116      0.10%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           20      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       118646                       # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walksPending::samples  -1570990092                       # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::0     -1570990092    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::total  -1570990092                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        117673     99.10%     99.10% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1071      0.90%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       118744                       # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K        117569     99.09%     99.09% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1077      0.91%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       118646                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       135051                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       135051                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       134868                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       134868                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       118744                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       118744                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       253795                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    439141642                       # ITB inst hits
-system.cpu.itb.inst_misses                     135051                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       118646                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       118646                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       253514                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    438855637                       # ITB inst hits
+system.cpu.itb.inst_misses                     134868                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           11                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               45304                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_mva_asid               45299                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                    1089                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    55572                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                    56516                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    356769                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    359281                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                439276693                       # ITB inst accesses
-system.cpu.itb.hits                         439141642                       # DTB hits
-system.cpu.itb.misses                          135051                       # DTB misses
-system.cpu.itb.accesses                     439276693                       # DTB accesses
-system.cpu.numCycles                       2565959423                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                438990505                       # ITB inst accesses
+system.cpu.itb.hits                         438855637                       # DTB hits
+system.cpu.itb.misses                          134868                       # DTB misses
+system.cpu.itb.accesses                     438990505                       # DTB accesses
+system.cpu.numCycles                       2563496972                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   922648651                       # Number of instructions committed
-system.cpu.committedOps                    1084091117                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      92858708                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends                      7622                       # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles                 100770378430                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi                               2.781080                       # CPI: cycles per instruction
-system.cpu.ipc                               0.359573                       # IPC: instructions per cycle
+system.cpu.committedInsts                   921877826                       # Number of instructions committed
+system.cpu.committedOps                    1083223459                       # Number of ops (including micro ops) committed
+system.cpu.discardedOps                      92885181                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.numFetchSuspends                      7623                       # Number of times Execute suspended instruction fetching
+system.cpu.quiesceCycles                 100772604966                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi                               2.780734                       # CPI: cycles per instruction
+system.cpu.ipc                               0.359617                       # IPC: instructions per cycle
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16482                       # number of quiesce instructions executed
-system.cpu.tickCycles                      1742118066                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       823841357                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements          10735802                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.930082                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           320587267                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          10736314                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.860087                       # Average number of references to valid blocks.
+system.cpu.kern.inst.quiesce                    16483                       # number of quiesce instructions executed
+system.cpu.tickCycles                      1740911334                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       822585638                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements          10734176                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.930080                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           320289523                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          10734688                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.836873                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        7087675500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.930082                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.930080                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999863                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999863                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          392                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          385                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1346721008                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1346721008                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    164117651                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       164117651                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    147554232                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      147554232                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       511700                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        511700                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       336216                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       336216                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3856271                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3856271                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      4163172                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      4163172                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     311671883                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        311671883                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    312183583                       # number of overall hits
-system.cpu.dcache.overall_hits::total       312183583                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      6375380                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       6375380                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      4133213                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4133213                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1400858                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1400858                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1238861                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1238861                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       308609                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       308609                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1345515853                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1345515853                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    163941297                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       163941297                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    147439641                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      147439641                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       511618                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        511618                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       335027                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       335027                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3852667                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3852667                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      4161339                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      4161339                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     311380938                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        311380938                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    311892556                       # number of overall hits
+system.cpu.dcache.overall_hits::total       311892556                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      6369353                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       6369353                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      4134165                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4134165                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1400138                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1400138                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1239654                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1239654                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       310380                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       310380                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     10508593                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       10508593                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     11909451                       # number of overall misses
-system.cpu.dcache.overall_misses::total      11909451                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 117756219000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 117756219000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 201470838000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 201470838000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  84198421500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  84198421500                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5139608000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   5139608000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     10503518                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       10503518                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     11903656                       # number of overall misses
+system.cpu.dcache.overall_misses::total      11903656                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 117431334000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 117431334000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 199634806500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 199634806500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  84591152000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  84591152000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   5133902500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   5133902500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 319227057000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 319227057000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 319227057000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 319227057000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    170493031                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    170493031                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    151687445                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    151687445                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1912558                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1912558                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1575077                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1575077                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4164880                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      4164880                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      4163173                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      4163173                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    322180476                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    322180476                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    324093034                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    324093034                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037394                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.037394                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027248                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.027248                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.732453                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.732453                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786540                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.786540                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.074098                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.074098                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 317066140500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 317066140500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 317066140500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 317066140500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    170310650                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    170310650                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    151573806                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    151573806                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1911756                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1911756                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1574681                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1574681                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      4163047                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      4163047                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      4161340                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      4161340                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    321884456                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    321884456                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    323796212                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    323796212                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.037398                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.037398                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027275                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.027275                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.732383                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.732383                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.787241                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.787241                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.074556                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.074556                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032617                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032617                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036747                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036747                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18470.462780                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 18470.462780                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48744.363767                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48744.363767                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 67964.381395                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 67964.381395                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16654.109245                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16654.109245                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032631                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032631                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036763                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036763                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18436.932919                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 18436.932919                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48289.027288                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48289.027288                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68237.711490                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68237.711490                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16540.700110                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16540.700110                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30377.716313                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30377.716313                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26804.514918                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26804.514918                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30186.661317                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30186.661317                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26636.030183                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26636.030183                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -654,155 +647,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      8239619                       # number of writebacks
-system.cpu.dcache.writebacks::total           8239619                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       773301                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       773301                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1821450                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1821450                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data          142                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total          142                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70152                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        70152                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2594751                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2594751                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2594751                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2594751                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5602079                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5602079                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2311763                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2311763                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1393294                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1393294                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1238719                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1238719                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       238457                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       238457                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      8245378                       # number of writebacks
+system.cpu.dcache.writebacks::total           8245378                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       770684                       # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteLineReq_mshr_hits::total          152                       # number of WriteLineReq MSHR hits
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+system.cpu.dcache.LoadLockedReq_mshr_hits::total        69756                       # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total      2593629                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2593629                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2593629                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5598669                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5598669                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2311220                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2311220                       # number of WriteReq MSHR misses
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+system.cpu.dcache.SoftPFReq_mshr_misses::total      1392587                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1239502                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1239502                       # number of WriteLineReq MSHR misses
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+system.cpu.dcache.LoadLockedReq_mshr_misses::total       240624                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7913842                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7913842                       # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total      9307136                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7909889                       # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total      9302476                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33706                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33706                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67403                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  96321163500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  96321163500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106904157500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 106904157500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  26939627500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  26939627500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  82952613500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  82952613500                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3468831500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3468831500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  96111391500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  96111391500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105871130000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 105871130000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  26586103000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  26586103000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  83345106500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  83345106500                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3481164500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3481164500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        81000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203225321000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 203225321000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230164948500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 230164948500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6198462000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6198462000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6207588500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6207588500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12406050500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12406050500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032858                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032858                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015240                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015240                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.728498                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.728498                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786450                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786450                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057254                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057254                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 201982521500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 201982521500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228568624500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 228568624500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6197557500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6197557500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6207394000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6207394000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12404951500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12404951500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032873                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032873                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015248                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015248                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.728433                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.728433                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787145                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787145                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.057800                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.057800                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024563                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.024563                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028717                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028717                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17193.824560                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17193.824560                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46243.562813                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46243.562813                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19335.206712                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19335.206712                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 66966.449614                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 66966.449614                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14546.989604                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14546.989604                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024574                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024574                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028729                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028729                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17166.828669                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17166.828669                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45807.465321                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45807.465321                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19091.161270                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19091.161270                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67240.800338                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67240.800338                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14467.237266                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14467.237266                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25679.729391                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25679.729391                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24729.943615                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24729.943615                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183946.998249                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183946.998249                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.649499                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.649499                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184057.838672                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184057.838672                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25535.443228                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25535.443228                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24570.729825                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24570.729825                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183920.156097                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183920.156097                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184162.879013                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184162.879013                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184041.533760                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184041.533760                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          24189642                       # number of replacements
+system.cpu.icache.tags.replacements          24166189                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.872408                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           414582353                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          24190154                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             17.138475                       # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs           414317362                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          24166701                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             17.144142                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       39504620500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.872408                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999751                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999751                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          133                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          104                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         462962680                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        462962680                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    414582353                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       414582353                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     414582353                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        414582353                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    414582353                       # number of overall hits
-system.cpu.icache.overall_hits::total       414582353                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     24190164                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      24190164                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     24190164                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       24190164                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     24190164                       # number of overall misses
-system.cpu.icache.overall_misses::total      24190164                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 327340789000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 327340789000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 327340789000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 327340789000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 327340789000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 327340789000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    438772517                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    438772517                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    438772517                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    438772517                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total    438772517                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.055131                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.055131                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.055131                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.055131                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.055131                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.055131                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13531.978907                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13531.978907                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13531.978907                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13531.978907                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13531.978907                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13531.978907                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         462650783                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        462650783                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    414317362                       # number of ReadReq hits
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+system.cpu.icache.overall_misses::total      24166711                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 327482385000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 327482385000                       # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total 327482385000                       # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total 327482385000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    438484073                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    438484073                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total    438484073                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    438484073                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    438484073                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.055114                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.055114                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.055114                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.055114                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.055114                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.055114                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13550.970382                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13550.970382                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13550.970382                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13550.970382                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13550.970382                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13550.970382                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -811,230 +804,231 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks     24189642                       # number of writebacks
-system.cpu.icache.writebacks::total          24189642                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24190164                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     24190164                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     24190164                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     24190164                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst     24190164                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total     24190164                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     24166189                       # number of writebacks
+system.cpu.icache.writebacks::total          24166189                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst     24166711                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total     24166711                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst     24166711                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total     24166711                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst     24166711                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total     24166711                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        52309                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        52309                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303150626000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 303150626000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303150626000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 303150626000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303150626000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 303150626000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303315675000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 303315675000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303315675000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 303315675000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303315675000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 303315675000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   6746864000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   6746864000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   6746864000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   6746864000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.055131                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.055131                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.055131                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.055131                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.055131                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.055131                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12531.978948                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12531.978948                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12531.978948                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12531.978948                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12531.978948                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12531.978948                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.055114                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.055114                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.055114                       # mshr miss rate for demand accesses
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+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.055114                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.055114                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12550.970424                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12550.970424                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12550.970424                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12550.970424                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12550.970424                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12550.970424                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1495284                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65229.781494                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           65922487                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1558468                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            42.299545                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1490419                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65266.902030                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           65881939                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1553674                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            42.403966                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      36600562500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36948.253650                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   327.788805                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   379.909026                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  7890.502586                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19683.327428                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563786                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.005002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.005797                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.120400                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.300344                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995327                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          237                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        62947                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          237                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 36961.112074                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   325.532890                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   387.132710                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7869.830371                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19723.293986                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.563982                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004967                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.005907                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.120084                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.300954                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.995894                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          269                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62986                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          268                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          502                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2422                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5485                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54486                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003616                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.960495                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        573928107                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       573928107                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       915811                       # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_hits::total        1195114                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      8239619                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      8239619                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     24185917                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     24185917                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data        10440                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total        10440                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1637843                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1637843                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     24086368                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     24086368                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6914406                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6914406                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       709945                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       709945                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       915811                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       279303                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.dtb.walker       915811                       # number of overall hits
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-system.cpu.l2cache.overall_hits::cpu.data      8552249                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       33833731                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         5557                       # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_misses::total        10405                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        37520                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        37520                       # number of UpgradeReq misses
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+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004105                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.961090                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        573572775                       # Number of tag accesses
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+system.cpu.l2cache.WritebackDirty_hits::total      8245378                       # number of WritebackDirty hits
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+system.cpu.l2cache.UpgradeReq_hits::cpu.data        10423                       # number of UpgradeReq hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
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-system.cpu.l2cache.InvalidateReq_misses::total       528774                       # number of InvalidateReq misses
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        79500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total        79500                       # number of SCUpgradeReq miss cycles
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-system.cpu.l2cache.WritebackDirty_accesses::total      8239619                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu.l2cache.WritebackDirty_accesses::writebacks      8245378                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      8245378                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     24162502                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     24162502                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        47869                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        47869                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2264033                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2264033                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24190161                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     24190161                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7233600                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7233600                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1238719                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1238719                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       921368                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       284151                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     24190161                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9497633                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     34893313                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       921368                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       284151                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     24190161                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9497633                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     34893313                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006031                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.017061                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.008631                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782319                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782319                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2263598                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2263598                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     24166708                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     24166708                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7231633                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7231633                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1239502                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1239502                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       924925                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       287189                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     24166708                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9495231                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     34874053                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       924925                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       287189                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     24166708                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9495231                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     34874053                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006003                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.016035                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.008380                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.782260                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.782260                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.276582                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.276582                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004291                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004291                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.044127                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.044127                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.426872                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.426872                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006031                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.017061                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004291                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.099539                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.030366                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006031                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.017061                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004291                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.099539                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.030366                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137340.651431                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136758.663366                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 137069.485824                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39528.331557                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39528.331557                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.272982                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.272982                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.004445                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.004445                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.043501                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.043501                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.428896                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.428896                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006003                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.016035                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.004445                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.098207                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.030111                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006003                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.016035                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.004445                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.098207                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.030111                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136824.117435                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137369.163952                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 137071.231663                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39755.701544                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39755.701544                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132659.882783                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132659.882783                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132259.270856                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132259.270856                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134610.448505                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134610.448505                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138758.307897                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138758.307897                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137340.651431                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136758.663366                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132259.270856                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133318.460541                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 133251.540702                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137340.651431                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136758.663366                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132259.270856                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133318.460541                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 133251.540702                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132642.376614                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132642.376614                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132292.801556                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132292.801556                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134753.083476                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134753.083476                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138793.573193                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138793.573193                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136824.117435                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137369.163952                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132292.801556                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133354.425357                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 133281.769839                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136824.117435                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137369.163952                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132292.801556                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133354.425357                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 133281.769839                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1043,45 +1037,45 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1267142                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1267142                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1258661                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1258661                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           21                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           22                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           25                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         5557                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4848                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        10405                       # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           25                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         5552                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         4605                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        10157                       # number of ReadReq MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        37520                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        37520                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        37446                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        37446                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       626190                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       626190                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       103790                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total       103790                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       319173                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       319173                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       528774                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       528774                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         5557                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4848                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       103790                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       945363                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1059558                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         5557                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4848                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       103790                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       945363                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1059558                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       617921                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       617921                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst       107423                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total       107423                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       314558                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       314558                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       531617                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       531617                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         5552                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         4605                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst       107423                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       932479                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1050059                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         5552                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         4605                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst       107423                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       932479                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1050059                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        52309                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33697                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        86006                       # number of ReadReq MSHR uncacheable
@@ -1090,162 +1084,163 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33706
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        52309                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67403                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total       119712                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    707632000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    614526000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1322158000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2655683000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2655683000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    704127500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    586535000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1290662500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2650319500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2650319500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        69500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        69500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  76808392000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  76808392000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  12689415000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  12689415000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  39772846000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  39772846000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  68084045500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  68084045500                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    707632000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    614526000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  12689415000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116581238000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 130592811000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    707632000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    614526000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  12689415000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116581238000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 130592811000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  75783300000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  75783300000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  13137194000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  13137194000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  39242637500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  39242637500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  68468853000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  68468853000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    704127500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    586535000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  13137194000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115025937500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 129453794000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    704127500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    586535000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  13137194000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115025937500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 129453794000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5936074000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5777189500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  11713263500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5819359500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5819359500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5776284500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  11712358500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5819171500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5819171500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   5936074000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11596549000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  17532623000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006031                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.017061                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008631                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11595456000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  17531530000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006003                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.016035                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008380                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782319                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782319                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.782260                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.782260                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.276582                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.276582                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004291                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004291                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.044124                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.044124                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.426872                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.426872                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006031                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.017061                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004291                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.099537                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.030366                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006031                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.017061                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004291                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.099537                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.030366                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126758.663366                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127069.485824                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70780.463753                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70780.463753                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.272982                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.272982                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.004445                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.004445                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.043498                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.043498                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.428896                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.428896                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006003                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.016035                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.004445                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.098205                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030110                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006003                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.016035                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.004445                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.098205                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030110                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127369.163952                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127071.231663                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70777.105699                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70777.105699                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122659.882783                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122659.882783                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122260.477888                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122260.477888                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124612.188374                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124612.188374                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128758.307897                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128758.307897                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126758.663366                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122260.477888                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123319.019255                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123252.158919                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126758.663366                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122260.477888                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123319.019255                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123252.158919                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122642.376614                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122642.376614                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122294.052484                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122294.052484                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124754.854431                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124754.854431                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128793.573193                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128793.573193                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127369.163952                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122294.052484                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123354.989764                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123282.400322                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127369.163952                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122294.052484                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123354.989764                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123282.400322                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171445.217675                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136191.236658                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.551831                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.551831                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171418.360685                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136180.714136                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172644.974189                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172644.974189                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172047.965224                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146456.687717                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.749329                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.557471                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     70595106                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     35668602                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4412                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2257                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2257                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     70542716                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     35641283                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4403                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2298                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2298                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq        1731880                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      33156424                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1728705                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      33127830                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33706                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33706                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      9613409                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     24185917                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2732498                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        47963                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      9610686                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     24162502                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2728698                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        47872                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        47964                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2264033                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2264033                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     24190164                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7242479                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1345383                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1238719                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     72670859                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32439334                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       687653                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2163740                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total         107961586                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3099416704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1135424530                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2273208                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7370944                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         4244485386                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2167477                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     38466398                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.018246                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.133841                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        47873                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2263598                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2263598                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     24166711                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7240510                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1346166                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1239502                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     72600538                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32434260                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       690132                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2164681                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total         107889611                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   3096417152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1135639442                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2297512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      7399400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         4241753506                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     2152838                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     38433190                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.018207                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.133699                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           37764532     98.18%     98.18% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             701866      1.82%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           37733441     98.18%     98.18% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             699749      1.82%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       38466398                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    68278869995                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       38433190                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    68234466996                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1476392                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1477892                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   36370852681                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   36335720582                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14941078957                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14937837927                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     403557888                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     402991902                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1242412419                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1239794423                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40327                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40327                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40325                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40325                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1255,18 +1250,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231012                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231012                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231008                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231008                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353796                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353792                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1276,24 +1269,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334480                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334480                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334464                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334464                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492400                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             42171500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492384                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             42167500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               332500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               10500                       # Layer occupancy (ticks)
@@ -1306,79 +1298,73 @@ system.iobus.reqLayer16.occupancy               16000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25807000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25751500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              170000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            34145500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            34147000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           565709151                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              120500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565729644                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               42000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147772000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147768000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115488                       # number of replacements
-system.iocache.tags.tagsinuse               10.440019                       # Cycle average of tags in use
+system.iocache.tags.replacements               115486                       # number of replacements
+system.iocache.tags.tagsinuse               10.440009                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115504                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115502                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13160148501000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.520841                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.919178                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         13160148730000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.520855                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.919154                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.220053                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.432449                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.432447                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.652501                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039911                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039911                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039893                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039893                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8842                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8879                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8840                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8877                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8842                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8882                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8840                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8880                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8842                       # number of overall misses
-system.iocache.overall_misses::total             8882                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5086500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1658170108                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1663256608                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8840                       # number of overall misses
+system.iocache.overall_misses::total             8880                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1638496114                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1643565614                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13863609036                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13863609036                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5437500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1658170108                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1663607608                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5437500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1658170108                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1663607608                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13864020537                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13864020537                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1638496114                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1643916614                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1638496114                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1643916614                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8842                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8879                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8840                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8877                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8842                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8882                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8840                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8880                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8842                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8882                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8840                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8880                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1392,55 +1378,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 187533.375707                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 187324.767204                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 185350.239140                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 185148.768052                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129974.584077                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129974.584077                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 187533.375707                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 187301.014186                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 187533.375707                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 187301.014186                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34622                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129978.441995                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129978.441995                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 185350.239140                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 185125.744820                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 185350.239140                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 185125.744820                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         33657                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                 3502                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.886351                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.610794                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8842                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8879                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8840                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8877                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8842                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8882                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8840                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8880                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8842                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8882                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1216070108                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1219306608                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8840                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8880                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1196496114                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1199715614                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8530409036                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8530409036                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3437500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1216070108                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1219507608                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3437500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1216070108                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1219507608                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8530820537                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8530820537                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1196496114                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1199916614                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1196496114                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1199916614                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1454,73 +1440,73 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137533.375707                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 137324.767204                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135350.239140                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 135148.768052                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79974.584077                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79974.584077                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 137533.375707                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 137301.014186                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 137533.375707                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 137301.014186                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79978.441995                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.441995                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 135350.239140                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 135125.744820                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 135350.239140                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 135125.744820                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               86006                       # Transaction distribution
-system.membus.trans_dist::ReadResp             528253                       # Transaction distribution
+system.membus.trans_dist::ReadResp             527021                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33706                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33706                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1373773                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           233285                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            38308                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1365292                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           236782                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            38218                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           38309                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1154179                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1154179                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        442247                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           38219                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1148769                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1148769                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        441015                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           32                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6916                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4854992                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4984644                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341559                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       341559                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5326203                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4836672                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4966324                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341304                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341304                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5307628                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          740                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13832                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    186025772                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    186196178                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7238272                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7238272                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               193434450                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3077                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3470793                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    185058092                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    185228498                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7229952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7229952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               192458450                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3204                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3459197                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3470793    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3459197    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3470793                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           102553500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3459197                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           102492500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               19828                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5511000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5497000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9297161713                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9250665962                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         8798501817                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         8763516637                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          227863618                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227782427                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal
index 8e58c5e11..9a18d3243 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal
@@ -104,10 +104,10 @@
 [    3.139989] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]

 [    3.140001] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]

 [    3.140044] pci_bus 0000:00: fixups for bus

-[    3.140053] pci_bus 0000:00: bus scan returning with max=00

+[    3.140052] pci_bus 0000:00: bus scan returning with max=00

 [    3.140066] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc

-[    3.140090] pci 0000:00:00.0: fixup irq: got 33

-[    3.140099] pci 0000:00:00.0: assigning IRQ 33

+[    3.140089] pci 0000:00:00.0: fixup irq: got 33

+[    3.140098] pci 0000:00:00.0: assigning IRQ 33

 [    3.140110] pci 0000:00:01.0: fixup irq: got 34

 [    3.140119] pci 0000:00:01.0: assigning IRQ 34

 [    3.140132] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

@@ -144,15 +144,15 @@
 [    3.421575] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01

 [    3.421589] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection

 [    3.421613] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k

-[    3.421624] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.

+[    3.421623] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.

 [    3.421648] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k

 [    3.421660] igb: Copyright (c) 2007-2014 Intel Corporation.

 [    3.421747] usbcore: registered new interface driver usb-storage

 [    3.421815] mousedev: PS/2 mouse device common for all mice

-[    3.422010] usbcore: registered new interface driver usbhid

+[    3.422009] usbcore: registered new interface driver usbhid

 [    3.422020] usbhid: USB HID core driver

 [    3.422060] TCP: cubic registered

-[    3.422069] NET: Registered protocol family 17

+[    3.422068] NET: Registered protocol family 17

 
 [    3.422570] devtmpfs: mounted

 [    3.422641] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)

@@ -160,7 +160,7 @@
 
 [    3.464661] udevd[607]: starting version 182

 Starting Bootlog daemon: bootlogd.


-[    3.594841] random: dd urandom read with 20 bits of entropy available

+[    3.594831] random: dd urandom read with 20 bits of entropy available

 Populating dev cache


 net.ipv4.conf.default.rp_filter = 1


 net.ipv4.conf.all.rp_filter = 1


@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory


 
INIT: Entering runlevel: 5



 Configuring network interfaces... udhcpc (v1.21.1) started


-[    3.761487] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

+[    3.761486] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

 Sending discover...


 Sending discover...


 Sending discover...


diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini
index 4597b7097..c5d0f1c68 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -901,10 +901,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -931,7 +930,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1058,12 +1057,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -1156,16 +1152,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1181,7 +1176,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1344,13 +1339,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1360,9 +1355,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1404,7 +1398,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1485,14 +1479,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1509,7 +1502,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1524,7 +1517,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1647,17 +1640,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1709,7 +1704,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1724,7 +1719,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr
index 485d0984f..96daf2d1b 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr
@@ -11,87 +11,93 @@ warn: 12469689449500: Instruction results do not match! (Values may not actually
 warn: 12469692907500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0
 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: 13858044111500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13859619440500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13859918576500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13860513270500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13897357688500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13899290842000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13920553373000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13947589978000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13980155713500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14222638356000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14222638963500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14222639213500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14222639459500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14222639675000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14230786818000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14230787024500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14238614478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14246439816000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14246440056000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14246440571500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14246440805500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14246441035500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14246441242000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14251755692500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14251756202000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14251756436000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14251756666000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14251756872500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14258214284500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14258214514500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14258214721000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14268021442500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14268021672500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14279273428000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14279273680000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14279274189500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14279274423500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14279274653500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14279274860000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14289078760000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14289078990000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14289079196500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14304548850000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14309612929000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14309613159000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14316607744000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14316607974000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14326722373000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14326723356500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14326723586500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14326723793000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14389661684500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14389661933000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14401989619000: Instruction results do not match! (Values may not actually be integers) Inst: 0x48, checker: 0x49
-warn: 14447395786500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14447396035000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14573254812500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14573344689000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14573345167500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14573345456500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14573345979000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14573347046000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14573347537500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14573347856000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14574083032500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14574083293500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
-warn: 14574083498000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14574154242500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
-warn: 14574154452500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14574154723500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
-warn: 14574155294000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14574155549500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
-warn: 14574155773000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14574156062000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14574156571000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14574157634000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14574158132000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14574158434000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14623142882500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
-warn: 14623143173500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14623143425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14623143670000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14623143932500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14623144171500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 13859656146500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13859950489500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13860549714500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13861141715500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13861425606000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13887655302500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13887984972000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13888175197500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13888527468000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13926855654000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13927074222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13927622636000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13927831908000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13928069949000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13928309196000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13944831907000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13960769373500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14182895786500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14182896036500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14182896282500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14191041595500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14198847599000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14198848114500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14198848578500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14206625430000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14206625664000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14206625894000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14211939480000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14211939710000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14218406091500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14218406321500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14228222612500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14228222857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14228223366500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14228223600500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14228223830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14228224037000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14239432062500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14239432572000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14239432806000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14239433036000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14239433242500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14249200202500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14249200432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14264670876000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14264671403500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14264671637500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14264671867500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14264672074000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14269733190000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14276719950000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14276720459500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14276720693500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14276720923500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14276721130000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14286856693000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14349944433000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14349944681500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14349944897000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14407864195500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14407864763000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14407865015500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14407865264000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14407865479500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14533528504500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14533619061000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
+warn: 14533620387500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14533622455000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14533622773500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14534367031000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14534367292000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
+warn: 14534367496500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14534438304500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14534438514500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14534438785500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
+warn: 14534439356000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14534439611500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14534439835000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14534440124000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14534440633000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14534441696000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14534442194000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14534442496000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14583340343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14583519554000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 14583519838000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14583520090000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14583520334500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14583520596500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14583520826000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout
index b51d319da..f9ab0d84b 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 18:31:30
-gem5 executing on e104799-lin, pid 7980
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 14:35:47
+gem5 executing on e104799-lin, pid 16996
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 51331535316000 because m5_exit instruction encountered
+Exiting @ tick 51291805611000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
index 1eec09462..e8c18c866 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.331535                       # Number of seconds simulated
-sim_ticks                                51331535316000                       # Number of ticks simulated
-final_tick                               51331535316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.291806                       # Number of seconds simulated
+sim_ticks                                51291805611000                       # Number of ticks simulated
+final_tick                               51291805611000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  77629                       # Simulator instruction rate (inst/s)
-host_op_rate                                    91214                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4714315459                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 686100                       # Number of bytes of host memory used
-host_seconds                                 10888.44                       # Real time elapsed on the host
-sim_insts                                   845255961                       # Number of instructions simulated
-sim_ops                                     993175006                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 109804                       # Simulator instruction rate (inst/s)
+host_op_rate                                   129027                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6627600062                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 686384                       # Number of bytes of host memory used
+host_seconds                                  7739.12                       # Real time elapsed on the host
+sim_insts                                   849784302                       # Number of instructions simulated
+sim_ops                                     998554740                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       205184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       203136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5579360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          71974536                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        439872                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             78402088                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5579360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5579360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     67218688                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       234176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       229184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5702880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          74235720                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        438720                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             80840680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5702880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5702880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     69030592                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          67239268                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3206                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3174                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             103130                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1124615                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6873                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1240998                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1050292                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          69051172                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3659                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3581                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             105060                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1159946                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6855                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1279101                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1078603                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1052865                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           3997                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           3957                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               108693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1402150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8569                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1527367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          108693                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108693                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1309501                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1081176                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           4566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4468                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               111185                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1447321                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8553                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1576093                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          111185                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             111185                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1345841                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1309902                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1309501                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          3997                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          3957                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              108693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1402551                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8569                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2837269                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1240998                       # Number of read requests accepted
-system.physmem.writeReqs                      1052865                       # Number of write requests accepted
-system.physmem.readBursts                     1240998                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1052865                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 79374080                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     49792                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  67238272                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  78402088                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               67239268                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      778                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         323831                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               73630                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               80699                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               78276                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               74217                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               73666                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               79970                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               75195                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               74032                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               71713                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              100993                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              77049                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              78387                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              77207                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              77888                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              72930                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              74368                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61890                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               67926                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               67010                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               65080                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               64889                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               68021                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64968                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65143                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               62358                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               69100                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              64674                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              67475                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              66848                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67005                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              63727                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64484                       # Per bank write bursts
+system.physmem.bw_write::total                1346242                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1345841                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4566                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4468                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              111185                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1447722                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8553                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2922335                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1279101                       # Number of read requests accepted
+system.physmem.writeReqs                      1081176                       # Number of write requests accepted
+system.physmem.readBursts                     1279101                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1081176                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 81811968                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     50496                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  69050112                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  80840680                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               69051172                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      789                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2248                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         335568                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               76700                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               81593                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               83146                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               75940                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               76984                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               83084                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               76647                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               76510                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               74528                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              104951                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              78345                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              82619                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              77692                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              79270                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              75132                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              75171                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               64170                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               68321                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               70316                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               66616                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               66722                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               70167                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               65460                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               67223                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               64606                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               72209                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              66721                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              70434                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              67362                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              68403                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              65406                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64772                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          26                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51331533904500                       # Total gap between requests
+system.physmem.numWrRetry                          27                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51291804197000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1219713                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1257816                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
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-system.physmem.writePktSize::6                1050292                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::4                       678                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17                      109                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::19                       76                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1078603                       # Write request sizes (log2)
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 system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -159,163 +159,162 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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 system.physmem.wrQLenPdf::62                       55                       # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples       475699                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      308.203229                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     177.287854                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     336.241632                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         186276     39.16%     39.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       111535     23.45%     62.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        45072      9.47%     72.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23389      4.92%     77.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18072      3.80%     80.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11535      2.42%     83.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10579      2.22%     85.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8108      1.70%     87.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        61133     12.85%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         475699                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59810                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.735663                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      269.812069                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          59807     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::63                       69                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       496985                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      303.554208                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.944807                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.108749                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         196641     39.57%     39.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       117090     23.56%     63.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        47261      9.51%     72.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        24196      4.87%     77.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18882      3.80%     81.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11863      2.39%     83.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10943      2.20%     85.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8246      1.66%     87.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        61863     12.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         496985                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61535                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.773365                       # Reads before turning the bus around for writes
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+system.physmem.rdPerTurnAround::0-2047          61532    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59810                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59810                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.565591                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.987331                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.225331                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           56970     95.25%     95.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             839      1.40%     96.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              56      0.09%     96.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             337      0.56%     97.31% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::60-63              38      0.06%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             506      0.85%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              29      0.05%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              24      0.04%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             125      0.21%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
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 system.physmem.wrPerTurnAround::84-87               1      0.00%     99.92% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.92% # Writes before turning the bus around for reads
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 system.physmem.wrPerTurnAround::100-103             2      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.01%     99.94% # Writes before turning the bus around for reads
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 system.physmem.wrPerTurnAround::128-131            25      0.04%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59810                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    31819415784                       # Total ticks spent queuing
-system.physmem.totMemAccLat               55073540784                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6201100000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25656.27                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::132-135             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           61535                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    32791506957                       # Total ticks spent queuing
+system.physmem.totMemAccLat               56759856957                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6391560000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25652.19                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44406.27                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.55                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.31                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.53                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.31                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44402.19                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.60                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.35                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.35                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.21                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1019502                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    795615                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.20                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.73                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22377767.94                       # Average gap between requests
-system.physmem.pageHitRate                      79.23                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1796611320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  980293875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4755496200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3401526960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352726044720                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1234173509595                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29716310123250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34314143605920                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.480817                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49435613390416                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1714072620000                       # Time in different power states
+system.physmem.avgWrQLen                        25.36                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1048127                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    812106                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.99                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.27                       # Row buffer hit rate for writes
+system.physmem.avgGap                     21731264.68                       # Average gap between requests
+system.physmem.pageHitRate                      78.92                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1887739560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1030016625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4918711200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3492687600                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3350131371600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1239587078895                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29687726109750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34288773715230                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.503935                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49388003607661                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1712746100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    181848672584                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    191055633589                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1799673120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  981964500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4918173000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3406348080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352726044720                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1238619690855                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29712409964250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34314861858525                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.494809                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49429083175074                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1714072620000                       # Time in different power states
+system.physmem_1.actEnergy                 1869467040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1020046500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5052099000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3498636240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3350131371600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1240740741510                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29686714133250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34289026495140                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.508863                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49386297692325                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1712746100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    188374993676                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    192761562675                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -339,15 +338,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               223536271                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         149385948                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12169974                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            157736918                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               103109650                       # Number of BTB hits
+system.cpu.branchPred.lookups               224688792                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         150206770                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12191755                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            158635537                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               103690237                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.368115                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30707782                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             342742                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.363814                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                30864801                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             343432                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -378,45 +377,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.dtb.walker.walks            196595                       # Table walker walks requested
-system.cpu.checker.dtb.walker.walksLong        196595                       # Table walker walks initiated with long descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples       196595                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0       196595    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total       196595                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walks            198718                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walksLong        198718                       # Table walker walks initiated with long descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples       198718                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0       198718    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total       198718                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.dtb.walker.walksPending::samples  -1584953796                       # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::0  -1584953796    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.checker.dtb.walker.walksPending::total  -1584953796                       # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K       153567     91.80%     91.80% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::2M        13723      8.20%    100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total       167290                       # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       196595                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkPageSizes::4K       154432     91.32%     91.32% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::2M        14687      8.68%    100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total       169119                       # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data       198718                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       196595                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       167290                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total       198718                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data       169119                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       167290                       # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total       363885                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total       169119                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total       367837                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits            159060610                       # DTB read hits
-system.cpu.checker.dtb.read_misses             146851                       # DTB read misses
-system.cpu.checker.dtb.write_hits           144228364                       # DTB write hits
-system.cpu.checker.dtb.write_misses             49744                       # DTB write misses
+system.cpu.checker.dtb.read_hits            159761932                       # DTB read hits
+system.cpu.checker.dtb.read_misses             147725                       # DTB read misses
+system.cpu.checker.dtb.write_hits           145062914                       # DTB write hits
+system.cpu.checker.dtb.write_misses             50993                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                   20                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.dtb.flush_tlb_mva_asid        78296                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.dtb.flush_tlb_asid            2034                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries            71608                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_tlb_mva_asid        79146                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_asid            2042                       # Number of times TLB was flushed by ASID
+system.cpu.checker.dtb.flush_entries            72161                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults           6498                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults           6829                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
-system.cpu.checker.dtb.perms_faults             18956                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses        159207461                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses       144278108                       # DTB write accesses
+system.cpu.checker.dtb.perms_faults             19116                       # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses        159909657                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses       145113907                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                 303288974                       # DTB hits
-system.cpu.checker.dtb.misses                  196595                       # DTB misses
-system.cpu.checker.dtb.accesses             303485569                       # DTB accesses
+system.cpu.checker.dtb.hits                 304824846                       # DTB hits
+system.cpu.checker.dtb.misses                  198718                       # DTB misses
+system.cpu.checker.dtb.accesses             305023564                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -446,46 +445,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.walker.walks            119842                       # Table walker walks requested
-system.cpu.checker.itb.walker.walksLong        119842                       # Table walker walks initiated with long descriptors
-system.cpu.checker.itb.walker.walkWaitTime::samples       119842                       # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::0       119842    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::total       119842                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walks            119115                       # Table walker walks requested
+system.cpu.checker.itb.walker.walksLong        119115                       # Table walker walks initiated with long descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples       119115                       # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0       119115    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total       119115                       # Table walker wait (enqueue to first request) latency
 system.cpu.checker.itb.walker.walksPending::samples  -1586149296                       # Table walker pending requests distribution
 system.cpu.checker.itb.walker.walksPending::0  -1586149296    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.checker.itb.walker.walksPending::total  -1586149296                       # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walkPageSizes::4K       108003     98.82%     98.82% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::2M         1286      1.18%    100.00% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::total       109289                       # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::4K       107231     98.82%     98.82% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::2M         1280      1.18%    100.00% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total       108511                       # Table walker page sizes translated
 system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       119842                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       119842                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst       119115                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total       119115                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       109289                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       109289                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin::total       229131                       # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits            845660985                       # ITB inst hits
-system.cpu.checker.itb.inst_misses             119842                       # ITB inst misses
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst       108511                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total       108511                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total       227626                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits            850192533                       # ITB inst hits
+system.cpu.checker.itb.inst_misses             119115                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
 system.cpu.checker.itb.write_misses                 0                       # DTB write misses
 system.cpu.checker.itb.flush_tlb                   20                       # Number of times complete TLB was flushed
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
-system.cpu.checker.itb.flush_tlb_mva_asid        78296                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.itb.flush_tlb_asid            2034                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries            51575                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_tlb_mva_asid        79146                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_asid            2042                       # Number of times TLB was flushed by ASID
+system.cpu.checker.itb.flush_entries            51914                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses        845780827                       # ITB inst accesses
-system.cpu.checker.itb.hits                 845660985                       # DTB hits
-system.cpu.checker.itb.misses                  119842                       # DTB misses
-system.cpu.checker.itb.accesses             845780827                       # DTB accesses
-system.cpu.checker.numCycles                993742997                       # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses        850311648                       # ITB inst accesses
+system.cpu.checker.itb.hits                 850192533                       # DTB hits
+system.cpu.checker.itb.misses                  119115                       # DTB misses
+system.cpu.checker.itb.accesses             850311648                       # DTB accesses
+system.cpu.checker.numCycles                999125211                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
@@ -517,85 +516,85 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    935593                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                935593                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15313                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       154778                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       425408                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       510185                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  2222.203710                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14681.416911                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535       506821     99.34%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071         1912      0.37%     99.72% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607          970      0.19%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143          202      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679          151      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215           19      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751           50      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::458752-524287           49      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::524288-589823            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       510185                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       473757                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23106.578900                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 18127.358359                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20599.365275                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       462892     97.71%     97.71% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         7688      1.62%     99.33% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         2250      0.47%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          174      0.04%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          494      0.10%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           87      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751          117      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           41      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       473757                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 784064516876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.722483                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.520538                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  781865994376     99.72%     99.72% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1176082000      0.15%     99.87% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     477234000      0.06%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     199500000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     146109500      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    120981500      0.02%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     26256500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     49725000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2626500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::18-19         7500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 784064516876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        154779     91.00%     91.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         15313      9.00%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       170092                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       935593                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks                    949667                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                949667                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        16250                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       155668                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       435817                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       513850                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2276.559307                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 14912.808509                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       510335     99.32%     99.32% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         1958      0.38%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607         1047      0.20%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          218      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          154      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215           27      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751           51      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287           54      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       513850                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       485169                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 23149.084134                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 18057.598080                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 21275.722761                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       473369     97.57%     97.57% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         7953      1.64%     99.21% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         2827      0.58%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          192      0.04%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          567      0.12%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215          106      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           98      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           42      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       485169                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 791579212632                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.715441                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.525649                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  789339278132     99.72%     99.72% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    1195712000      0.15%     99.87% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     474046500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     207567500      0.03%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     154449500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    121794500      0.02%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     29070000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     54831500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      2463000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 791579212632                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        155669     90.55%     90.55% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         16250      9.45%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       171919                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       949667                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       935593                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       170092                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       949667                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       171919                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       170092                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1105685                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       171919                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1121586                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    168870430                       # DTB read hits
-system.cpu.dtb.read_misses                     669785                       # DTB read misses
-system.cpu.dtb.write_hits                   146966916                       # DTB write hits
-system.cpu.dtb.write_misses                    265808                       # DTB write misses
+system.cpu.dtb.read_hits                    169633674                       # DTB read hits
+system.cpu.dtb.read_misses                     671728                       # DTB read misses
+system.cpu.dtb.write_hits                   147819857                       # DTB write hits
+system.cpu.dtb.write_misses                    277939                       # DTB write misses
 system.cpu.dtb.flush_tlb                           20                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               78296                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    2034                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    71844                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                        98                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   9429                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               79146                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    2042                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    72392                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                        97                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   9958                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     69613                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                169540215                       # DTB read accesses
-system.cpu.dtb.write_accesses               147232724                       # DTB write accesses
+system.cpu.dtb.perms_faults                     70151                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                170305402                       # DTB read accesses
+system.cpu.dtb.write_accesses               148097796                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         315837346                       # DTB hits
-system.cpu.dtb.misses                          935593                       # DTB misses
-system.cpu.dtb.accesses                     316772939                       # DTB accesses
+system.cpu.dtb.hits                         317453531                       # DTB hits
+system.cpu.dtb.misses                          949667                       # DTB misses
+system.cpu.dtb.accesses                     318403198                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -625,884 +624,885 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    161130                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                161130                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1443                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       121427                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17608                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       143522                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1275.602347                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  9467.048086                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       142512     99.30%     99.30% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          586      0.41%     99.70% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303           51      0.04%     99.74% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071           83      0.06%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839          223      0.16%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           32      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                    160444                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                160444                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1424                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       120836                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        17536                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       142908                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1360.753072                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 10149.850878                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       141808     99.23%     99.23% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          585      0.41%     99.64% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303           64      0.04%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071          103      0.07%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839          274      0.19%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           31      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375            7      0.00%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911           13      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911           17      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       143522                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       140478                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 29089.590541                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24285.230021                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 22670.988579                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       137385     97.80%     97.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071          891      0.63%     98.43% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1925      1.37%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           93      0.07%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          119      0.08%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           27      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           23      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       140478                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 668097269884                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.944108                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.230056                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     37393446856      5.60%      5.60% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    630652469528     94.40%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        50695000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          657500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4            1000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 668097269884                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        121427     98.83%     98.83% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1443      1.17%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       122870                       # Table walker page sizes translated
+system.cpu.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-425983            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       142908                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       139796                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 29385.243498                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24234.240486                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 24521.703817                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       136348     97.53%     97.53% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071          877      0.63%     98.16% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607         2201      1.57%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143          135      0.10%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679          151      0.11%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           29      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           40      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       139796                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 671317017344                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.945059                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.228245                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     36939918060      5.50%      5.50% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    634320646784     94.49%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        55500500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          942000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4           10000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 671317017344                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        120836     98.84%     98.84% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1424      1.16%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       122260                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161130                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       161130                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       160444                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       160444                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       122870                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       122870                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       284000                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    355391745                       # ITB inst hits
-system.cpu.itb.inst_misses                     161130                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       122260                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       122260                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       282704                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    357283873                       # ITB inst hits
+system.cpu.itb.inst_misses                     160444                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           20                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               78296                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    2034                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    52871                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               79146                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    2042                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    53225                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    369048                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    370647                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                355552875                       # ITB inst accesses
-system.cpu.itb.hits                         355391745                       # DTB hits
-system.cpu.itb.misses                          161130                       # DTB misses
-system.cpu.itb.accesses                     355552875                       # DTB accesses
-system.cpu.numCycles                       1639149006                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                357444317                       # ITB inst accesses
+system.cpu.itb.hits                         357283873                       # DTB hits
+system.cpu.itb.misses                          160444                       # DTB misses
+system.cpu.itb.accesses                     357444317                       # DTB accesses
+system.cpu.numCycles                       1651928956                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          642133876                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      997446842                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   223536271                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          133817432                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     910640256                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                25987402                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3814067                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                27748                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9296817                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1023598                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          983                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 355005878                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6082209                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   48751                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1579931046                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.739715                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.145918                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          644904840                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1002675339                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   224688792                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          134555038                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     920067624                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26040080                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3808104                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                29772                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       9331769                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1037128                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          949                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 356896495                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6093203                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   48590                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1592200226                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.737909                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.145097                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1024858413     64.87%     64.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                213048750     13.48%     78.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70422001      4.46%     82.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                271601882     17.19%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1034156168     64.95%     64.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                214254104     13.46%     78.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70725246      4.44%     82.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                273064708     17.15%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1579931046                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.136373                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.608515                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                522505611                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             567007663                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 431520293                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              49702709                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9194770                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33525771                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3859042                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1080875290                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              28941730                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9194770                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                566963257                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                68325752                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      370117398                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 436739828                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             128590041                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1061188804                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6761282                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5074872                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 331009                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 667465                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               77645177                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20261                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1009236679                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1634390089                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1255037462                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1470821                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             943893813                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65342863                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           26761446                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23109655                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 101993436                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            172887729                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           150512713                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9835963                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8956761                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1026341207                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27052915                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1041697414                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3264017                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60219112                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33542548                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         311458                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1579931046                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.659331                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.917837                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1592200226                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.136016                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.606972                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                524217376                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             575207225                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 433339906                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              50215792                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9219927                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33654884                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3860028                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1086626232                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              28988785                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9219927                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                568973528                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                70181306                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      374019312                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 438766207                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             131039946                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1066849636                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6780403                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               5130065                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 345924                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 553258                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               79683463                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            20375                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1014727198                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1644037540                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1261867774                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1469696                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             949117253                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 65609942                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           27037743                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23369810                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 103057716                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            173655780                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           151390357                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9897841                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9017927                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1031708315                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27333559                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1047312719                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3286243                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        60487130                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33695071                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         315067                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1592200226                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.657777                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.917314                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           935073091     59.18%     59.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           332737212     21.06%     80.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           233873919     14.80%     95.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            71794095      4.54%     99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6433566      0.41%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19163      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           943790813     59.28%     59.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           334741898     21.02%     80.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           234957148     14.76%     95.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            72204170      4.53%     99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6486970      0.41%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19227      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1579931046                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1592200226                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                57548727     35.04%     35.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 100099      0.06%     35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26751      0.02%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              757      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44132085     26.87%     62.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              62410380     38.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                57844214     35.03%     35.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  99575      0.06%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26721      0.02%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              685      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44353632     26.86%     61.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              62797684     38.03%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             717342377     68.86%     68.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2532202      0.24%     69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                122567      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   8      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         121087      0.01%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            172736633     16.58%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           148842483     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                 1      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             721297441     68.87%     68.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2539668      0.24%     69.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                122649      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         121234      0.01%     69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            173513888     16.57%     85.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           149717789     14.30%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1041697414                       # Type of FU issued
-system.cpu.iq.rate                           0.635511                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   164218799                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157645                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3828331710                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1112806179                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1023834597                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2476979                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             946356                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       909820                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1204359624                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1556578                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4281868                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1047312719                       # Type of FU issued
+system.cpu.iq.rate                           0.633994                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   165122511                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157663                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3852756863                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1118723028                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1029355100                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2477554                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             946947                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       909717                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1210878214                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1557015                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4319350                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13732493                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14369                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       140572                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6281305                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13798077                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14626                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       142237                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6323389                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2514322                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1544139                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2533948                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1563961                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9194770                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6870613                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               9053250                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1053615244                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9219927                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 7084785                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               9314562                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1059264038                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             172887729                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            150512713                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           22684457                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  56400                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               8925068                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         140572                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3644333                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5090402                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8734735                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1030574997                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             168857481                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10197714                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             173655780                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            151390357                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           22943670                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  58438                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               9182367                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         142237                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3657929                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5098518                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8756447                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1036137894                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             169621625                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10236296                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        221122                       # number of nop insts executed
-system.cpu.iew.exec_refs                    315819616                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                195518777                       # Number of branches executed
-system.cpu.iew.exec_stores                  146962135                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.628726                       # Inst execution rate
-system.cpu.iew.wb_sent                     1025549780                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1024744417                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 436186320                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 705504935                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.625169                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618261                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        51156578                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        26741457                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8371043                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1568002280                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.633402                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.269603                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        222164                       # number of nop insts executed
+system.cpu.iew.exec_refs                    317437095                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                196547238                       # Number of branches executed
+system.cpu.iew.exec_stores                  147815470                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.627229                       # Inst execution rate
+system.cpu.iew.wb_sent                     1031075002                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1030264817                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 438532269                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 709380763                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.623674                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.618190                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        51390718                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        27018492                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8391642                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1580228062                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.631905                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.268654                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1058124948     67.48%     67.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    286691231     18.28%     85.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    120053535      7.66%     93.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36420041      2.32%     95.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28336916      1.81%     97.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     13959603      0.89%     98.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8598360      0.55%     98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4160425      0.27%     99.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11657221      0.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1067496193     67.55%     67.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    288499411     18.26%     85.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    120593665      7.63%     93.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36542296      2.31%     95.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28489830      1.80%     97.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14035785      0.89%     98.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8641720      0.55%     98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4180750      0.26%     99.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11748412      0.74%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1568002280                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            845255961                       # Number of instructions committed
-system.cpu.commit.committedOps              993175006                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1580228062                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            849784302                       # Number of instructions committed
+system.cpu.commit.committedOps              998554740                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      303386643                       # Number of memory references committed
-system.cpu.commit.loads                     159155235                       # Number of loads committed
-system.cpu.commit.membars                     6901293                       # Number of memory barriers committed
-system.cpu.commit.branches                  188640484                       # Number of branches committed
-system.cpu.commit.fp_insts                     896738                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 912506063                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25186659                       # Number of function calls committed.
+system.cpu.commit.refs                      304924670                       # Number of memory references committed
+system.cpu.commit.loads                     159857702                       # Number of loads committed
+system.cpu.commit.membars                     6942890                       # Number of memory barriers committed
+system.cpu.commit.branches                  189641559                       # Number of branches committed
+system.cpu.commit.fp_insts                     896155                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 917432780                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25317062                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        687431731     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2146648      0.22%     69.43% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            97945      0.01%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       111997      0.01%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       159155235     16.02%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      144231408     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        691266097     69.23%     69.23% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2154064      0.22%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            98002      0.01%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       111865      0.01%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       159857702     16.01%     85.47% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      145066968     14.53%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         993175006                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11657221                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2593153041                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2100498051                       # The number of ROB writes
-system.cpu.timesIdled                         8123602                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        59217960                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101023921760                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   845255961                       # Number of Instructions Simulated
-system.cpu.committedOps                     993175006                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.939234                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.939234                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.515668                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.515668                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1219925781                       # number of integer regfile reads
-system.cpu.int_regfile_writes               728690577                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1462315                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   782072                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 224390859                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                225039549                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2563491272                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               26777143                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9646522                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.972803                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           282175483                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9647034                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.249973                       # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total         998554740                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11748412                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2610868733                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2111769063                       # The number of ROB writes
+system.cpu.timesIdled                         8146861                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59728730                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 100931682357                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   849784302                       # Number of Instructions Simulated
+system.cpu.committedOps                     998554740                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.943939                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.943939                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.514419                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.514419                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1226658290                       # number of integer regfile reads
+system.cpu.int_regfile_writes               732482520                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1461367                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   784012                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 225710355                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                226370154                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              2581410543                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               27063260                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9708370                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.972782                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           283529628                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9708882                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.203118                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.972803                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.972782                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          376                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          379                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1232341715                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1232341715                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146679057                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146679057                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127793945                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127793945                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       377283                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        377283                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       324111                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       324111                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3281173                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3281173                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3676011                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3676011                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     274473002                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        274473002                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    274850285                       # number of overall hits
-system.cpu.dcache.overall_hits::total       274850285                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9506685                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9506685                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11193954                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11193954                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1163770                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1163770                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1231562                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1231562                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       446112                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       446112                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1238524544                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1238524544                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    147275132                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       147275132                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128498890                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128498890                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       378449                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        378449                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       323156                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       323156                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3306743                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3306743                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3702780                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3702780                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     275774022                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        275774022                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    276152471                       # number of overall hits
+system.cpu.dcache.overall_hits::total       276152471                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9562571                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9562571                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11295910                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11295910                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1177323                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1177323                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1234379                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1234379                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       448575                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       448575                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20700639                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20700639                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21864409                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21864409                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 165615263000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 165615263000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 435458645679                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 435458645679                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  89047451888                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  89047451888                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6832433500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6832433500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     20858481                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20858481                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     22035804                       # number of overall misses
+system.cpu.dcache.overall_misses::total      22035804                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 169032232500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 169032232500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 449840740248                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 449840740248                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  90036958042                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  90036958042                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6928434500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6928434500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       275500                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       275500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 601073908679                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 601073908679                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 601073908679                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 601073908679                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    156185742                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    156185742                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    138987899                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    138987899                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1541053                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1541053                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1555673                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1555673                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3727285                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3727285                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3676016                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3676016                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    295173641                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    295173641                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    296714694                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    296714694                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060868                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060868                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080539                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080539                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.755178                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.755178                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791659                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.791659                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119688                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119688                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 618872972748                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 618872972748                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 618872972748                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 618872972748                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    156837703                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    156837703                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    139794800                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    139794800                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1555772                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1555772                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1557535                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1557535                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3755318                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3755318                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3702785                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3702785                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    296632503                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    296632503                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    298188275                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    298188275                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060971                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.060971                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080804                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080804                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.756745                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.756745                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.792521                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.792521                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119451                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119451                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070130                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070130                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073688                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073688                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17420.926748                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17420.926748                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38901.235942                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38901.235942                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72304.481535                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72304.481535                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15315.511576                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15315.511576                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070318                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070318                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.073899                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.073899                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17676.442089                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17676.442089                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39823.328997                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39823.328997                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72941.096731                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72941.096731                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15445.431645                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15445.431645                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55100                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55100                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29036.490549                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29036.490549                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27490.974427                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27490.974427                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     49516087                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29670.088284                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29670.088284                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28084.882800                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28084.882800                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     50470132                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1592102                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1604709                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.101077                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.451267                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7469877                       # number of writebacks
-system.cpu.dcache.writebacks::total           7469877                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4421127                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4421127                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9198347                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9198347                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         6981                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         6981                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218536                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       218536                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13619474                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13619474                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13619474                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13619474                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5085558                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5085558                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1995607                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1995607                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1156964                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1156964                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224581                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1224581                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227576                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       227576                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      7520985                       # number of writebacks
+system.cpu.dcache.writebacks::total           7520985                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4446912                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4446912                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9285751                       # number of WriteReq MSHR hits
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+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7178                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         7178                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219380                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       219380                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13732663                       # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::cpu.data     13732663                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13732663                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5115659                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5115659                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2010159                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2010159                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1170514                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1170514                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1227201                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1227201                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       229195                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       229195                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7081165                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7081165                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8238129                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8238129                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7125818                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7125818                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8296332                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8296332                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  83741631500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  83741631500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  76263176167                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  76263176167                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  22882989500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  22882989500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  87447550388                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  87447550388                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3189935000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3189935000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  85157095500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  85157095500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  78478155174                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  78478155174                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23792891000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23792891000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  88415534042                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  88415534042                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3234901000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3234901000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       270500                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       270500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160004807667                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 160004807667                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182887797167                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 182887797167                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192854000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192854000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228264964                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228264964                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12421118964                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12421118964                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032561                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032561                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014358                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014358                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.750762                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.750762                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787171                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787171                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061057                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061057                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163635250674                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 163635250674                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187428141674                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 187428141674                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6191802000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6191802000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228377464                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228377464                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12420179464                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12420179464                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032618                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032618                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014379                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014379                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.752369                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.752369                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787912                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787912                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061032                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061032                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023990                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.023990                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027764                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027764                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16466.557160                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16466.557160                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38215.528492                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38215.528492                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19778.480143                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19778.480143                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71410.180615                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71410.180615                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14017.009702                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14017.009702                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024022                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024022                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027822                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027822                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16646.358856                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16646.358856                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39040.769996                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39040.769996                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20326.874348                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20326.874348                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 72046.497715                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 72046.497715                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14114.186610                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14114.186610                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54100                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54100                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22595.831006                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22595.831006                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22200.161853                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22200.161853                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183884.256785                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183884.256785                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184836.923196                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184836.923196                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184360.717250                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184360.717250                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22963.714576                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22963.714576                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22591.687709                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22591.687709                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183853.019776                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183853.019776                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184840.261871                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184840.261871                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184346.772702                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184346.772702                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          14982836                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.916862                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           339236129                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          14983348                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.640876                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements          15025014                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.916800                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           341084146                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          15025526                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.700313                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       24730722500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.916862                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999838                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999838                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.916800                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999837                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999837                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           97                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         369968151                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        369968151                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    339236129                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       339236129                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     339236129                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        339236129                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    339236129                       # number of overall hits
-system.cpu.icache.overall_hits::total       339236129                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15748452                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15748452                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15748452                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15748452                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15748452                       # number of overall misses
-system.cpu.icache.overall_misses::total      15748452                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 212811738878                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 212811738878                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 212811738878                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 212811738878                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 212811738878                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 212811738878                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    354984581                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    354984581                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    354984581                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::cpu.inst    354984581                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    354984581                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044364                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044364                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044364                       # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::cpu.inst     0.044364                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044364                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13513.184590                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13513.184590                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13513.184590                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13513.184590                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13513.184590                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13513.184590                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        22549                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         371900940                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        371900940                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    341084146                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst 213656099879                       # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::total 213656099879                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    356875197                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total    356875197                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044248                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.044248                       # miss rate for ReadReq accesses
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+system.cpu.icache.demand_miss_rate::total     0.044248                       # miss rate for demand accesses
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+system.cpu.icache.overall_miss_rate::total     0.044248                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13530.201370                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13530.201370                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13530.201370                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13530.201370                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13530.201370                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13530.201370                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        23378                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1395                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1447                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    16.164158                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    16.156185                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks     14982836                       # number of writebacks
-system.cpu.icache.writebacks::total          14982836                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       764882                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       764882                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       764882                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       764882                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       764882                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       764882                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     14983570                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     14983570                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     14983570                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     14983570                       # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total     14983570                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     15025014                       # number of writebacks
+system.cpu.icache.writebacks::total          15025014                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       765308                       # number of ReadReq MSHR hits
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 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190589950887                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 190589950887                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190589950887                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 190589950887                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190589950887                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 190589950887                       # number of overall MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_miss_latency::total 191350406888                       # number of ReadReq MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042209                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.042209                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.042209                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12719.929288                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12719.929288                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12719.929288                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042104                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042104                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042104                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.042104                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042104                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.042104                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12734.838263                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12734.838263                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12734.838263                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12734.838263                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12734.838263                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12734.838263                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1120546                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65234.831512                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           45882504                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1182138                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.813154                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1160032                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65258.923808                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46054624                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1222499                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            37.672525                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      22908442500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37014.981518                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   292.089334                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   422.524862                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8026.847283                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19478.388514                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.564804                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004457                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006447                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.122480                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.297217                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995405                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          295                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61297                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          295                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          558                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2697                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5154                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52826                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004501                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.935318                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        407493288                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       407493288                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       779225                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       298670                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1077895                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      7469877                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      7469877                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     14980289                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     14980289                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9372                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9372                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 37170.221016                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   291.467899                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   431.621608                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7623.970972                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19741.642313                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.567173                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004447                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006586                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.116333                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.301234                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.995772                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          293                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62174                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          293                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          537                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2696                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5137                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53733                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004471                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.948700                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        409232486                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       409232486                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       784138                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       294772                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1078910                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      7520985                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      7520985                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     15022476                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     15022476                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         9415                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         9415                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1568886                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1568886                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14901485                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     14901485                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6220691                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6220691                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       731394                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       731394                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       779225                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       298670                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14901485                       # number of demand (read+write) hits
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-system.cpu.l2cache.demand_hits::total        23768957                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       779225                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       298670                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14901485                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7789577                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       23768957                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3206                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3174                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         6380                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        33876                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        33876                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1567928                       # number of ReadExReq hits
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+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14941736                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     14941736                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6252288                       # number of ReadSharedReq hits
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+system.cpu.l2cache.InvalidateReq_hits::cpu.data       727284                       # number of InvalidateReq hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       386656                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       386656                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        81874                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        81874                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       246229                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       246229                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       493187                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       493187                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         3206                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         3174                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        81874                       # number of demand (read+write) misses
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-system.cpu.l2cache.demand_misses::total        721139                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         3206                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         3174                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        81874                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       632885                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       721139                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    444507000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    436877000                       # number of ReadReq miss cycles
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-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1421351500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total   1421351500                       # number of UpgradeReq miss cycles
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
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-system.cpu.l2cache.InvalidateReq_miss_latency::total  76472888000                       # number of InvalidateReq miss cycles
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-system.cpu.l2cache.WritebackDirty_accesses::total      7469877                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       787797                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       298353                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1086150                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      7520985                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      7520985                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     15022476                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     15022476                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43844                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        43844                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1955542                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1955542                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     14983359                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     14983359                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6466920                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      6466920                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1224581                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1224581                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       782431                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       301844                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     14983359                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      8422462                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     24490096                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       782431                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       301844                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     14983359                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      8422462                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     24490096                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010515                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.005884                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.783296                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.783296                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1969613                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1969613                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     15025540                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     15025540                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6512078                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      6512078                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1227201                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1227201                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       787797                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       298353                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     15025540                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      8481691                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     24593381                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       787797                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       298353                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     15025540                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      8481691                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     24593381                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004645                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.012003                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.006666                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.785261                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.785261                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.600000                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.600000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.197723                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.197723                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005464                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005464                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.038075                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.038075                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.402739                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.402739                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.010515                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005464                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.075143                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.029446                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.010515                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005464                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.075143                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.029446                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137642.407057                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 138147.962382                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41957.477270                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41957.477270                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.203941                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.203941                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005577                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005577                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.039894                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.039894                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.407364                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.407364                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004645                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.012003                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005577                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.077989                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.030598                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004645                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.012003                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005577                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.077989                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.030598                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136977.999453                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137566.322256                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 137268.991713                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41410.221035                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41410.221035                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138807.494258                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138807.494258                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134607.335662                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134607.335662                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 138900.901194                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 138900.901194                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155058.604546                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155058.604546                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137642.407057                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134607.335662                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 138843.834978                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 138356.690596                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137642.407057                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134607.335662                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 138843.834978                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 138356.690596                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138987.986855                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138987.986855                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134754.623884                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134754.623884                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139216.442126                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139216.442126                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 154976.918168                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 154976.918168                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136977.999453                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137566.322256                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134754.623884                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139077.711176                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 138578.870434                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136977.999453                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137566.322256                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134754.623884                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139077.711176                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 138578.870434                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1511,41 +1511,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       943662                       # number of writebacks
-system.cpu.l2cache.writebacks::total           943662                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       971973                       # number of writebacks
+system.cpu.l2cache.writebacks::total           971973                       # number of writebacks
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           19                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total           19                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           19                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           19                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           19                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3206                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3174                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         6380                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3659                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3581                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         7240                       # number of ReadReq MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        33876                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        33876                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34429                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        34429                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       386656                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       386656                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        81874                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        81874                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       246210                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       246210                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       493187                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       493187                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3206                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3174                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        81874                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       632866                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       721120                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3206                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3174                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        81874                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       632866                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       721120                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       401685                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       401685                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        83804                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        83804                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       259771                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       259771                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       499917                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       499917                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3659                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3581                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        83804                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       661456                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       752500                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3659                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3581                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        83804                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       661456                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       752500                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54972                       # number of ReadReq MSHR uncacheable
@@ -1554,162 +1554,163 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    405137000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    817584000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2397445500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2397445500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    464612500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    456815000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    921427500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2436642500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2436642500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       212000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       212000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  49804190500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  49804190500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10202101000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10202101000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31736616500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31736616500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  71541018000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  71541018000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    405137000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10202101000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  81540807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  92560492000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    405137000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10202101000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  81540807000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  92560492000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  51812539500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  51812539500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10454936500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10454936500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33566675000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33566675000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  72476426000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  72476426000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    464612500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    456815000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10454936500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  85379214500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  96755578500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    464612500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    456815000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10454936500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  85379214500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  96755578500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5771724000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8190487000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836234500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836234500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770632000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189395000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836350500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836350500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607958500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14026721500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005884                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11606982500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14025745500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004645                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.012003                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006666                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783296                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783296                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.785261                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.785261                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.197723                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.197723                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005464                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038072                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038072                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.402739                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.402739                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.075140                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.029445                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.075140                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.029445                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128147.962382                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70771.209706                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70771.209706                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.203941                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.203941                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005577                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005577                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039891                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039891                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.407364                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.407364                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004645                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.012003                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005577                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.077986                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030598                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004645                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.012003                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005577                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.077986                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030598                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126977.999453                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127566.322256                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127268.991713                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70772.967556                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70772.967556                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128807.494258                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128807.494258                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124607.335662                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128900.599082                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128900.599082                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145058.604546                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145058.604546                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128843.715731                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128356.573108                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128843.715731                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128356.573108                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128987.986855                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128987.986855                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124754.623884                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124754.623884                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129216.405988                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129216.405988                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 144976.918168                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 144976.918168                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126977.999453                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127566.322256                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124754.623884                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129077.692998                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128578.841860                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126977.999453                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127566.322256                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124754.623884                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129077.692998                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128578.841860                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171379.654374                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148993.796842                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173202.590812                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173202.590812                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171347.229645                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148973.932184                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.033357                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.033357                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172291.366106                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158193.728290                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172276.879805                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158182.720937                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     49994853                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     25364266                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3498                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2149                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2149                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     50209605                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     25474994                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3484                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2120                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2120                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq        1617841                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23069110                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1623677                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23162262                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      8520195                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     14980289                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2361594                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43251                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8599615                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     15022476                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2383518                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43847                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43256                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1955542                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1955542                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     14983570                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6475758                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1331245                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1224581                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     44989806                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29161893                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       729252                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1917892                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          76798843                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1918014176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1017349854                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2414752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6259448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2944038230                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1831110                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     27676926                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.025201                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.156737                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43852                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1969613                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1969613                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     15025743                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6520923                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1333865                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1227201                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45116347                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29348618                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       723959                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1930896                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          77119820                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1923413728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1024410462                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2386824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6302376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2956513390                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1874549                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     27826881                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025283                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.156985                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           26979426     97.48%     97.48% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             697500      2.52%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           27123321     97.47%     97.47% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             703560      2.53%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       27676926                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    47946942997                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       27826881                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    48147469995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1474889                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1446401                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22505485675                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   22568730706                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13321051501                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13411529968                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     427763271                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     425937320                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1135810761                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1143472216                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40286                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40286                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40293                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40293                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1719,18 +1720,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230930                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230930                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230944                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230944                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353714                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353728                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1740,24 +1739,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334152                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334152                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334208                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334208                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492072                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             41870500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492128                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             41872500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               342000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
@@ -1770,79 +1768,73 @@ system.iobus.reqLayer16.occupancy               14500                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25173000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25139500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              168500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36500500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            36497500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           565848565                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              129000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565751099                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               44500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147690000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147704000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115446                       # number of replacements
-system.iocache.tags.tagsinuse               10.422238                       # Cycle average of tags in use
+system.iocache.tags.replacements               115453                       # number of replacements
+system.iocache.tags.tagsinuse               10.417914                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115462                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115469                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         13103145499000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.543896                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.878342                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221494                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429896                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651390                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ethernet     3.546638                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.871276                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221665                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.429455                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651120                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039542                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039542                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039605                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039605                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8801                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8838                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8808                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8845                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8801                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8841                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8808                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8848                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8801                       # number of overall misses
-system.iocache.overall_misses::total             8841                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1693888006                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1698957506                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8808                       # number of overall misses
+system.iocache.overall_misses::total             8848                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5070500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1690818481                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1695888981                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13866022593                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13866022593                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1693888006                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1699308506                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1693888006                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1699308506                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13865997584                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13865997584                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5421500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1690818481                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1696239981                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5421500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1690818481                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1696239981                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8801                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8838                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8808                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8845                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8801                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8841                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8808                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8848                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8801                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8841                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8808                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8848                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1856,55 +1848,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 192465.402341                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 192233.254809                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 191963.951067                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 191734.197965                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129997.211740                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129997.211740                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 192465.402341                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 192207.726049                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 192465.402341                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 192207.726049                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         36226                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129996.977274                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129996.977274                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 191963.951067                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 191708.858612                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 191963.951067                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 191708.858612                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         36185                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3621                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3641                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.004419                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.938204                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8801                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8838                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8808                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8845                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8801                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8841                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8808                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8848                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8801                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8841                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1253838006                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1257057506                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8808                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8848                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1250418481                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1253638981                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8532822593                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8532822593                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1253838006                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1257258506                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1253838006                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1257258506                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8532797584                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8532797584                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3421500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1250418481                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1253839981                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3421500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1250418481                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1253839981                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1918,73 +1910,73 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142465.402341                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 142233.254809                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141963.951067                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 141734.197965                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79997.211740                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79997.211740                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 142465.402341                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 142207.726049                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 142465.402341                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 142207.726049                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79996.977274                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79996.977274                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 141963.951067                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 141708.858612                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 141963.951067                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 141708.858612                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
-system.membus.trans_dist::ReadResp             398274                       # Transaction distribution
+system.membus.trans_dist::ReadResp             414632                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1050292                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           182485                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34687                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1078603                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           193680                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35229                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           34690                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            879035                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           879035                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        343302                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           35232                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            900805                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           900805                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        359660                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3662907                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3792527                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342336                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342336                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4134863                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3779727                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3909347                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342337                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342337                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4251684                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    138377164                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    138547134                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7264192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7264192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               145811326                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2632                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2687314                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    142628812                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    142798782                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7263040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7263040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               150061822                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2657                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2765486                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2687314    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2765486    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2687314                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           103976500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2765486                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           103948000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               32000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5452000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5458000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7124848125                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7323908114                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6613283400                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6816104590                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          227684837                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227615986                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2039,6 +2031,6 @@ system.realview.mcc.osc_mcc.clock               20000                       # Cl
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16105                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    16126                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal
index 27543035d..1b50f034a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal
@@ -104,13 +104,13 @@
 [    3.136841] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]

 [    3.136852] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]

 [    3.136885] pci_bus 0000:00: fixups for bus

-[    3.136894] pci_bus 0000:00: bus scan returning with max=00

+[    3.136893] pci_bus 0000:00: bus scan returning with max=00

 [    3.136906] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc

 [    3.136925] pci 0000:00:00.0: fixup irq: got 33

-[    3.136934] pci 0000:00:00.0: assigning IRQ 33

+[    3.136933] pci 0000:00:00.0: assigning IRQ 33

 [    3.136944] pci 0000:00:01.0: fixup irq: got 34

 [    3.136952] pci 0000:00:01.0: assigning IRQ 34

-[    3.136964] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

+[    3.136963] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

 [    3.136976] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]

 [    3.136989] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

 [    3.137002] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

@@ -119,17 +119,17 @@
 [    3.137036] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

 [    3.137048] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

 [    3.137493] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

-[    3.137734] ata_piix 0000:00:01.0: version 2.13

-[    3.137745] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

-[    3.137769] ata_piix 0000:00:01.0: enabling bus mastering

-[    3.138034] scsi0 : ata_piix

-[    3.138126] scsi1 : ata_piix

-[    3.138154] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

-[    3.138167] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

-[    3.138266] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

-[    3.138278] e1000: Copyright (c) 1999-2006 Intel Corporation.

-[    3.138293] e1000 0000:00:00.0: enabling device (0000 -> 0002)

-[    3.138304] e1000 0000:00:00.0: enabling bus mastering

+[    3.137735] ata_piix 0000:00:01.0: version 2.13

+[    3.137746] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

+[    3.137770] ata_piix 0000:00:01.0: enabling bus mastering

+[    3.138035] scsi0 : ata_piix

+[    3.138128] scsi1 : ata_piix

+[    3.138156] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

+[    3.138168] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

+[    3.138267] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

+[    3.138279] e1000: Copyright (c) 1999-2006 Intel Corporation.

+[    3.138294] e1000 0000:00:00.0: enabling device (0000 -> 0002)

+[    3.138306] e1000 0000:00:00.0: enabling bus mastering

 [    3.290915] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66

 [    3.290924] ata1.00: 2096640 sectors, multi 0: LBA 

 [    3.290951] ata1.00: configured for UDMA/33

@@ -160,7 +160,7 @@
 
 [    3.450398] udevd[607]: starting version 182

 Starting Bootlog daemon: bootlogd.


-[    3.543435] random: dd urandom read with 19 bits of entropy available

+[    3.533417] random: dd urandom read with 19 bits of entropy available

 Populating dev cache


 net.ipv4.conf.default.rp_filter = 1


 net.ipv4.conf.all.rp_filter = 1


@@ -168,7 +168,7 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory
 Mon Jan 27 08:00:00 UTC 2014


 hwclock: can't open '/dev/misc/rtc': No such file or directory


 
INIT: Entering runlevel: 5



-Configuring network interfaces... [    3.671120] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

+Configuring network interfaces... [    3.661125] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

 udhcpc (v1.21.1) started


 Sending discover...


 Sending discover...


diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
index 17e0e65c9..11768aa62 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -1423,10 +1423,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -1453,7 +1452,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1617,12 +1616,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -1715,16 +1711,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1740,7 +1735,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1903,13 +1898,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1919,9 +1914,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1963,7 +1957,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -2044,14 +2038,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -2068,7 +2061,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -2083,7 +2076,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -2206,17 +2199,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -2268,7 +2263,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -2283,7 +2278,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
index 7a8adf6ca..4c70e8d66 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
@@ -11,4 +11,3 @@ warn: allocating bonus target for snoop
 warn: allocating bonus target for snoop
 warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
 warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: allocating bonus target for snoop
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
index 38e5abd49..cc1e1c387 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 18:32:57
-gem5 executing on e104799-lin, pid 8213
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 13:59:02
+gem5 executing on e104799-lin, pid 13304
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 47314506373000 because m5_exit instruction encountered
+Exiting @ tick 47393980707000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
index d00fb13a2..5e9f9ee14 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
@@ -1,172 +1,172 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.314506                       # Number of seconds simulated
-sim_ticks                                47314506373000                       # Number of ticks simulated
-final_tick                               47314506373000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.393981                       # Number of seconds simulated
+sim_ticks                                47393980707000                       # Number of ticks simulated
+final_tick                               47393980707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  98624                       # Simulator instruction rate (inst/s)
-host_op_rate                                   115961                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5063135105                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 768296                       # Number of bytes of host memory used
-host_seconds                                  9344.90                       # Real time elapsed on the host
-sim_insts                                   921635123                       # Number of instructions simulated
-sim_ops                                    1083644532                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 118826                       # Simulator instruction rate (inst/s)
+host_op_rate                                   139727                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6107626980                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 769604                       # Number of bytes of host memory used
+host_seconds                                  7759.80                       # Real time elapsed on the host
+sim_insts                                   922064003                       # Number of instructions simulated
+sim_ops                                    1084251192                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       141824                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       130048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          4236960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         43669256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     19384064                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       193856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       178880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3171232                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         16700240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher     15629760                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        443968                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            103880088                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      4236960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3171232                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7408192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     86326016                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       150400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       142336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          4326432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         44486728                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     20365824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       171008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       152256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3129632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         15575440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher     14887232                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        428800                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            103816088                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      4326432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3129632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7456064                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     86117376                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          86346600                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2216                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2032                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             82155                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            682345                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       302876                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         3029                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2795                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             49594                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            260954                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       244215                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6937                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1639148                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1348844                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          86137960                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2350                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         2224                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             83553                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            695118                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       318216                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2672                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2379                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             48944                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            243379                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       232613                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6700                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1638148                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1345584                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1351418                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2997                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2749                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               89549                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              922957                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       409685                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          4097                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3781                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               67025                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              352962                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       330338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             9383                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2195523                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          89549                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          67025                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             156573                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1824515                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                435                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1348158                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          3173                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          3003                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               91287                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              938658                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       429713                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          3608                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          3213                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               66034                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              328638                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       314117                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9048                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2190491                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          91287                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          66034                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             157321                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1817053                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1824950                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1824515                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2997                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2749                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              89549                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             923392                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       409685                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         4097                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3781                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              67025                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             352962                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       330338                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            9383                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4020473                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1639148                       # Number of read requests accepted
-system.physmem.writeReqs                      1351418                       # Number of write requests accepted
-system.physmem.readBursts                     1639148                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1351418                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                104871744                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     33728                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  86344960                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 103880088                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               86346600                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      527                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1817487                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1817053                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         3173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         3003                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              91287                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             939092                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       429713                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         3608                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         3213                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              66034                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             328638                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       314117                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9048                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4007978                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1638148                       # Number of read requests accepted
+system.physmem.writeReqs                      1348158                       # Number of write requests accepted
+system.physmem.readBursts                     1638148                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1348158                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                104808896                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     32576                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  86137280                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 103816088                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               86137960                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      509                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         532498                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              106578                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              104344                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              100892                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              102125                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              100013                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              109287                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              101103                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               99682                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               97394                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              128253                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              98226                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              99141                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              97088                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             102696                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              95500                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              96299                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               86551                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               88756                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               83871                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               85066                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               83226                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               90269                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               84251                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               84163                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               81439                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               87752                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              80936                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              83767                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              81736                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              86099                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              79882                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              81376                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         529318                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               98506                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              102125                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               96514                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              101212                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               98283                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              109978                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              106703                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              105175                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               93813                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              120186                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              99379                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             109206                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              97639                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             103304                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              94884                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             100732                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               82092                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               86582                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               80748                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               83407                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               81928                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               88947                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               86848                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               87370                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               79257                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               83439                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              82066                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              89206                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              82040                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              87648                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              80198                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              84119                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          31                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47314504873500                       # Total gap between requests
+system.physmem.numWrRetry                          13                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47393979099500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1617790                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1616790                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1348844                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    620628                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    413232                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    168696                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::14                      943                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::21                        8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1345584                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    619728                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    417888                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::22                        5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
@@ -188,169 +188,163 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::60                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       63                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1061449                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      180.146498                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     111.187522                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     239.320652                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         660214     62.20%     62.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       197053     18.56%     80.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        62946      5.93%     86.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        34930      3.29%     89.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        24785      2.34%     92.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        13743      1.29%     93.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        13849      1.30%     94.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7639      0.72%     95.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        46290      4.36%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1061449                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         76381                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.453032                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      249.608933                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          76378    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::50                      204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      210                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       35                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1054994                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      180.992301                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     111.466356                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     240.522304                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         655278     62.11%     62.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       195680     18.55%     80.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        62552      5.93%     86.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        34743      3.29%     89.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        24726      2.34%     92.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        13789      1.31%     93.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        13873      1.31%     94.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         7523      0.71%     95.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        46830      4.44%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1054994                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         76193                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.493169                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      249.861284                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          76190    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::65536-69631            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           76381                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         76381                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.663293                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.185244                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.515109                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           70865     92.78%     92.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            3094      4.05%     96.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             460      0.60%     97.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             346      0.45%     97.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              86      0.11%     98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             303      0.40%     98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             170      0.22%     98.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47             108      0.14%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51             111      0.15%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              84      0.11%     99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              42      0.05%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              72      0.09%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             382      0.50%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              49      0.06%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              51      0.07%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              81      0.11%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              17      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             3      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           76193                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         76193                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.664287                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.191501                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.434084                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           70631     92.70%     92.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23            3142      4.12%     96.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             485      0.64%     97.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             323      0.42%     97.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              79      0.10%     97.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             306      0.40%     98.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             178      0.23%     98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47             116      0.15%     98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              95      0.12%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              99      0.13%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              41      0.05%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              55      0.07%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             407      0.53%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              35      0.05%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              33      0.04%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              86      0.11%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83              20      0.03%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               6      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             6      0.01%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::108-111             1      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             4      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            25      0.03%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            28      0.04%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           76381                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    70826288095                       # Total ticks spent queuing
-system.physmem.totMemAccLat              101550431845                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   8193105000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       43223.11                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           76193                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    70239099561                       # Total ticks spent queuing
+system.physmem.totMemAccLat              100944830811                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   8188195000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       42890.47                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  61973.11                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.22                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  61640.47                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.21                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.82                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.20                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.19                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.82                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.33                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.65                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1314681                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    611629                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.23                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  45.33                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15821254.20                       # Average gap between requests
-system.physmem.pageHitRate                      64.47                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 4090980600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 2232181875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6427387200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4446271440                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3090353329440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1181376195975                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27352407006750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31641333353280                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.744914                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45502947755010                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1579935240000                       # Time in different power states
+system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.73                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1316973                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    611565                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.42                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  45.44                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15870436.28                       # Average gap between requests
+system.physmem.pageHitRate                      64.64                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 4035157560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 2201722875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6384222000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               4392934560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3095544201360                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1182732038730                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27398902223250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31694192500335                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.738819                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45580299815708                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1582589060000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    231620211240                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    231091139792                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3933573840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 2146295250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                6353809800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4296155760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3090353329440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1178540083170                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27354894825000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31640518072260                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.727683                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45507092069935                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1579935240000                       # Time in different power states
+system.physmem_1.actEnergy                 3940597080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 2150127375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                6389315400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               4328465040                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3095544201360                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1183329754695                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27398377902750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31694060363700                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.736031                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45579400276584                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1582589060000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    227478372065                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    231988109666                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -384,15 +378,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              132773230                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         87983669                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          6601963                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            93351299                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               61553732                       # Number of BTB hits
+system.cpu0.branchPred.lookups              135522453                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         89756354                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          6696164                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            95487916                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               63232655                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            65.937735                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               18245658                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            197691                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            66.220583                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               18624977                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            201233                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -423,85 +417,85 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   574649                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               574649                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        12370                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        88781                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       269295                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       305354                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2428.535405                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 14847.246962                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       302828     99.17%     99.17% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1395      0.46%     99.63% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          849      0.28%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          146      0.05%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679           44      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                   590400                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               590400                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        12973                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        94460                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       278631                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       311769                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2427.181663                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 14785.327659                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       309280     99.20%     99.20% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1331      0.43%     99.63% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          885      0.28%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          124      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679           48      0.02%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::327680-393215           73      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751           14      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       305354                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       295785                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 20483.935967                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 17662.897721                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 19270.228379                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       292925     99.03%     99.03% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          638      0.22%     99.25% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1609      0.54%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          142      0.05%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          290      0.10%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           80      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           60      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           29      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       295785                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 533721818468                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.601728                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.544409                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 532429522968     99.76%     99.76% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3    722596500      0.14%     99.89% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5    256398500      0.05%     99.94% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7    121663500      0.02%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9     95265000      0.02%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11     53651000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13     19676500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15     22307000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17       728500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19         9000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 533721818468                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        88781     87.77%     87.77% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        12370     12.23%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       101151                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       574649                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::393216-458751           22      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       311769                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       310891                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 20766.069137                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 17798.694444                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 20375.668326                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       307651     98.96%     98.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          747      0.24%     99.20% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1834      0.59%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143          107      0.03%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          307      0.10%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215          102      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           75      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287           36      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823           21      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       310891                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 523001837252                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.567345                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.551290                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 521647732752     99.74%     99.74% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3    761373500      0.15%     99.89% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5    275460500      0.05%     99.94% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7    125915000      0.02%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9     99351000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11     52861000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13     16652500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15     21714500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17       741500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19        35000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 523001837252                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        94460     87.92%     87.92% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        12973     12.08%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       107433                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       590400                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       574649                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       101151                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       590400                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       107433                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       101151                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       675800                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       107433                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       697833                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    96498807                       # DTB read hits
-system.cpu0.dtb.read_misses                    413728                       # DTB read misses
-system.cpu0.dtb.write_hits                   78559139                       # DTB write hits
-system.cpu0.dtb.write_misses                   160921                       # DTB write misses
+system.cpu0.dtb.read_hits                    98363253                       # DTB read hits
+system.cpu0.dtb.read_misses                    426453                       # DTB read misses
+system.cpu0.dtb.write_hits                   80524387                       # DTB write hits
+system.cpu0.dtb.write_misses                   163947                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              44695                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid              44673                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   38359                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      510                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  7352                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                   40807                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      204                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  7493                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    37571                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                96912535                       # DTB read accesses
-system.cpu0.dtb.write_accesses               78720060                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    42725                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                98789706                       # DTB read accesses
+system.cpu0.dtb.write_accesses               80688334                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        175057946                       # DTB hits
-system.cpu0.dtb.misses                         574649                       # DTB misses
-system.cpu0.dtb.accesses                    175632595                       # DTB accesses
+system.cpu0.dtb.hits                        178887640                       # DTB hits
+system.cpu0.dtb.misses                         590400                       # DTB misses
+system.cpu0.dtb.accesses                    179478040                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -531,210 +525,206 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    78486                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                78486                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          887                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        55688                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore         9272                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        69214                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1487.228017                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 11268.156243                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        68484     98.95%     98.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          441      0.64%     99.58% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303           31      0.04%     99.63% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071           33      0.05%     99.67% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839          145      0.21%     99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           56      0.08%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        69214                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        65847                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26575.804517                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 22865.862438                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 26620.164914                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        64258     97.59%     97.59% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071          112      0.17%     97.76% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607         1232      1.87%     99.63% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           99      0.15%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           79      0.12%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           35      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           19      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287           11      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    85262                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                85262                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1098                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        61891                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore         9791                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        75471                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1466.000186                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 11351.229924                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-65535        75137     99.56%     99.56% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-131071           79      0.10%     99.66% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-196607          235      0.31%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-262143            9      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        75471                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        72780                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 26660.353119                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 23025.074927                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 26139.582838                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        71045     97.62%     97.62% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          123      0.17%     97.79% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607         1365      1.88%     99.66% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           91      0.13%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           88      0.12%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           30      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           31      0.04%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        65847                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 404869617088                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.839049                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.367685                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    65190904252     16.10%     16.10% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   339654890336     83.89%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       21211000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        2423500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         188000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 404869617088                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        55688     98.43%     98.43% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          887      1.57%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        56575                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total        72780                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 389854695076                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     0.839132                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev     0.367626                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0    62743884640     16.09%     16.09% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   327084697936     83.90%     99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       23698000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        2390500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4          24000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 389854695076                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        61891     98.26%     98.26% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         1098      1.74%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        62989                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        78486                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        78486                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        85262                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        85262                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        56575                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        56575                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       135061                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   209228100                       # ITB inst hits
-system.cpu0.itb.inst_misses                     78486                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        62989                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        62989                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       148251                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   213975614                       # ITB inst hits
+system.cpu0.itb.inst_misses                     85262                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              44695                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid              44673                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   27529                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                   29309                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   202656                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   214464                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               209306586                       # ITB inst accesses
-system.cpu0.itb.hits                        209228100                       # DTB hits
-system.cpu0.itb.misses                          78486                       # DTB misses
-system.cpu0.itb.accesses                    209306586                       # DTB accesses
-system.cpu0.numCycles                       789288757                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               214060876                       # ITB inst accesses
+system.cpu0.itb.hits                        213975614                       # DTB hits
+system.cpu0.itb.misses                          85262                       # DTB misses
+system.cpu0.itb.accesses                    214060876                       # DTB accesses
+system.cpu0.numCycles                       807659312                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          88186567                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     587222731                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  132773230                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          79799390                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    653950437                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               14236776                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   1849931                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles              326899                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles      5945958                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       775108                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles       835772                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                209027134                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              1689441                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  26384                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         758989060                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.905560                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            1.200949                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          88233839                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     599476727                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  135522453                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          81857632                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    670713114                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               14447630                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2036483                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles              334818                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles      6261942                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       813783                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles       863786                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                213760838                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              1698349                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  28412                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         776481580                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.903685                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.199979                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               429796828     56.63%     56.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1               127839256     16.84%     73.47% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                44588296      5.87%     79.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3               156764680     20.65%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               440207018     56.69%     56.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1               130689201     16.83%     73.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                45750499      5.89%     79.42% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3               159834862     20.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           758989060                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.168219                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.743990                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               104466806                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            394260374                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                219139619                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             36084867                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5037394                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19164568                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              2120604                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             606612799                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts             22830363                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5037394                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               138662412                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               63104555                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     247113571                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                220473798                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             84597330                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             589875332                       # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts              5798642                       # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents             10641909                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                381250                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents                853231                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              50687884                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents           10092                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          564041119                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            911558490                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       696481853                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           699850                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            508008632                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                56032481                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          14857922                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      12905611                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 72985645                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            96647129                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           81788442                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          8697028                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         7422933                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 568689811                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           14912069                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                572654206                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued          2621739                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       52458189                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     34404562                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        258659                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    758989060                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.754496                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.046900                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           776481580                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.167797                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.742240                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               105533428                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            405339788                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                223093644                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             37388098                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5126622                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19615970                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              2136984                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             619581339                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts             23102207                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5126622                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               140592491                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               65041706                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     253704898                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                224831888                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             87183975                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             602582059                       # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts              5894427                       # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents             10859505                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                384608                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents                879717                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              52095352                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents           10977                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          576174683                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            933371731                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       711261087                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           684793                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            519247735                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                56926942                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15518812                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13493208                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 75428854                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            98376014                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           83834868                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          8883598                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         7640207                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 580665271                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15522553                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                585221400                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued          2674583                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       53398017                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     34936380                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        261009                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    776481580                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.753684                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.045500                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          446419238     58.82%     58.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1          130584028     17.20%     76.02% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2          111330924     14.67%     90.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           63215854      8.33%     99.02% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            7434312      0.98%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5               4704      0.00%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          456332573     58.77%     58.77% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1          134692381     17.35%     76.12% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2          113447710     14.61%     90.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           64406978      8.29%     99.02% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            7597025      0.98%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5               4913      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      758989060                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      776481580                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu               59334745     45.62%     45.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 61701      0.05%     45.67% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                  15638      0.01%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc              17      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead              34211739     26.30%     71.98% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite             36440950     28.02%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu               60244006     45.44%     45.44% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 62130      0.05%     45.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                  15273      0.01%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc              15      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead              34917494     26.34%     71.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite             37330795     28.16%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            391815865     68.42%     68.42% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1438003      0.25%     68.67% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                75602      0.01%     68.69% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            400469737     68.43%     68.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1445270      0.25%     68.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                74848      0.01%     68.69% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     68.69% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.69% # Type of FU issued
 system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.69% # Type of FU issued
@@ -757,949 +747,948 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.69% # Ty
 system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.69% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.69% # Type of FU issued
 system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         42288      0.01%     68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            99488891     17.37%     86.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           79793556     13.93%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         41036      0.01%     68.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           101401840     17.33%     86.02% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           81788668     13.98%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             572654206                       # Type of FU issued
-system.cpu0.iq.rate                          0.725532                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                  130064790                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.227126                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        2035873022                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        635743875                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    556160378                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1110977                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            443650                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       409772                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             702028683                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 690312                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         2617659                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             585221400                       # Type of FU issued
+system.cpu0.iq.rate                          0.724589                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                  132569713                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.226529                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        2081071755                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        649281804                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    568296572                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1096919                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            437057                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       404655                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             717109128                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 681984                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         2687978                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     11976787                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        15696                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       128509                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      5549515                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     12198109                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        15815                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       133954                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      5685458                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2485031                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      4622903                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2533664                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      4860713                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5037394                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                7963594                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              7170717                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          583715188                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles               5126622                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                8215667                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles              7173428                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          596307716                       # Number of instructions dispatched to IQ
 system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             96647129                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            81788442                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          12627210                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 54569                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              7047111                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        128509                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       1976888                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2838838                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             4815726                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            565090405                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             96493854                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          6996299                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts             98376014                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            83834868                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13216543                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 57072                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents              7044703                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        133954                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2031236                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2866413                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             4897649                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            577519741                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             98358575                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          7118543                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       113308                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   175051410                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               106737211                       # Number of branches executed
-system.cpu0.iew.exec_stores                  78557556                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.715949                       # Inst execution rate
-system.cpu0.iew.wb_sent                     557331942                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    556570150                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                270940614                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                444738310                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.705154                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.609214                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       45776609                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       14653410                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4520969                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    750266004                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.707940                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.517135                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       119892                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   178881734                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               109041178                       # Number of branches executed
+system.cpu0.iew.exec_stores                  80523159                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.715054                       # Inst execution rate
+system.cpu0.iew.wb_sent                     569480217                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    568701227                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                276442254                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                453748356                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.704135                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.609241                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       46598328                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15261544                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4598971                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    767596191                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.707129                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.516118                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    517711139     69.00%     69.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1    119807975     15.97%     84.97% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     52242096      6.96%     91.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     17345693      2.31%     94.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     12502849      1.67%     95.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      8569717      1.14%     97.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      5628818      0.75%     97.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3480187      0.46%     98.27% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     12977530      1.73%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    529386438     68.97%     68.97% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1    123369518     16.07%     85.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     53181556      6.93%     91.97% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     17664925      2.30%     94.27% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     12675398      1.65%     95.92% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      8710511      1.13%     97.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      5748655      0.75%     97.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3557202      0.46%     98.27% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     13301988      1.73%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    750266004                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           452897446                       # Number of instructions committed
-system.cpu0.commit.committedOps             531143684                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    767596191                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           462839739                       # Number of instructions committed
+system.cpu0.commit.committedOps             542789800                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     160909268                       # Number of memory references committed
-system.cpu0.commit.loads                     84670341                       # Number of loads committed
-system.cpu0.commit.membars                    3612111                       # Number of memory barriers committed
-system.cpu0.commit.branches                 101352463                       # Number of branches committed
-system.cpu0.commit.fp_insts                    401266                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                487082373                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13540419                       # Number of function calls committed.
+system.cpu0.commit.refs                     164327314                       # Number of memory references committed
+system.cpu0.commit.loads                     86177904                       # Number of loads committed
+system.cpu0.commit.membars                    3634236                       # Number of memory barriers committed
+system.cpu0.commit.branches                 103555612                       # Number of branches committed
+system.cpu0.commit.fp_insts                    396011                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                497579695                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13818381                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       368934944     69.46%     69.46% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1203387      0.23%     69.69% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           59505      0.01%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.70% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        36580      0.01%     69.71% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.71% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.71% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.71% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       84670341     15.94%     85.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      76238927     14.35%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       377157891     69.49%     69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1210852      0.22%     69.71% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           58620      0.01%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.72% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        35123      0.01%     69.73% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.73% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.73% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.73% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       86177904     15.88%     85.60% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      78149410     14.40%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        531143684                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             12977530                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1309875410                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1162529912                       # The number of ROB writes
-system.cpu0.timesIdled                         987855                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       30299697                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 93839724027                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  452897446                       # Number of Instructions Simulated
-system.cpu0.committedOps                    531143684                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.742754                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.742754                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.573805                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.573805                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               666947650                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              396615179                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   682678                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  298828                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                124079442                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               124706529                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1318525921                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              14734262                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements          5881965                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          478.956800                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          149156359                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5882471                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            25.356072                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total        542789800                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             13301988                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1339296609                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1187626415                       # The number of ROB writes
+system.cpu0.timesIdled                        1008617                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       31177732                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 93980302134                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  462839739                       # Number of Instructions Simulated
+system.cpu0.committedOps                    542789800                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.745009                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.745009                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.573063                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.573063                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               681400785                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              404691660                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   669454                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  305508                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                127155216                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               127713312                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1347757085                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15341922                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements          6037671                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          477.387062                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          152039806                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          6038183                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            25.179728                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       2962390000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   478.956800                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.935463                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.935463                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          506                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          370                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.988281                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        334047120                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       334047120                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     78452229                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       78452229                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     65886147                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      65886147                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       209885                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       209885                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       258671                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       258671                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1757048                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1757048                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1773588                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1773588                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    144338376                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       144338376                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    144548261                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      144548261                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6459284                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      6459284                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      7288144                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      7288144                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       689122                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       689122                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       817042                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       817042                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       245228                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       245228                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       193470                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       193470                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     13747428                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      13747428                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     14436550                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     14436550                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110052955500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 110052955500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 170225463786                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 170225463786                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  91498155223                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  91498155223                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3890581500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3890581500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5535454500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   5535454500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      8571500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      8571500                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 280278419286                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 280278419286                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 280278419286                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 280278419286                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     84911513                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     84911513                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     73174291                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     73174291                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       899007                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       899007                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1075713                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1075713                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2002276                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2002276                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1967058                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1967058                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    158085804                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    158085804                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    158984811                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    158984811                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.076071                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.076071                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.099600                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.099600                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766537                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766537                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.759535                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.759535                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.122475                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.122475                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.098355                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.098355                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086962                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.086962                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.090805                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.090805                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17037.949640                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17037.949640                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23356.490183                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 23356.490183                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111987.089064                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111987.089064                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15865.160177                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15865.160177                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28611.435882                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28611.435882                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   477.387062                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.932397                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.932397                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          391                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        341097294                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       341097294                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     79771007                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       79771007                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     67422867                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      67422867                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       213459                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       213459                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       258123                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       258123                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1760749                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1760749                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1785447                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1785447                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    147193874                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       147193874                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    147407333                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      147407333                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6628879                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      6628879                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      7648651                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      7648651                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       727328                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       727328                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       823977                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       823977                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       249122                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       249122                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       189214                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       189214                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     14277530                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      14277530                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     15004858                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     15004858                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 114348877500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 114348877500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 176760598457                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 176760598457                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  91829921579                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  91829921579                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   3934102000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   3934102000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5393439500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   5393439500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      4601000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      4601000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 291109475957                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 291109475957                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 291109475957                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 291109475957                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     86399886                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     86399886                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     75071518                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     75071518                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       940787                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       940787                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1082100                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1082100                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2009871                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      2009871                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1974661                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1974661                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    161471404                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    161471404                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    162412191                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    162412191                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.076723                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.076723                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.101885                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.101885                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.773106                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.773106                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.761461                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.761461                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.123949                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.123949                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.095821                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.095821                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.088421                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.088421                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.092388                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.092388                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17250.107824                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17250.107824                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23110.035803                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 23110.035803                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111447.190369                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111447.190369                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15791.869044                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15791.869044                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28504.442060                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28504.442060                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.698651                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 20387.698651                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19414.501338                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 19414.501338                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     28857818                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets     25701299                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           757026                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets         713337                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    38.119983                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    36.029673                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20389.344372                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 20389.344372                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19401.015055                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 19401.015055                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     28956080                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets     26869955                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           763930                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets         756063                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    37.904101                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    35.539307                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      5882015                       # number of writebacks
-system.cpu0.dcache.writebacks::total          5882015                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3286907                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      3286907                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5842010                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      5842010                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4476                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         4476                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       122858                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       122858                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      9128917                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      9128917                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      9128917                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      9128917                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3172377                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3172377                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1446134                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1446134                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       682277                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       682277                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       812566                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       812566                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       122370                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       122370                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       193461                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       193461                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4618511                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4618511                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5300788                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5300788                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32879                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32879                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        32981                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        32981                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        65860                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        65860                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  49995905500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  49995905500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39710234771                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  39710234771                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  17655223500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17655223500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  90433652723                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  90433652723                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1780369000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1780369000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5342108500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5342108500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      8456500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      8456500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  89706140271                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  89706140271                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 107361363771                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 107361363771                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6303225000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6303225000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   6238855500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6238855500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12542080500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12542080500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037361                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037361                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019763                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019763                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.758923                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.758923                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.755374                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.755374                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061115                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061115                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.098350                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.098350                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029215                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029215                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.033341                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.033341                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15759.761687                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15759.761687                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27459.581734                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27459.581734                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25876.914362                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25876.914362                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 111293.916707                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 111293.916707                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14549.064313                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14549.064313                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27613.361349                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27613.361349                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      6037757                       # number of writebacks
+system.cpu0.dcache.writebacks::total          6037757                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3397304                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      3397304                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6149640                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      6149640                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4348                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         4348                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       126499                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       126499                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      9546944                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      9546944                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      9546944                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      9546944                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3231575                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3231575                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1499011                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1499011                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       720499                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       720499                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       819629                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       819629                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       122623                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       122623                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       189214                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       189214                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4730586                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4730586                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      5451085                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      5451085                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        32157                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        32157                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        31964                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        31964                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        64121                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        64121                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  51760022500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  51760022500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  40775562681                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  40775562681                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  18675421500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  18675421500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  90765682079                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  90765682079                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1771728000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1771728000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5204285500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5204285500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      4541000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      4541000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  92535585181                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  92535585181                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111211006681                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 111211006681                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6175664000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6175664000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   6047364000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6047364000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12223028000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12223028000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.037403                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.037403                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019968                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019968                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.765847                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.765847                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.757443                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.757443                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061010                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.061010                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.095821                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.095821                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029297                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.029297                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.033563                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.033563                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16016.964638                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16016.964638                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27201.643404                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27201.643404                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25920.121333                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25920.121333                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 110739.959273                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 110739.959273                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14448.578162                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14448.578162                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27504.759162                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27504.759162                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19423.173458                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19423.173458                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20253.849762                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20253.849762                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191709.753946                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191709.753946                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189165.140535                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189165.140535                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190435.476769                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190435.476769                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19561.125235                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19561.125235                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20401.627691                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20401.627691                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192047.268091                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192047.268091                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189192.967088                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189192.967088                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190624.413219                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190624.413219                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          6005225                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.936915                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          202641946                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          6005737                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            33.741395                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          5991449                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.937020                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          207384617                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          5991961                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            34.610475                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      21603135000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.936915                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.937020                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999877                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999877                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           70                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        424004104                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       424004104                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    202641946                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      202641946                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    202641946                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       202641946                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    202641946                       # number of overall hits
-system.cpu0.icache.overall_hits::total      202641946                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6357218                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      6357218                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6357218                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       6357218                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6357218                       # number of overall misses
-system.cpu0.icache.overall_misses::total      6357218                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  72002088632                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  72002088632                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  72002088632                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  72002088632                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  72002088632                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  72002088632                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    208999164                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    208999164                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    208999164                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    208999164                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    208999164                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    208999164                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.030417                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.030417                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.030417                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.030417                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.030417                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.030417                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11326.037369                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 11326.037369                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11326.037369                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 11326.037369                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11326.037369                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 11326.037369                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs     11168048                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets         1595                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs           759109                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets             14                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.712048                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets   113.928571                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.tag_accesses        433456796                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       433456796                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    207384617                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      207384617                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    207384617                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       207384617                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    207384617                       # number of overall hits
+system.cpu0.icache.overall_hits::total      207384617                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6347783                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      6347783                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6347783                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       6347783                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6347783                       # number of overall misses
+system.cpu0.icache.overall_misses::total      6347783                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  72771579605                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  72771579605                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  72771579605                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  72771579605                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  72771579605                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  72771579605                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    213732400                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    213732400                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    213732400                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    213732400                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    213732400                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    213732400                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029700                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.029700                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029700                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.029700                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029700                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.029700                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11464.093780                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 11464.093780                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11464.093780                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 11464.093780                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11464.093780                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 11464.093780                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs     11432767                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets         1960                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs           763504                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets             16                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.974076                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets   122.500000                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      6005225                       # number of writebacks
-system.cpu0.icache.writebacks::total          6005225                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       351442                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       351442                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       351442                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       351442                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       351442                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       351442                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6005776                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      6005776                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6005776                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      6005776                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6005776                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      6005776                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      5991449                       # number of writebacks
+system.cpu0.icache.writebacks::total          5991449                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       355787                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       355787                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst       355787                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       355787                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst       355787                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       355787                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5991996                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      5991996                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      5991996                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      5991996                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      5991996                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      5991996                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  64732998531                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  64732998531                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  64732998531                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  64732998531                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  64732998531                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  64732998531                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  65359568752                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  65359568752                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  65359568752                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  65359568752                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  65359568752                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  65359568752                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2939780998                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2939780998                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2939780998                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   2939780998                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028736                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028736                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028736                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.028736                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028736                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.028736                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10778.457027                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10778.457027                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10778.457027                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10778.457027                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10778.457027                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10778.457027                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.028035                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.028035                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.028035                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.028035                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.028035                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.028035                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10907.812481                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10907.812481                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10907.812481                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10907.812481                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10907.812481                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10907.812481                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7993443                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      8002831                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit         8432                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      8312308                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      8321741                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit         8453                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1016241                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2612055                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       15872.009303                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          17309640                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2628171                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.586192                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage      1049931                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2736768                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       15876.012159                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          17362528                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2752871                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.307062                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle      3536776000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14904.546668                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    64.900343                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    63.931766                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   838.630526                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.909701                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003961                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003902                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.051186                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.968751                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1148                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           72                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14896                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           19                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          168                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          583                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          378                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14917.842100                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    70.317341                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    59.112590                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   828.740128                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.910513                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.004292                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.003608                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.050582                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.968995                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1213                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           79                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14811                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          186                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          670                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          342                       # Occupied blocks per task id
 system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           39                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           20                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           12                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1338                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5968                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4418                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3068                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.070068                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004395                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.909180                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       407586755                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      407586755                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       586295                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       178487                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        764782                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      3871957                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      3871957                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      8013001                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      8013001                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          532                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total          532                       # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            1                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       876856                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       876856                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5449817                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      5449817                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2990512                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2990512                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       195363                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       195363                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       586295                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       178487                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      5449817                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3867368                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total       10081967                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       586295                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       178487                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      5449817                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3867368                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total      10081967                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        11719                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8497                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        20216                       # number of ReadReq misses
-system.cpu0.l2cache.WritebackDirty_misses::writebacks            2                       # number of WritebackDirty misses
-system.cpu0.l2cache.WritebackDirty_misses::total            2                       # number of WritebackDirty misses
-system.cpu0.l2cache.WritebackClean_misses::writebacks            2                       # number of WritebackClean misses
-system.cpu0.l2cache.WritebackClean_misses::total            2                       # number of WritebackClean misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       253056                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       253056                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       193456                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       193456                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           47                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           15                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           16                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1270                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5895                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4592                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2939                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.074036                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004822                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.903992                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       412851946                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      412851946                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       601484                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       195644                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        797128                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      3986432                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      3986432                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      8040621                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      8040621                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          576                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total          576                       # number of UpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            2                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       912887                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       912887                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5408697                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      5408697                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3048347                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      3048347                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       196930                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       196930                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       601484                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       195644                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      5408697                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3961234                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total       10167059                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       601484                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       195644                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      5408697                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3961234                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total      10167059                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        12249                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         9259                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        21508                       # number of ReadReq misses
+system.cpu0.l2cache.WritebackDirty_misses::writebacks            1                       # number of WritebackDirty misses
+system.cpu0.l2cache.WritebackDirty_misses::total            1                       # number of WritebackDirty misses
+system.cpu0.l2cache.WritebackClean_misses::writebacks            3                       # number of WritebackClean misses
+system.cpu0.l2cache.WritebackClean_misses::total            3                       # number of WritebackClean misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       258491                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       258491                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       189208                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       189208                       # number of SCUpgradeReq misses
 system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            4                       # number of SCUpgradeFailReq misses
 system.cpu0.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       324941                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       324941                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       555934                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       555934                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       984475                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       984475                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       615167                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       615167                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        11719                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8497                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       555934                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1309416                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1885566                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        11719                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8497                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       555934                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1309416                       # number of overall misses
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-system.cpu0.l2cache.UpgradeReq_miss_latency::total   3400771000                       # number of UpgradeReq miss cycles
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-system.cpu0.l2cache.InvalidateReq_miss_latency::total  86915383999                       # number of InvalidateReq miss cycles
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-system.cpu0.l2cache.WritebackDirty_accesses::total      3871959                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      8013003                       # number of WritebackClean accesses(hits+misses)
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 system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
 system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
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-system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
-system.cpu0.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
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 system.cpu0.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
 system.cpu0.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.997902                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.997902                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999995                       # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999995                       # miss rate for SCUpgradeReq accesses
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 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
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-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.758969                       # miss rate for InvalidateReq accesses
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-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 55040.131811                       # average ReadReq miss latency
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-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13438.808011                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10814.810603                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10814.810603                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 2070874.750000                       # average SCUpgradeFailReq miss latency
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-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40813.177460                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44209.839733                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44209.839733                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 141287.461777                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 141287.461777                       # average InvalidateReq miss latency
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-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 55040.131811                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40813.177460                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50069.939172                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 47351.414360                       # average overall miss latency
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-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 55040.131811                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40813.177460                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50069.939172                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 47351.414360                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs         3549                       # number of cycles access was blocked
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+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.759196                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.019958                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.045187                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.097343                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.255667                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.161996                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.019958                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.045187                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.097343                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.255667                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.161996                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48939.831823                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 54920.293768                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 51514.366747                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13699.415067                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13699.415067                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10658.666653                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10658.666653                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data      1112750                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1112750                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66791.211482                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66791.211482                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40459.230485                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40459.230485                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44684.186295                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44684.186295                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 140485.676574                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 140485.676574                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48939.831823                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 54920.293768                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40459.230485                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50151.484007                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 47290.005780                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48939.831823                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 54920.293768                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40459.230485                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50151.484007                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 47290.005780                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs         2951                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs              15                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs              31                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs   236.600000                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    95.193548                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1633377                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1633377                       # number of writebacks
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            5                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          190                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_hits::total          195                       # number of ReadReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        59160                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total        59160                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            2                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         6628                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         6628                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data           15                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.InvalidateReq_mshr_hits::total           15                       # number of InvalidateReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            5                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          190                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data        65788                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total        65985                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker            5                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          190                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            2                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data        65788                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total        65985                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        11714                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8307                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        20021                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            2                       # number of WritebackDirty MSHR misses
-system.cpu0.l2cache.WritebackDirty_mshr_misses::total            2                       # number of WritebackDirty MSHR misses
-system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            2                       # number of WritebackClean MSHR misses
-system.cpu0.l2cache.WritebackClean_mshr_misses::total            2                       # number of WritebackClean MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       825638                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       825638                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       253056                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       253056                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       193456                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       193456                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.writebacks::writebacks      1713705                       # number of writebacks
+system.cpu0.l2cache.writebacks::total         1713705                       # number of writebacks
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker            4                       # number of ReadReq MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          178                       # number of ReadReq MSHR hits
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+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        63480                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total        63480                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         6383                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         6383                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            5                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.InvalidateReq_mshr_hits::total            5                       # number of InvalidateReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          178                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.demand_mshr_hits::cpu0.data        69863                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total        70046                       # number of demand (read+write) MSHR hits
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+system.cpu0.l2cache.overall_mshr_hits::cpu0.data        69863                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total        70046                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        12245                       # number of ReadReq MSHR misses
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+system.cpu0.l2cache.ReadReq_mshr_misses::total        21326                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks            1                       # number of WritebackDirty MSHR misses
+system.cpu0.l2cache.WritebackDirty_mshr_misses::total            1                       # number of WritebackDirty MSHR misses
+system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks            3                       # number of WritebackClean MSHR misses
+system.cpu0.l2cache.WritebackClean_mshr_misses::total            3                       # number of WritebackClean MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       867285                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       867285                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       258491                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total       258491                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       189208                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       189208                       # number of SCUpgradeReq MSHR misses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeFailReq MSHR misses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       265781                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       265781                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       555932                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       555932                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       977847                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       977847                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       615152                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       615152                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        11714                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8307                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       555932                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1243628                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1819581                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        11714                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker         8307                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       555932                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1243628                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       825638                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total      2645219                       # number of overall MSHR misses
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+system.cpu0.l2cache.ReadExReq_mshr_misses::total       273016                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       583278                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       583278                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1017743                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1017743                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       620867                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.InvalidateReq_mshr_misses::total       620867                       # number of InvalidateReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        12245                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1290759                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::total      2762648                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32879                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        54172                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        32981                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        32981                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        32157                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        53450                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        31964                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        31964                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        65860                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        87153                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    494096500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    408146000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    902242500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  60235996440                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  60235996440                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7625664494                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7625664494                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3888505997                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3888505997                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      7593499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      7593499                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  16722004500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  16722004500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  19353809498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  19353809498                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  37185118471                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  37185118471                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  83223435999                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  83223435999                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    494096500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    408146000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  19353809498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  53907122971                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total  74163174969                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    494096500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    408146000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  19353809498                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  53907122971                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  60235996440                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total 134399171409                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        64121                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        85414                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    525913500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    445082000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total    970995500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  62672299402                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  62672299402                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7863725997                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7863725997                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3782122004                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3782122004                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      4091000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      4091000                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  17017630999                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  17017630999                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  20099332998                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  20099332998                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  39175352474                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  39175352474                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  83498176486                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  83498176486                       # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    525913500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    445082000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  20099332998                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  56192983473                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total  77263311971                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    525913500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    445082000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  20099332998                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  56192983473                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  62672299402                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 139935611373                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780082500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6040017000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8820099500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5985704467                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5985704467                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   5918259500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8698342000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5801825967                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5801825967                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   2780082500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  12025721467                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  14805803967                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.019588                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.044426                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.025505                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
-system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11720085467                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  14500167967                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.019952                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.044319                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.026051                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackDirty accesses
+system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackDirty accesses
 system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.997902                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.997902                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999995                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999995                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.997777                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.997777                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999989                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999989                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.221153                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.221153                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.092567                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.092567                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.246000                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.246000                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.758950                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.758950                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.019588                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.044426                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.092567                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240232                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.152043                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.019588                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.044426                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.092567                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240232                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.218521                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.218521                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.097343                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.097343                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.249908                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249908                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.759190                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.759190                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.019952                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.044319                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.097343                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.242539                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.156222                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.019952                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.044319                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.097343                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.242539                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.221033                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 45064.806953                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 72956.909009                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30134.296338                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30134.296338                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20100.208818                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20100.208818                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1898374.750000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1898374.750000                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62916.478228                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62916.478228                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34813.267626                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34813.267626                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38027.542623                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38027.542623                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 135289.222825                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 135289.222825                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34813.267626                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43346.662323                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40758.380621                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34813.267626                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43346.662323                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50808.334361                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.227707                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 45531.065366                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72262.635007                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 72262.635007                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30421.662638                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30421.662638                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19989.228806                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19989.228806                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data      1022750                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1022750                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62331.991528                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62331.991528                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34459.268133                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34459.268133                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38492.382138                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38492.382138                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 134486.414137                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 134486.414137                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34459.268133                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43534.837621                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40764.387598                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34459.268133                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43534.837621                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72262.635007                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50652.711230                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183704.400985                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162816.574983                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181489.477790                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181489.477790                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184042.650123                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162737.923293                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181511.261638                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181511.261638                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182595.224218                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169882.895219                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182780.765537                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169763.363933                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests     24664078                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12671171                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2283                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops      2001831                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2001348                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          483                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        921539                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp     11008242                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        32982                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        32981                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      5510686                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      8013020                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      2592060                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq      1056695                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp            3                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       478539                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       354281                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       520874                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq          100                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          211                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1281558                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1212477                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6005776                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4986753                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       818816                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       810530                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18057865                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19072336                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       391759                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1260604                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         38782564                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    768948880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    715383853                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1495872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4784112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1490612717                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    7046224                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     20167865                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.116092                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.320411                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests     24968942                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12837433                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         2144                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops      2067889                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      2067431                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          458                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        957998                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp     11124580                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        31965                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        31964                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      5704814                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      8040643                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2700571                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq      1106688                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp            8                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       482477                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       344108                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       518232                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           45                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          101                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1334424                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1260303                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5991996                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5072927                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       824948                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       817802                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18016682                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19524167                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       428300                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1294882                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         39264031                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    767195088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    734396467                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1639224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      4909864                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1508140643                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    7265658                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     20566582                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.118168                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.322876                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          17827011     88.39%     88.39% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2340371     11.60%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               483      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          18136730     88.19%     88.19% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           2429394     11.81%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2               458      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      20167865                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   24544733928                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      20566582                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   24844807916                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    212322671                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    204855996                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   9035902540                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   9015512485                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8451585698                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   8672428624                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    205222100                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    223891503                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    663162345                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    681731807                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu1.branchPred.lookups              136771271                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         91615454                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          6699408                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            96252672                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               62838118                       # Number of BTB hits
+system.cpu1.branchPred.lookups              134041815                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         89707660                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          6609017                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            94187638                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               61197396                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            65.284544                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               18248077                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            178326                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            64.973915                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               17950728                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            175820                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1729,87 +1718,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   587464                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               587464                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        12287                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        93954                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       273243                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       314221                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2460.273184                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 14941.067276                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       311748     99.21%     99.21% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1254      0.40%     99.61% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          917      0.29%     99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143          161      0.05%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679           52      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215           63      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751           18      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                   567287                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               567287                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11327                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        89325                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       259417                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       307870                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2446.318251                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 14947.483095                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535       305492     99.23%     99.23% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071         1236      0.40%     99.63% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607          840      0.27%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143          161      0.05%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679           48      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215           59      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751           20      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       314221                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       302969                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 20764.791117                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17394.458301                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 22544.227052                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       299168     98.75%     98.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          939      0.31%     99.06% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1914      0.63%     99.69% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          156      0.05%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          510      0.17%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215          121      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751          110      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287           28      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            7      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       302969                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 477883045620                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.598615                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.553378                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 476579478620     99.73%     99.73% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3    689019500      0.14%     99.87% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5    279828500      0.06%     99.93% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7    139297000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9     94668000      0.02%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11     55014500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13     17997000      0.00%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15     27375000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17       352000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19        15500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 477883045620                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        93955     88.43%     88.43% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        12287     11.57%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       106242                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       587464                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::589824-655359            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       307870                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       284687                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 20644.869629                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17424.592515                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 21452.651975                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       281397     98.84%     98.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071          951      0.33%     99.18% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1579      0.55%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          108      0.04%     99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          394      0.14%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215          106      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751          102      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           31      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       284687                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 488633591384                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.617867                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.545160                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 487382306384     99.74%     99.74% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3    662548500      0.14%     99.88% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5    271218500      0.06%     99.94% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7    131442000      0.03%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9     92501000      0.02%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11     52739500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13     15718500      0.00%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15     24644000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17       457500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19         9000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-21         1000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::22-23         1500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-25         1500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::26-27         2500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 488633591384                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        89326     88.75%     88.75% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        11327     11.25%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       100653                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       567287                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       587464                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       106242                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       567287                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       100653                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       106242                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       693706                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       100653                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       667940                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   101377575                       # DTB read hits
-system.cpu1.dtb.read_misses                    401827                       # DTB read misses
-system.cpu1.dtb.write_hits                   83690670                       # DTB write hits
-system.cpu1.dtb.write_misses                   185637                       # DTB write misses
+system.cpu1.dtb.read_hits                    99577859                       # DTB read hits
+system.cpu1.dtb.read_misses                    392921                       # DTB read misses
+system.cpu1.dtb.write_hits                   81911984                       # DTB write hits
+system.cpu1.dtb.write_misses                   174366                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              44695                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid              44673                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   39959                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      225                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  6406                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                   37295                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      442                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  6095                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    43965                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               101779402                       # DTB read accesses
-system.cpu1.dtb.write_accesses               83876307                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    38665                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                99970780                       # DTB read accesses
+system.cpu1.dtb.write_accesses               82086350                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        185068245                       # DTB hits
-system.cpu1.dtb.misses                         587464                       # DTB misses
-system.cpu1.dtb.accesses                    185655709                       # DTB accesses
+system.cpu1.dtb.hits                        181489843                       # DTB hits
+system.cpu1.dtb.misses                         567287                       # DTB misses
+system.cpu1.dtb.accesses                    182057130                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1839,1165 +1831,1167 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    92227                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                92227                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          973                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        66704                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        11080                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        81147                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1613.670253                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 12323.334174                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        80305     98.96%     98.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          403      0.50%     99.46% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303           31      0.04%     99.50% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071           81      0.10%     99.60% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839          234      0.29%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607           59      0.07%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679            7      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        81147                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        78757                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26873.185876                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 22946.544582                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 27397.779974                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        76775     97.48%     97.48% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071          153      0.19%     97.68% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607         1519      1.93%     99.61% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143          117      0.15%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679          110      0.14%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           35      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           36      0.05%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    85422                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                85422                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          706                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        60440                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        10533                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        74889                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1637.737184                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 12543.180008                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-65535        74488     99.46%     99.46% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-131071           92      0.12%     99.59% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-196607          279      0.37%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-262143           10      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-327679           13      0.02%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-393215            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        74889                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        71679                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26447.767128                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 22834.132885                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 26054.956905                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        70042     97.72%     97.72% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071          124      0.17%     97.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607         1290      1.80%     99.69% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           62      0.09%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           94      0.13%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           24      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           27      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        78757                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 434901307160                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.857521                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.349757                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    61992873300     14.25%     14.25% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   372883353360     85.74%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       22166000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        2474500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         253500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5         186500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 434901307160                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        66704     98.56%     98.56% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          973      1.44%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        67677                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        71679                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 419883309648                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     0.857166                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev     0.350104                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    59999474576     14.29%     14.29% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   359861735072     85.71%     99.99% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       18604000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        3422000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4          61500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5          12500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 419883309648                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        60440     98.85%     98.85% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          706      1.15%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        61146                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        92227                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        92227                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        85422                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        85422                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        67677                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        67677                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       159904                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   215454990                       # ITB inst hits
-system.cpu1.itb.inst_misses                     92227                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        61146                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        61146                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       146568                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   210903230                       # ITB inst hits
+system.cpu1.itb.inst_misses                     85422                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              44695                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid              44673                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                   1067                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   28858                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                   26936                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   231246                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   219212                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               215547217                       # ITB inst accesses
-system.cpu1.itb.hits                        215454990                       # DTB hits
-system.cpu1.itb.misses                          92227                       # DTB misses
-system.cpu1.itb.accesses                    215547217                       # DTB accesses
-system.cpu1.numCycles                       759155378                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               210988652                       # ITB inst accesses
+system.cpu1.itb.hits                        210903230                       # DTB hits
+system.cpu1.itb.misses                          85422                       # DTB misses
+system.cpu1.itb.accesses                    210988652                       # DTB accesses
+system.cpu1.numCycles                       739589068                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          87128814                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     606063748                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  136771271                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          81086195                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    630037393                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               14425462                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2172177                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles              325931                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles      6736887                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       827556                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles       851702                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                215200214                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              1679756                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  31517                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         735293191                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.969104                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.218230                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          87179307                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     594353675                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  134041815                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          79148124                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    611930141                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               14224484                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   1980961                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles              327085                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles      6413771                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       794469                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles       836341                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                210662459                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              1674863                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  29397                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         716574317                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.975535                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            1.220237                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               394185812     53.61%     53.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1               132782093     18.06%     71.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                45182528      6.14%     77.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3               163142758     22.19%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               382171132     53.33%     53.33% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1               130053591     18.15%     71.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                44058900      6.15%     77.63% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3               160290694     22.37%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           735293191                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.180162                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.798340                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               105275670                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            361149345                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                225652352                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             38094367                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5121457                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            19322389                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              2132865                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             630175710                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts             23074598                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5121457                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               140790232                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               54705867                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     237824642                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                227778492                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             69072501                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             613335461                       # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts              5878562                       # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents             11068691                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                265258                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents                344448                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              33464644                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents           12708                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          582683755                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            946463821                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       725287459                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           802163                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            525337621                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                57346134                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          16349116                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      14383675                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 76724538                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads           101292205                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           87094038                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          9603338                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         8276902                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 590341476                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           16600780                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                596033149                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued          2703684                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       54441407                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     34942140                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        296921                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    735293191                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.810606                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.063717                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           716574317                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.181238                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.803627                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               104297157                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            348522347                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                221906314                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             36809016                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5039483                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            18926425                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              2113724                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             618028101                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts             22771231                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5039483                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               138949493                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               52143991                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     230343934                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                223632177                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             66465239                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             601445820                       # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts              5788119                       # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents             10817316                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                260401                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents                332552                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              31997393                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents           11898                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          571172784                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            925552885                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       711516112                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           817303                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            514566329                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                56606455                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          15686724                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      13790746                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 74346046                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            99668213                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           85253354                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          9496006                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         8106709                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 579162522                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           15985308                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                584188542                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued          2667167                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       53686437                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     34500302                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        290258                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    716574317                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.815252                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.066417                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          408888874     55.61%     55.61% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          138685440     18.86%     74.47% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2          113812160     15.48%     89.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           65908523      8.96%     98.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            7993150      1.09%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               5044      0.00%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          397414827     55.46%     55.46% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1          134713914     18.80%     74.26% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2          111740906     15.59%     89.85% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           64830862      9.05%     98.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            7868810      1.10%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               4998      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      735293191                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      716574317                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu               59894815     43.89%     43.89% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 54223      0.04%     43.93% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                  19415      0.01%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc              13      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead              36698954     26.89%     70.83% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite             39811710     29.17%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu               59065524     44.03%     44.03% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 54166      0.04%     44.07% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                  19277      0.01%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc              22      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.09% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead              36039894     26.87%     70.95% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite             38965641     29.05%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass               40      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            405160238     67.98%     67.98% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1323587      0.22%     68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                73165      0.01%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  6      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         83635      0.01%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           104404803     17.52%     85.74% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           84987627     14.26%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            396970173     67.95%     67.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1317793      0.23%     68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                74565      0.01%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  1      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         84907      0.01%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           102569706     17.56%     85.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           83171310     14.24%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             596033149                       # Type of FU issued
-system.cpu1.iq.rate                          0.785127                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                  136479130                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.228979                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        2065187396                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        660997777                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    578833453                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1354907                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            550149                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       503649                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             731674033                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 838206                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         2717332                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             584188542                       # Type of FU issued
+system.cpu1.iq.rate                          0.789883                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                  134144524                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.229625                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        2020390722                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        648436438                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    567390385                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1372370                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            557189                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       510457                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             717484509                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 848517                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         2681981                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     12501770                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        16793                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       165759                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      5982611                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     12380566                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        16529                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       160745                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      5876169                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      2801463                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      4362378                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      2772484                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      4108210                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5121457                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                6701200                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              2456436                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          607072203                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles               5039483                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                6511130                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles              2319208                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          595271017                       # Number of instructions dispatched to IQ
 system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts            101292205                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            87094038                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          14166456                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 66987                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              2327340                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        165759                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2053658                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2840126                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4893784                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            588333719                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            101371104                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          7124424                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts             99668213                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            85253354                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          13572161                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 64444                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents              2193101                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        160745                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2023154                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2795718                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4818872                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            576621181                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             99570735                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          7012433                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       129947                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   185062017                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               110209905                       # Number of branches executed
-system.cpu1.iew.exec_stores                  83690913                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.774985                       # Inst execution rate
-system.cpu1.iew.wb_sent                     580075402                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    579337102                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                280158358                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                458852190                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.763134                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.610563                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       47675638                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       16303859                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4608134                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    726275789                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.760731                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.562013                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       123187                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   181482515                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               107903719                       # Number of branches executed
+system.cpu1.iew.exec_stores                  81911780                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.779651                       # Inst execution rate
+system.cpu1.iew.wb_sent                     568628901                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    567900842                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                274880956                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                450165977                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.767860                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.610621                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       47031076                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       15695050                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4536258                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    707685383                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.765116                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.566861                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    483439526     66.56%     66.56% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1    126884990     17.47%     84.03% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     53284484      7.34%     91.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     17968651      2.47%     93.85% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     12727519      1.75%     95.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      8624800      1.19%     96.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      6048440      0.83%     97.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3562811      0.49%     98.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     13734568      1.89%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    470367960     66.47%     66.47% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1    123401303     17.44%     83.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     52359305      7.40%     91.30% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     17652538      2.49%     93.80% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     12497517      1.77%     95.56% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      8502383      1.20%     96.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      5935480      0.84%     97.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3482174      0.49%     98.09% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     13486723      1.91%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    726275789                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           468737677                       # Number of instructions committed
-system.cpu1.commit.committedOps             552500848                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    707685383                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           459224264                       # Number of instructions committed
+system.cpu1.commit.committedOps             541461392                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     169901862                       # Number of memory references committed
-system.cpu1.commit.loads                     88790435                       # Number of loads committed
-system.cpu1.commit.membars                    3923548                       # Number of memory barriers committed
-system.cpu1.commit.branches                 104577420                       # Number of branches committed
-system.cpu1.commit.fp_insts                    490317                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                507351840                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13608772                       # Number of function calls committed.
+system.cpu1.commit.refs                     166664832                       # Number of memory references committed
+system.cpu1.commit.loads                     87287647                       # Number of loads committed
+system.cpu1.commit.membars                    3905531                       # Number of memory barriers committed
+system.cpu1.commit.branches                 102374979                       # Number of branches committed
+system.cpu1.commit.fp_insts                    497703                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                497469676                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13371734                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       381394130     69.03%     69.03% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1072293      0.19%     69.22% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           58068      0.01%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        74453      0.01%     69.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.25% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       88790435     16.07%     85.32% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      81111427     14.68%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       373594883     69.00%     69.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1066183      0.20%     69.19% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           59540      0.01%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        75912      0.01%     69.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.22% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       87287647     16.12%     85.34% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      79377185     14.66%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        552500848                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             13734568                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1308834452                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1209328543                       # The number of ROB writes
-system.cpu1.timesIdled                         978867                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       23862187                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 93869849108                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  468737677                       # Number of Instructions Simulated
-system.cpu1.committedOps                    552500848                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.619574                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.619574                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.617446                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.617446                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               695521161                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              411377637                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   787723                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  479172                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                125942514                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               126793051                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1299771916                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              16418490                       # number of misc regfile writes
-system.cpu1.dcache.tags.replacements          5616176                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          458.902978                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          158371031                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          5616685                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            28.196531                       # Average number of references to valid blocks.
+system.cpu1.commit.op_class_0::total        541461392                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             13486723                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1278856692                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1185834230                       # The number of ROB writes
+system.cpu1.timesIdled                         958439                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       23014751                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 94048355585                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  459224264                       # Number of Instructions Simulated
+system.cpu1.committedOps                    541461392                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.610518                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.610518                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.620918                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.620918                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               681935687                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              403917801                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   803668                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  473340                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                122826591                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               123738784                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1267794356                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              15807378                       # number of misc regfile writes
+system.cpu1.dcache.tags.replacements          5498905                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          458.394450                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          155608106                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5499414                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            28.295398                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     8486277940000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   458.902978                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.896295                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.896295                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   458.394450                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.895302                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.895302                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          363                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          416                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        352316395                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       352316395                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     82533449                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       82533449                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     71018677                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      71018677                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       182219                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       182219                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data        55748                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total        55748                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1865594                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1865594                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1903770                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1903770                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    153552126                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       153552126                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    153734345                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      153734345                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      6611698                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      6611698                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      7495595                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      7495595                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       706613                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       706613                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       438931                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       438931                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       288457                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       288457                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       203515                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       203515                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data     14107293                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total      14107293                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data     14813906                       # number of overall misses
-system.cpu1.dcache.overall_misses::total     14813906                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 112950117500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 112950117500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 162063724604                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 162063724604                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  18729695563                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  18729695563                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4597585500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   4597585500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5657651000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   5657651000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      7414500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      7414500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 275013842104                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 275013842104                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 275013842104                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 275013842104                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     89145147                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     89145147                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     78514272                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     78514272                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       888832                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       888832                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       494679                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       494679                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2154051                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      2154051                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2107285                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      2107285                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    167659419                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    167659419                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    168548251                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    168548251                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.074168                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.074168                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.095468                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.095468                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.794991                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.794991                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.887305                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.887305                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.133914                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.133914                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.096577                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.096577                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.084143                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.084143                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.087891                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.087891                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17083.375178                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 17083.375178                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21621.195463                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21621.195463                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42671.161442                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42671.161442                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15938.547166                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15938.547166                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27799.675700                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27799.675700                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.tag_accesses        345701865                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       345701865                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     81166944                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       81166944                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     69652711                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      69652711                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       179570                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       179570                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data        55554                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total        55554                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1867218                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1867218                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1906025                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1906025                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    150819655                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       150819655                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    150999225                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      150999225                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      6513815                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      6513815                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      7138740                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      7138740                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       666746                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       666746                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       433208                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       433208                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       280157                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       280157                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       195063                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       195063                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data     13652555                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total      13652555                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data     14319301                       # number of overall misses
+system.cpu1.dcache.overall_misses::total     14319301                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 107790302500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 107790302500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 154935306923                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 154935306923                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  17952138757                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  17952138757                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   4403404000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   4403404000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5419622500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   5419622500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3200000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3200000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 262725609423                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 262725609423                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 262725609423                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 262725609423                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     87680759                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     87680759                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     76791451                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     76791451                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       846316                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       846316                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       488762                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       488762                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2147375                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      2147375                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2101088                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      2101088                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    164472210                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    164472210                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    165318526                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    165318526                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.074290                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.074290                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.092963                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.092963                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.787822                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.787822                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.886337                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.886337                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.130465                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.130465                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.092839                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.092839                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.083008                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.083008                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.086616                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.086616                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16547.952697                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16547.952697                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21703.452839                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21703.452839                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41439.998239                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41439.998239                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15717.629758                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15717.629758                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27783.959541                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27783.959541                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19494.444618                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19494.444618                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18564.573186                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18564.573186                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs      4974164                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets     25867147                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs           359446                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets         756404                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    13.838418                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets    34.197528                       # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19243.695369                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19243.695369                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18347.656036                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18347.656036                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs      4719493                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets     24576154                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs           351674                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets         713575                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    13.420079                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets    34.440884                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      5616192                       # number of writebacks
-system.cpu1.dcache.writebacks::total          5616192                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3382349                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total      3382349                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      6057293                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      6057293                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3337                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total         3337                       # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       147189                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total       147189                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      9439642                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      9439642                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      9439642                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      9439642                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3229349                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      3229349                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1438302                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1438302                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       706535                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       706535                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       435594                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       435594                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       141268                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       141268                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       203504                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       203504                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      4667651                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      4667651                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      5374186                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      5374186                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         5460                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         5460                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         5292                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         5292                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        10752                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        10752                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  50929568500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  50929568500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  34490212579                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  34490212579                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16980659000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16980659000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  18123603563                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  18123603563                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   2072685000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   2072685000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5454243000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5454243000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      7318500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      7318500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  85419781079                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  85419781079                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 102400440079                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 102400440079                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    594704500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    594704500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    661334500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    661334500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1256039000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1256039000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036226                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036226                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018319                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018319                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.794903                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.794903                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.880559                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.880559                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.065582                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.065582                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.096572                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.096572                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027840                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027840                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031885                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.031885                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15770.846849                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15770.846849                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23979.812709                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23979.812709                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24033.712413                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24033.712413                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41606.641880                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41606.641880                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14672.006399                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14672.006399                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26801.650090                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26801.650090                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      5498938                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5498938                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3304670                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total      3304670                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5753104                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      5753104                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3561                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.WriteLineReq_mshr_hits::total         3561                       # number of WriteLineReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       144550                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total       144550                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      9057774                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      9057774                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      9057774                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      9057774                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3209145                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      3209145                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1385636                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1385636                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       666638                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       666638                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       429647                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       429647                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       135607                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       135607                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       195058                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       195058                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4594781                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4594781                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      5261419                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      5261419                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         6299                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         6299                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         6428                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         6428                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        12727                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        12727                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  49159510500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  49159510500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  33253300624                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  33253300624                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  15899737000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  15899737000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  17350623757                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  17350623757                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1958308000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1958308000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5224605500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5224605500                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3159000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3159000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  82412811124                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  82412811124                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  98312548124                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  98312548124                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    727883500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    727883500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    859834500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    859834500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1587718000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1587718000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036600                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036600                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018044                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018044                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.787694                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.787694                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.879052                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.879052                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063150                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.063150                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.092837                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.092837                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027937                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027937                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031826                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.031826                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15318.569432                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15318.569432                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23998.583051                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23998.583051                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23850.631077                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23850.631077                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40383.439794                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40383.439794                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14441.053928                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14441.053928                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26784.881933                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26784.881933                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18300.378730                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18300.378730                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19054.130259                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19054.130259                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108920.238095                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 108920.238095                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124968.726379                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124968.726379                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116819.103423                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116819.103423                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17936.178269                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17936.178269                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18685.557665                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18685.557665                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 115555.405620                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 115555.405620                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133763.923460                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 133763.923460                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124751.944685                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124751.944685                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          5955939                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          501.596349                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          208888584                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          5956451                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            35.069303                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements          5972259                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          501.613786                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          204337040                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5972771                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            34.211431                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle     8525956583000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.596349                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979680                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.979680                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.613786                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979714                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.979714                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0          170                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           97                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          351                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        436342012                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       436342012                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    208888584                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      208888584                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    208888584                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       208888584                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    208888584                       # number of overall hits
-system.cpu1.icache.overall_hits::total      208888584                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      6304191                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      6304191                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      6304191                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       6304191                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      6304191                       # number of overall misses
-system.cpu1.icache.overall_misses::total      6304191                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  70452471315                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  70452471315                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  70452471315                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  70452471315                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  70452471315                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  70452471315                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    215192775                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    215192775                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    215192775                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    215192775                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    215192775                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    215192775                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029296                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.029296                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029296                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.029296                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029296                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.029296                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11175.497588                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 11175.497588                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11175.497588                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 11175.497588                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11175.497588                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 11175.497588                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs     10802796                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          573                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs           747541                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              5                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.451108                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets   114.600000                       # average number of cycles each access was blocked
+system.cpu1.icache.tags.tag_accesses        427283163                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       427283163                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    204337040                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      204337040                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    204337040                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       204337040                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    204337040                       # number of overall hits
+system.cpu1.icache.overall_hits::total      204337040                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      6318152                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      6318152                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      6318152                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       6318152                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      6318152                       # number of overall misses
+system.cpu1.icache.overall_misses::total      6318152                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  69955140831                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  69955140831                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  69955140831                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  69955140831                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  69955140831                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  69955140831                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    210655192                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    210655192                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    210655192                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    210655192                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    210655192                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    210655192                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029993                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.029993                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029993                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.029993                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029993                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.029993                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11072.088932                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 11072.088932                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11072.088932                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 11072.088932                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11072.088932                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 11072.088932                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs     10670268                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets         1157                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs           748022                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets              8                       # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    14.264645                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets   144.625000                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks      5955939                       # number of writebacks
-system.cpu1.icache.writebacks::total          5955939                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       347729                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total       347729                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst       347729                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total       347729                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst       347729                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total       347729                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5956462                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      5956462                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      5956462                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      5956462                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      5956462                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      5956462                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      5972259                       # number of writebacks
+system.cpu1.icache.writebacks::total          5972259                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       345373                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total       345373                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst       345373                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total       345373                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst       345373                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total       345373                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5972779                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5972779                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5972779                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5972779                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5972779                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5972779                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  63484136905                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  63484136905                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  63484136905                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  63484136905                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  63484136905                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  63484136905                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  63045966777                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  63045966777                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  63045966777                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  63045966777                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  63045966777                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  63045966777                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8835998                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      8835998                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      8835998                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total      8835998                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.027680                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.027680                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.027680                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.027680                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.027680                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.027680                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10658.027686                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10658.027686                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10658.027686                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10658.027686                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10658.027686                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10658.027686                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028353                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028353                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028353                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.028353                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028353                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.028353                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10555.549900                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10555.549900                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10555.549900                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10555.549900                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10555.549900                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10555.549900                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 131880.567164                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 131880.567164                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      7807580                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      7812689                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit         4721                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      7501600                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      7506319                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit         4330                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       919623                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         2337918                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13374.571842                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          17269379                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         2353639                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            7.337310                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    10121843878000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12566.070038                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    56.667232                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    65.366082                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data     0.000003                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   686.468486                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.766972                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003459                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.003990                       # Average percentage of cache occupancy
+system.cpu1.l2cache.prefetcher.pfSpanPage       900873                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         2224556                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13365.286062                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          17240330                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         2240308                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            7.695518                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    10278781174500                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12562.638726                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    67.088648                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    68.405438                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data     0.000005                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   667.153246                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.766763                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.004095                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004175                       # Average percentage of cache occupancy
 system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.000000                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.041899                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.816319                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1203                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           84                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14434                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           80                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          187                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          549                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          387                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            3                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           65                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            5                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           11                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          840                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4705                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4934                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3842                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.073425                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005127                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.880981                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       397810098                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      397810098                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       597256                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       208532                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        805788                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      3539726                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      3539726                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      8031138                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      8031138                       # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          945                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total          945                       # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            4                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total            4                       # number of SCUpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       889943                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       889943                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5374664                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      5374664                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3032294                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      3032294                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       189660                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       189660                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       597256                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       208532                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      5374664                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3922237                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total       10102689                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       597256                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       208532                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      5374664                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3922237                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total      10102689                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        12883                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        10252                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        23135                       # number of ReadReq misses
-system.cpu1.l2cache.WritebackDirty_misses::writebacks            5                       # number of WritebackDirty misses
-system.cpu1.l2cache.WritebackDirty_misses::total            5                       # number of WritebackDirty misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       246019                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       246019                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       203494                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       203494                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            6                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            6                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       311077                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       311077                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       581787                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       581787                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1040673                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total      1040673                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       244105                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       244105                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        12883                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker        10252                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       581787                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1351750                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1956672                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        12883                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker        10252                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       581787                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1351750                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1956672                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    705237000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    609311000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total   1314548000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3694717000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   3694717000                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1939092500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1939092500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      7171998                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      7171998                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  16701418499                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  16701418499                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  22000590000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  22000590000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  43617133977                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  43617133977                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  15757180999                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total  15757180999                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    705237000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    609311000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  22000590000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  60318552476                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  83633690476                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    705237000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    609311000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  22000590000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  60318552476                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  83633690476                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       610139                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       218784                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       828923                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3539731                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total      3539731                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks      8031138                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total      8031138                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       246964                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       246964                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       203498                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       203498                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            6                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            6                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1201020                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1201020                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5956451                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      5956451                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4072967                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      4072967                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       433765                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       433765                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       610139                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       218784                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      5956451                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      5273987                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total     12059361                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       610139                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       218784                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      5956451                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      5273987                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total     12059361                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.021115                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.046859                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.027910                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.040720                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.815752                       # Average percentage of cache occupancy
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+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           98                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14365                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           78                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          178                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          616                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          417                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           79                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           14                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          949                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4690                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         4883                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         3797                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.078674                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005981                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.876770                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       393723429                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      393723429                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       587134                       # number of ReadReq hits
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+system.cpu1.l2cache.ReadReq_hits::total        780060                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3457963                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3457963                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      8011825                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      8011825                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          813                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total          813                       # number of UpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            2                       # number of SCUpgradeReq hits
+system.cpu1.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
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+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       191485                       # number of InvalidateReq hits
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+system.cpu1.l2cache.ReadReq_misses::total        21970                       # number of ReadReq misses
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+system.cpu1.l2cache.WritebackDirty_misses::total            4                       # number of WritebackDirty misses
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+system.cpu1.l2cache.InvalidateReq_misses::total       236473                       # number of InvalidateReq misses
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+system.cpu1.l2cache.UpgradeReq_miss_latency::total   3573774499                       # number of UpgradeReq miss cycles
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+system.cpu1.l2cache.InvalidateReq_miss_latency::total  14994721499                       # number of InvalidateReq miss cycles
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+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3457967                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3457967                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.020913                       # miss rate for ReadReq accesses
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+system.cpu1.l2cache.ReadReq_miss_rate::total     0.027393                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks     0.000001                       # miss rate for WritebackDirty accesses
 system.cpu1.l2cache.WritebackDirty_miss_rate::total     0.000001                       # miss rate for WritebackDirty accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.996174                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.996174                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999980                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999980                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.WritebackClean_miss_rate::writebacks     0.000000                       # miss rate for WritebackClean accesses
+system.cpu1.l2cache.WritebackClean_miss_rate::total     0.000000                       # miss rate for WritebackClean accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.996614                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.996614                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999990                       # miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999990                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.259011                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.259011                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.097673                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.097673                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.255507                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.255507                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.562759                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.562759                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.021115                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.046859                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.097673                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.256305                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.162253                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.021115                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.046859                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.097673                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.256305                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.162253                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 54741.675076                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 59433.378853                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 56820.747785                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15018.014869                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15018.014869                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9528.991027                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  9528.991027                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      1195333                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      1195333                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53689.017507                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53689.017507                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37815.540739                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37815.540739                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 41912.429723                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 41912.429723                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 64550.832629                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 64550.832629                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 54741.675076                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 59433.378853                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37815.540739                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 44622.565176                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 42742.825816                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 54741.675076                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 59433.378853                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37815.540739                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 44622.565176                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 42742.825816                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs          758                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.259429                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.259429                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.093564                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.093564                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.250420                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.250420                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.552561                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.552561                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.020913                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.046596                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.093564                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.252435                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.157824                       # miss rate for demand accesses
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+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.046596                       # miss rate for overall accesses
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+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.252435                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.157824                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 51731.002312                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 56396.754693                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 53733.431953                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14936.470019                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14936.470019                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9616.664531                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  9616.664531                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      3096999                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      3096999                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53696.685667                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53696.685667                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38092.287527                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38092.287527                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 40803.600780                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 40803.600780                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 63409.867084                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 63409.867084                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 51731.002312                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 56396.754693                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38092.287527                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43768.113544                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 42200.727925                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 51731.002312                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 56396.754693                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38092.287527                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43768.113544                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 42200.727925                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs         1276                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               6                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               8                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs   126.333333                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs   159.500000                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks      1264789                       # number of writebacks
-system.cpu1.l2cache.writebacks::total         1264789                       # number of writebacks
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker            4                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          169                       # number of ReadReq MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_hits::total          173                       # number of ReadReq MSHR hits
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-system.cpu1.l2cache.ReadExReq_mshr_hits::total        44408                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         5726                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         5726                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            6                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total            6                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          169                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data        50134                       # number of demand (read+write) MSHR hits
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-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        12879                       # number of ReadReq MSHR misses
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-system.cpu1.l2cache.ReadReq_mshr_misses::total        22962                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks            5                       # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.WritebackDirty_mshr_misses::total            5                       # number of WritebackDirty MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       820594                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       820594                       # number of HardPFReq MSHR misses
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-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       246019                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       203494                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       203494                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            6                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            6                       # number of SCUpgradeFailReq MSHR misses
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-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       581787                       # number of ReadCleanReq MSHR misses
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-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       244099                       # number of InvalidateReq MSHR misses
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-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       581787                       # number of overall MSHR misses
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 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         5460                       # number of ReadReq MSHR uncacheable
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 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        10752                       # number of overall MSHR uncacheable misses
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-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    627888000                       # number of ReadReq MSHR miss cycles
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-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  49091164625                       # number of HardPFReq MSHR miss cycles
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-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   7718588995                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3925065997                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3925065997                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      6595998                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      6595998                       # number of SCUpgradeFailReq MSHR miss cycles
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-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  12865032499                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  18509868000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  18509868000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  37054911477                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  37054911477                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  14292006999                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  14292006999                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    627888000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    537691500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  18509868000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  49919943976                       # number of demand (read+write) MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    627888000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    537691500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  18509868000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  49919943976                       # number of overall MSHR miss cycles
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-system.cpu1.l2cache.overall_mshr_miss_latency::total 118686556101                       # number of overall MSHR miss cycles
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 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      8332500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    550904000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    559236500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    621567000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    621567000                       # number of WriteReq MSHR uncacheable cycles
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 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      8332500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1172471000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1180803500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.021108                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.046087                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.027701                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   1488910500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   1497243000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.020908                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.045628                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.027145                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks     0.000001                       # mshr miss rate for WritebackDirty accesses
 system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total     0.000001                       # mshr miss rate for WritebackDirty accesses
+system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks     0.000000                       # mshr miss rate for WritebackClean accesses
+system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total     0.000000                       # mshr miss rate for WritebackClean accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.996174                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.996174                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999980                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999980                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.996614                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.996614                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999990                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999990                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.222035                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.222035                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.097673                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.097673                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.254101                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.254101                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.562745                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.562745                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.021108                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.046087                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.097673                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.246799                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.158082                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.021108                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.046087                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.097673                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.246799                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.222329                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.222329                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.093564                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.093564                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.249012                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249012                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.552554                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.552554                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.020908                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.045628                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.093564                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.243042                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.153745                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.020908                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.045628                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.093564                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.243042                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.226128                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 50761.235955                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59823.938056                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31373.954837                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31373.954837                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19288.362296                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19288.362296                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      1099333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      1099333                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48243.449741                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48243.449741                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31815.540739                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31815.540739                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 35803.680263                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35803.680263                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 58550.043216                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 58550.043216                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31815.540739                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 38352.282068                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 36506.855443                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31815.540739                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 38352.282068                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43523.410547                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.218798                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 47696.316200                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60275.447456                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 60275.447456                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31180.899835                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31180.899835                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19270.223778                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19270.223778                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      2850999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      2850999                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48033.169385                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48033.169385                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32092.287527                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32092.287527                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34717.232569                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34717.232569                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 57409.047655                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 57409.047655                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32092.287527                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37442.533808                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35935.044345                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32092.287527                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37442.533808                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60275.447456                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43171.931250                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100898.168498                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101182.648815                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117454.081633                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117454.081633                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107536.434355                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 107713.556393                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126250.544493                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 126250.544493                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109046.781994                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 109141.648951                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116988.331893                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 117026.965765                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests     24065952                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     12401926                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1256                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops      2060689                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2060329                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          360                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq        934376                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp     11053796                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         5292                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         5292                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      4812576                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      8031153                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      2767424                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq      1034593                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp            2                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       454030                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       361772                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       513435                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq          121                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          211                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1276992                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1207288                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5956462                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      5025648                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       440267                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       433765                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     17868522                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18112795                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       459206                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1298566                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         37739089                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    762364336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    703129592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1750272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4881112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1472125312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    6734851                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     19529823                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.125012                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.330788                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests     23835470                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     12272459                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1390                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops      2000895                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      2000561                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          334                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq        900425                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp     10970003                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         6428                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         6428                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4651207                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      8011843                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      2673516                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       976496                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp            6                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       442024                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       347278                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       498740                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           61                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          101                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1227372                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1161574                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5972779                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4961310                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       435892                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       427958                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     17917345                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17734263                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       424426                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1271663                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         37347697                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    764444720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    688461274                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1618840                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4797400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1459322234                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    6483444                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     19136823                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.123774                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.329377                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          17088727     87.50%     87.50% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           2440736     12.50%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               360      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          16768514     87.62%     87.62% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           2367975     12.37%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2               334      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      19529823                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   23888032965                       # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    176197847                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      19136823                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   23662576976                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    176028266                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   8940771887                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   8965097194                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   8370756543                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   8193842587                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    240887058                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    222514103                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    689185473                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    672743976                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40298                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40298                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136623                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136623                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47620                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40336                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40336                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136625                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136625                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47628                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -3007,18 +3001,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122554                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231208                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231208                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122562                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231280                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231280                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353842                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47640                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353922                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47648                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -3028,24 +3020,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155661                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338848                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7338848                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155669                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339136                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7339136                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7496595                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             36904500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7496891                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             36916001                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               327000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                 9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                 9000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
@@ -3058,79 +3049,73 @@ system.iobus.reqLayer16.occupancy               14000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            24719501                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            24643501                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              169000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36442501                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            36445000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           565518728                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              115000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565389979                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               44500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92662000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92668000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147904000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147976000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115596                       # number of replacements
-system.iocache.tags.tagsinuse               11.294963                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      4                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115612                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000035                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9125681000000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     7.424342                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     3.870620                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.464021                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.241914                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.705935                       # Average percentage of cache occupancy
+system.iocache.tags.replacements               115636                       # number of replacements
+system.iocache.tags.tagsinuse               11.302848                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs               115652                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         9125688591000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     7.411882                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     3.890966                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.463243                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.243185                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.706428                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1040789                       # Number of tag accesses
-system.iocache.tags.data_accesses             1040789                       # Number of data accesses
+system.iocache.tags.tag_accesses              1041117                       # Number of tag accesses
+system.iocache.tags.data_accesses             1041117                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8876                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8913                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8912                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8949                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8876                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8916                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8912                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8952                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8876                       # number of overall misses
-system.iocache.overall_misses::total             8916                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8912                       # number of overall misses
+system.iocache.overall_misses::total             8952                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5200000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1711011512                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1716211512                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1705648493                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1710848493                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13978863467                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13978863467                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13974401235                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13974401235                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5569000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1711011512                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1716580512                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1705648493                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1711217493                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5569000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1711011512                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1716580512                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1705648493                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1711217493                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8876                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8913                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8912                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8949                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8876                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8916                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8912                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8952                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8876                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8916                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8912                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8952                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -3145,54 +3130,54 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 192768.309148                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 192551.499159                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 191387.847060                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 191177.616829                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130976.533496                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130976.533496                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130934.724112                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130934.724112                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       139225                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 192768.309148                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 192528.096904                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 191387.847060                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 191154.769102                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       139225                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 192768.309148                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 192528.096904                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         36708                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 191387.847060                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 191154.769102                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         35975                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3726                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3674                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.851852                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.791780                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106693                       # number of writebacks
-system.iocache.writebacks::total               106693                       # number of writebacks
+system.iocache.writebacks::writebacks          106694                       # number of writebacks
+system.iocache.writebacks::total               106694                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8876                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8913                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8912                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8949                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8876                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8916                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8912                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8952                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8876                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8916                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8912                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8952                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3350000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1267211512                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1270561512                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1260048493                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1263398493                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8642463467                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8642463467                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8638001235                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8638001235                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3569000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1267211512                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1270780512                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1260048493                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1263617493                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3569000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1267211512                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1270780512                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1260048493                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1263617493                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -3207,625 +3192,619 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142768.309148                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 142551.499159                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141387.847060                       # average ReadReq mshr miss latency
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 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80976.533496                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80976.533496                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80934.724112                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80934.724112                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89225                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 142768.309148                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 142528.096904                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 141387.847060                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 141154.769102                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89225                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 142768.309148                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 142528.096904                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 141387.847060                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 141154.769102                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1583129                       # number of replacements
-system.l2c.tags.tagsinuse                63158.639853                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    6207421                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1642739                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     3.778702                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1576044                       # number of replacements
+system.l2c.tags.tagsinuse                63242.380291                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    6232719                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1635533                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     3.810818                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   20395.624897                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    35.797068                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker    37.096794                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3244.022805                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4223.269206                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  3404.413573                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   297.158145                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   465.494648                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3968.740099                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     9359.576527                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17727.446091                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.311213                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000546                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000566                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1.data       0.142816                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1024        49262                       # Occupied blocks per task id
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-system.l2c.tags.age_task_id_blocks_1023::4          205                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
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-system.l2c.WritebackDirty_hits::total         2898173                       # number of WritebackDirty hits
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-system.l2c.WritebackClean_hits::total               1                       # number of WritebackClean hits
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-system.l2c.UpgradeReq_hits::cpu1.data          150342                       # number of UpgradeReq hits
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-system.l2c.ReadSharedReq_hits::cpu0.data       574885                       # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5287                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       532007                       # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_misses::cpu0.data       146627                       # number of ReadSharedReq misses
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-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         3029                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         2795                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        49780                       # number of ReadSharedReq misses
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-system.l2c.overall_misses::cpu1.l2cache.prefetcher       244242                       # number of overall misses
-system.l2c.overall_misses::total              1621875                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    974602500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data   1153364500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total   2127967000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data    208392500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data    213995000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    422387500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  89500490493                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  18793488998                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 108293979491                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    316188000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    293419000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   8381886002                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  21271080498                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  54991951248                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    433939500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    397141000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   6825711500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  19972888998                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  43219182868                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 156103388614                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    316188000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    293419000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   8381886002                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 110771570991                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  54991951248                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    433939500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    397141000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   6825711500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  38766377996                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  43219182868                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    264397368105                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    316188000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    293419000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   8381886002                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 110771570991                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  54991951248                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    433939500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    397141000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   6825711500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  38766377996                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  43219182868                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   264397368105                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      2898173                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      2898173                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       220491                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       214527                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          435018                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        50550                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        56493                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total        107043                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       694970                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       307035                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          1002005                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         7947                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         5690                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       555932                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       721512                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       579198                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        10028                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         8082                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       581787                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       765602                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       570403                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3806181                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         7947                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         5690                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          555932                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1416482                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       579198                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        10028                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         8082                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          581787                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1072637                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       570403                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4808186                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         7947                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         5690                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         555932                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1416482                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       579198                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        10028                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         8082                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         581787                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1072637                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       570403                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4808186                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.272134                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.299193                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.285478                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.264372                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.208344                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.234803                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.778032                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.415275                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.666876                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.278847                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.357118                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.109922                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.203222                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.523324                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.302054                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.345830                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.085564                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.181196                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.428192                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.250556                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.278847                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.357118                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.109922                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.485242                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.523324                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.302054                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.345830                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.085564                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.248200                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.428192                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.337315                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.278847                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.357118                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.109922                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.485242                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.523324                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.302054                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.345830                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.085564                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.248200                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.428192                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.337315                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16242.562872                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17969.377580                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 17135.045254                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15593.572284                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 18181.393373                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 16805.422933                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165524.321757                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147395.289544                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 162065.059331                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142684.115523                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 144399.114173                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137162.872932                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 145069.328964                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143261.637504                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142089.803220                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137117.547208                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143975.728771                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 163688.380804                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142684.115523                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 144399.114173                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 137162.872932                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 161160.729237                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 143261.637504                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142089.803220                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 137117.547208                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 145613.451613                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 163019.571857                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142684.115523                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 144399.114173                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 137162.872932                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 161160.729237                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 143261.637504                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142089.803220                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 137117.547208                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 145613.451613                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 163019.571857                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             10461                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   20333.059620                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    44.017365                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker    59.342117                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3579.623644                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     5086.228075                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  3815.151087                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   296.252046                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   450.100507                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3644.907232                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     8614.023056                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17319.675542                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.310258                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000672                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000905                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.054621                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.077610                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.058215                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.004520                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.006868                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.055617                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.131440                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.264277                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.965002                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022         9601                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          201                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        49687                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2         1158                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          504                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         7939                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            8                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          193                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          374                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2840                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5617                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        40824                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.146500                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.003067                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.758163                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 79314813                       # Number of tag accesses
+system.l2c.tags.data_accesses                79314813                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks      2898844                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2898844                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks            4                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total               4                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data          171467                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          140817                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              312284                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         39034                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         42272                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             81306                       # number of SCUpgradeReq hits
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+system.l2c.UpgradeReq_miss_latency::cpu0.data   1024631500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data   1063145500                       # number of UpgradeReq miss cycles
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+system.l2c.WritebackClean_accesses::writebacks            4                       # number of WritebackClean accesses(hits+misses)
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+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.265707                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.305115                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.284017                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.244625                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.210622                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.227320                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.766583                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.422126                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.667227                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.263099                       # miss rate for ReadSharedReq accesses
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+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.200655                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.512986                       # miss rate for ReadSharedReq accesses
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+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.087915                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.175356                       # miss rate for ReadSharedReq accesses
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+system.l2c.ReadSharedReq_miss_rate::total     0.250036                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.263099                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.442980                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.336396                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.263099                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.328363                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.107181                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.470760                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu1.inst      0.087915                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.245635                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.336396                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16514.062147                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17194.376607                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 16853.629003                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15336.840440                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17270.635695                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 16248.683110                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165212.200118                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147186.219875                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 161922.745925                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143534.255319                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 142763.039568                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137096.871233                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 144739.537079                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 179442.014515                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143303.143713                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141331.441782                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 136685.925097                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143269.788738                       # average ReadSharedReq miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::total 163253.524778                       # average ReadSharedReq miss latency
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+system.l2c.overall_avg_miss_latency::total 162707.130129                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             17532                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                      107                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                      141                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs     97.766355                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs    124.340426                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1242151                       # number of writebacks
-system.l2c.writebacks::total                  1242151                       # number of writebacks
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-system.l2c.CleanEvict_mshr_misses::total        60824                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        60003                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        64185                       # number of UpgradeReq MSHR misses
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-system.l2c.overall_mshr_miss_latency::total 248017540622                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        12725                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        98206                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   4564244502                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   4544780000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   9109024502                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data    967924994                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    862182998                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total   1830107992                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  16651388996                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 101050284993                       # number of ReadExReq MSHR miss cycles
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+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    312437500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   6197673000                       # number of ReadSharedReq MSHR miss cycles
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+system.l2c.ReadSharedReq_mshr_miss_latency::total 146278359902                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    313805500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    295265000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   7922359002                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 105399081495                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.inst   6197673000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data  33523329495                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::total 247328644895                       # number of demand (read+write) MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu0.inst   7922359002                       # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::total 247328644895                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2396808000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5447961500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5339273500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      7124500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    452516500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   8304410500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   5424521033                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    531333000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5955854033                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    563876500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   8307082500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   5257909033                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    701977500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5959886533                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2396808000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10872482533                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10597182533                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      7124500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    983849500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  14260264533                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1265854000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  14266969033                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.272134                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.299193                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.285478                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.264372                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.208344                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.234803                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.778031                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.415275                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.666875                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.278847                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.357118                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.109544                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.202317                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.523301                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.302054                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.345830                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.085145                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.180852                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.428190                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.250193                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.278847                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.357118                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.109544                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.484780                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.523301                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.302054                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.345830                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.085145                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.247954                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.428190                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.337027                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.278847                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.357118                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.109544                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.484780                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.523301                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.302054                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.345830                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.085145                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.247954                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.428190                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.337027                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73513.974368                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73520.246226                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73517.215898                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76539.471865                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76458.666015                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76501.631296                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155524.478079                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137395.289544                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 152065.180648                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127229.273092                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 135142.172565                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127189.983043                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133999.223594                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 153742.669820                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127229.273092                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 151191.633086                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127189.983043                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135627.302450                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 153050.954108                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127229.273092                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 151191.633086                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127189.983043                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135627.302450                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 153050.954108                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.265707                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.305115                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.284017                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.244625                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.210622                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.227320                       # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.422126                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.667226                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.263099                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.328363                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.106805                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.200613                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.512986                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.289962                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.344134                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.087478                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.175312                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.442980                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.249898                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.263099                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.328363                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.106805                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.470737                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.512986                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.289962                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.344134                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.087478                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.245603                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.442980                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.336287                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.263099                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.328363                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.106805                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.470737                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.512986                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.289962                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.344134                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.087478                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.245603                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.442980                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.336287                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73562.268349                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73503.258883                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73532.814824                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76570.286686                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76441.439667                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76509.531438                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155212.364182                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137186.219875                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 151922.875105                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127170.794773                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 134745.272716                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 126778.075523                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133277.041377                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 153279.075099                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127170.794773                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 150652.975558                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126778.075523                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135190.524275                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 152722.061920                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127170.794773                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 150652.975558                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126778.075523                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135190.524275                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 152722.061920                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165697.299188                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166037.674534                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 82908.849395                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139109.343853                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164474.122464                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100403.061224                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155615.029734                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89546.847705                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138881.908918                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164494.713834                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109206.207218                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155237.719655                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165084.763635                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165268.516290                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91520.883721                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 145557.461805                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99477.721022                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 145275.940706                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               59697                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1020888                       # Transaction distribution
-system.membus.trans_dist::WriteReq              38273                       # Transaction distribution
-system.membus.trans_dist::WriteResp             38273                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1348844                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           267564                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           448101                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         314840                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          158230                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            678893                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           659308                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        961191                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        106727                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       106727                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122554                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               59814                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1023090                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38392                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38392                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1345584                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           266165                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           443726                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         302861                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          156448                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            1                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            676664                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           656494                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        963276                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106728                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106728                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122562                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25446                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5713992                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5862068                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342759                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342759                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6204827                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155661                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25910                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5690514                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      5839062                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342298                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342298                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6181360                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155669                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50892                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    182954368                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    183161477                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7272320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7272320                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190433797                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           627031                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4226315                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51820                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    182696832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    182904877                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7257216                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7257216                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190162093                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           613313                       # Total snoops (count)
+system.membus.snoop_fanout::samples           4205672                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 4226315    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 4205672    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             4226315                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            98488499                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4205672                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            98421997                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               53000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            21525971                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21914471                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          9456985184                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          9436458556                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         8888143010                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         8880795227                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228798971                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228859415                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3879,57 +3858,57 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     12205155                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      6621083                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1960564                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         171525                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       155955                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        15570                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              59699                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           4664873                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             38273                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            38273                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      4247047                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1614803                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          750027                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        396749                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1146775                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          211                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          211                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1140836                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1140836                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      4612412                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       106727                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8853195                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7749082                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              16602277                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    269317869                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    224565592                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              493883461                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         3357154                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          8803755                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.347401                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.479844                       # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests     12199905                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      6623903                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1949036                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         168152                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       152817                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        15335                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              59816                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           4662380                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38392                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38392                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      4244441                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean            4                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1619343                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          747362                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        384167                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1131529                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          101                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          101                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1137603                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1137603                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      4609811                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106728                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9241165                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      7356268                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              16597433                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    283441843                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    210970938                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              494412781                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         3322045                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          8775737                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.344900                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.478998                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                5760896     65.44%     65.44% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                3027289     34.39%     99.82% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  15570      0.18%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                5764320     65.68%     65.68% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                2996082     34.14%     99.83% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  15335      0.17%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            8803755                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         9517655622                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8775737                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         9513972562                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2614297                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2693663                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4898920623                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        5075177047                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4389147401                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4195991011                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   12586                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   12889                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    5763                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                    5680                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal
index bbb96f95b..8e5190276 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal
@@ -105,62 +105,62 @@
 [    2.144312] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]

 [    2.144339] pci_bus 0000:00: fixups for bus

 [    2.144347] pci_bus 0000:00: bus scan returning with max=00

-[    2.144359] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc

+[    2.144358] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc

 [    2.144376] pci 0000:00:00.0: fixup irq: got 33

 [    2.144384] pci 0000:00:00.0: assigning IRQ 33

 [    2.144394] pci 0000:00:01.0: fixup irq: got 34

 [    2.144402] pci 0000:00:01.0: assigning IRQ 34

 [    2.144413] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

 [    2.144426] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]

-[    2.144439] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

+[    2.144438] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

 [    2.144451] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

-[    2.144463] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]

-[    2.144474] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]

+[    2.144462] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]

+[    2.144473] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]

 [    2.144485] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

 [    2.144496] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

 [    2.144948] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

-[    2.145138] ata_piix 0000:00:01.0: version 2.13

+[    2.145137] ata_piix 0000:00:01.0: version 2.13

 [    2.145148] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

-[    2.145170] ata_piix 0000:00:01.0: enabling bus mastering

-[    2.145355] scsi0 : ata_piix

-[    2.145414] scsi1 : ata_piix

-[    2.145435] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

-[    2.145447] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

-[    2.145523] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

-[    2.145535] e1000: Copyright (c) 1999-2006 Intel Corporation.

-[    2.145548] e1000 0000:00:00.0: enabling device (0000 -> 0002)

-[    2.145560] e1000 0000:00:00.0: enabling bus mastering

+[    2.145169] ata_piix 0000:00:01.0: enabling bus mastering

+[    2.145354] scsi0 : ata_piix

+[    2.145413] scsi1 : ata_piix

+[    2.145434] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

+[    2.145446] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

+[    2.145522] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

+[    2.145534] e1000: Copyright (c) 1999-2006 Intel Corporation.

+[    2.145547] e1000 0000:00:00.0: enabling device (0000 -> 0002)

+[    2.145559] e1000 0000:00:00.0: enabling bus mastering

 [    2.290704] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66

 [    2.290714] ata1.00: 2096640 sectors, multi 0: LBA 

 [    2.290739] ata1.00: configured for UDMA/33

-[    2.290783] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5

-[    2.290882] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)

-[    2.290916] sd 0:0:0:0: [sda] Write Protect is off

-[    2.290925] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00

-[    2.290941] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA

-[    2.290995] sd 0:0:0:0: Attached scsi generic sg0 type 0

-[    2.291062]  sda: sda1

-[    2.291150] sd 0:0:0:0: [sda] Attached SCSI disk

+[    2.290784] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5

+[    2.290883] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)

+[    2.290917] sd 0:0:0:0: [sda] Write Protect is off

+[    2.290926] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00

+[    2.290943] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA

+[    2.290996] sd 0:0:0:0: Attached scsi generic sg0 type 0

+[    2.291064]  sda: sda1

+[    2.291152] sd 0:0:0:0: [sda] Attached SCSI disk

 [    2.410949] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01

 [    2.410962] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection

 [    2.410980] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k

 [    2.410990] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.

 [    2.411008] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k

 [    2.411020] igb: Copyright (c) 2007-2014 Intel Corporation.

-[    2.411069] usbcore: registered new interface driver usb-storage

-[    2.411117] mousedev: PS/2 mouse device common for all mice

-[    2.411224] usbcore: registered new interface driver usbhid

-[    2.411234] usbhid: USB HID core driver

-[    2.411259] TCP: cubic registered

+[    2.411070] usbcore: registered new interface driver usb-storage

+[    2.411118] mousedev: PS/2 mouse device common for all mice

+[    2.411225] usbcore: registered new interface driver usbhid

+[    2.411235] usbhid: USB HID core driver

+[    2.411260] TCP: cubic registered

 [    2.411267] NET: Registered protocol family 17

-
-[    2.411614] devtmpfs: mounted

-[    2.411651] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)

+
+[    2.411619] devtmpfs: mounted

+[    2.411656] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)

 
 
-[    2.447825] udevd[609]: starting version 182

+[    2.447817] udevd[609]: starting version 182

 Starting Bootlog daemon: bootlogd.


-[    2.512686] random: dd urandom read with 18 bits of entropy available

+[    2.532679] random: dd urandom read with 18 bits of entropy available

 Populating dev cache


 net.ipv4.conf.default.rp_filter = 1


 net.ipv4.conf.all.rp_filter = 1


@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory


 
INIT: Entering runlevel: 5



 Configuring network interfaces... udhcpc (v1.21.1) started


-[    2.620897] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

+[    2.640899] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

 Sending discover...


 Sending discover...


 Sending discover...


diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
index e9e155362..2ab6e4e82 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -749,10 +749,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -779,7 +778,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -906,12 +905,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -1004,16 +1000,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1029,7 +1024,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1192,13 +1187,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1208,9 +1203,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1252,7 +1246,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1333,14 +1327,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1357,7 +1350,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1372,7 +1365,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1495,17 +1488,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1557,7 +1552,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1572,7 +1567,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
index ad9b8b91f..596287bde 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 18:31:16
-gem5 executing on e104799-lin, pid 7932
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 11:54:11
+gem5 executing on e104799-lin, pid 641
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 51331535316000 because m5_exit instruction encountered
+Exiting @ tick 51291805611000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
index 669c357ff..25838a319 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
@@ -1,140 +1,140 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.331535                       # Number of seconds simulated
-sim_ticks                                51331535316000                       # Number of ticks simulated
-final_tick                               51331535316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.291806                       # Number of seconds simulated
+sim_ticks                                51291805611000                       # Number of ticks simulated
+final_tick                               51291805611000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  99693                       # Simulator instruction rate (inst/s)
-host_op_rate                                   117139                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6054269729                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 687132                       # Number of bytes of host memory used
-host_seconds                                  8478.57                       # Real time elapsed on the host
-sim_insts                                   845255961                       # Number of instructions simulated
-sim_ops                                     993175006                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 117828                       # Simulator instruction rate (inst/s)
+host_op_rate                                   138456                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7111926295                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 686644                       # Number of bytes of host memory used
+host_seconds                                  7212.08                       # Real time elapsed on the host
+sim_insts                                   849784302                       # Number of instructions simulated
+sim_ops                                     998554740                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       205184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       203136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           5579360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          71974536                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        439872                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             78402088                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      5579360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5579360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     67218688                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       234176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       229184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           5702880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          74235720                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        438720                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             80840680                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      5702880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5702880                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     69030592                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          67239268                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         3206                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         3174                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             103130                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1124615                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6873                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1240998                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1050292                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          69051172                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         3659                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         3581                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             105060                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1159946                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6855                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1279101                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1078603                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1052865                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           3997                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           3957                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               108693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1402150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8569                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1527367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          108693                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             108693                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1309501                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1081176                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           4566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           4468                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               111185                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1447321                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8553                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1576093                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          111185                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             111185                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1345841                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1309902                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1309501                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          3997                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          3957                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              108693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1402551                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8569                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2837269                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1240998                       # Number of read requests accepted
-system.physmem.writeReqs                      1052865                       # Number of write requests accepted
-system.physmem.readBursts                     1240998                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1052865                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 79374080                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     49792                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  67238272                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  78402088                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               67239268                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      778                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         323831                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               73630                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               80699                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               78276                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               74217                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               73666                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               79970                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               75195                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               74032                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               71713                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              100993                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              77049                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              78387                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              77207                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              77888                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              72930                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              74368                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61890                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               67926                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               67010                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               65080                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               64889                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               68021                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64968                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65143                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               62358                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               69100                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              64674                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              67475                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              66848                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              67005                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              63727                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64484                       # Per bank write bursts
+system.physmem.bw_write::total                1346242                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1345841                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          4566                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          4468                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              111185                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1447722                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8553                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2922335                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1279101                       # Number of read requests accepted
+system.physmem.writeReqs                      1081176                       # Number of write requests accepted
+system.physmem.readBursts                     1279101                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1081176                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 81811968                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     50496                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  69050112                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  80840680                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               69051172                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      789                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2248                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         335568                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               76700                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               81593                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               83146                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               75940                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               76984                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               83084                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               76647                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               76510                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               74528                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              104951                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              78345                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              82619                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              77692                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              79270                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              75132                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              75171                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               64170                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               68321                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               70316                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               66616                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               66722                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               70167                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               65460                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               67223                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               64606                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               72209                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              66721                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              70434                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              67362                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              68403                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              65406                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64772                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          26                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51331533904500                       # Total gap between requests
+system.physmem.numWrRetry                          27                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51291804197000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1219713                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1257816                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1050292                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    631662                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    326376                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    149637                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    126770                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       678                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       576                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       562                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1325                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       777                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       342                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      390                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::12                      165                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      109                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       93                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       76                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1078603                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    653601                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    337199                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    152943                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    128864                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       660                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       562                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       565                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1243                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       728                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       380                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      369                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      207                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      186                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      145                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      141                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      128                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       83                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       65                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -159,163 +159,162 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    11849                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    13848                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    31106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    44112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    54434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    62830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    64146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    65206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    66402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    65786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    66222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    71472                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    66143                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::29                    84167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    64432                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    68381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    61265                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1283                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      540                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      366                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      337                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      265                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      246                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      268                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      220                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      226                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      194                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      101                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::28                    82006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    85825                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    66342                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    70369                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    63013                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1359                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      528                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      460                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      358                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      386                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      314                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      377                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      262                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      209                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      303                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      205                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       98                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       67                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       475699                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      308.203229                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     177.287854                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     336.241632                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         186276     39.16%     39.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       111535     23.45%     62.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        45072      9.47%     72.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        23389      4.92%     77.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18072      3.80%     80.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11535      2.42%     83.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10579      2.22%     85.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8108      1.70%     87.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        61133     12.85%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         475699                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59810                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.735663                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      269.812069                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          59807     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::63                       69                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       496985                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      303.554208                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.944807                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.108749                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         196641     39.57%     39.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       117090     23.56%     63.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        47261      9.51%     72.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        24196      4.87%     77.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        18882      3.80%     81.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11863      2.39%     83.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895        10943      2.20%     85.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8246      1.66%     87.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        61863     12.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         496985                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61535                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.773365                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      265.981989                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047          61532    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59810                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59810                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.565591                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.987331                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.225331                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           56970     95.25%     95.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             839      1.40%     96.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              56      0.09%     96.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             337      0.56%     97.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              42      0.07%     97.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             348      0.58%     97.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             200      0.33%     98.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              22      0.04%     98.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              64      0.11%     98.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             127      0.21%     98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              27      0.05%     98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              38      0.06%     98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             506      0.85%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              29      0.05%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              24      0.04%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             125      0.21%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           61535                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61535                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.533241                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.977663                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.054277                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           58637     95.29%     95.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             877      1.43%     96.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              68      0.11%     96.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             330      0.54%     97.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              47      0.08%     97.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             368      0.60%     98.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             228      0.37%     98.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              20      0.03%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              53      0.09%     98.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             138      0.22%     98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              26      0.04%     98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              33      0.05%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             471      0.77%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              36      0.06%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              24      0.04%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             129      0.21%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.00%     99.92% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::84-87               1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::100-103             2      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.00%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             3      0.00%     99.94% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::128-131            25      0.04%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             5      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59810                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    31819415784                       # Total ticks spent queuing
-system.physmem.totMemAccLat               55073540784                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6201100000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       25656.27                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::132-135             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           61535                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    32791506957                       # Total ticks spent queuing
+system.physmem.totMemAccLat               56759856957                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6391560000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       25652.19                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44406.27                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.55                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.31                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.53                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.31                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44402.19                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.60                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.35                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.58                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.35                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.21                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1019502                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    795615                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.20                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.73                       # Row buffer hit rate for writes
-system.physmem.avgGap                     22377767.94                       # Average gap between requests
-system.physmem.pageHitRate                      79.23                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1796611320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  980293875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4755496200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3401526960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352726044720                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1234173509595                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29716310123250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34314143605920                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.480817                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49435613390416                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1714072620000                       # Time in different power states
+system.physmem.avgWrQLen                        25.36                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1048127                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    812106                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.99                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.27                       # Row buffer hit rate for writes
+system.physmem.avgGap                     21731264.68                       # Average gap between requests
+system.physmem.pageHitRate                      78.92                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1887739560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1030016625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4918711200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3492687600                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3350131371600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1239587078895                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29687726109750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34288773715230                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.503935                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49388003607661                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1712746100000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    181848672584                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    191055633589                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1799673120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  981964500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4918173000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3406348080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352726044720                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1238619690855                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29712409964250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34314861858525                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.494809                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49429083175074                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1714072620000                       # Time in different power states
+system.physmem_1.actEnergy                 1869467040                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1020046500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5052099000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3498636240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3350131371600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1240740741510                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29686714133250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34289026495140                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.508863                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49386297692325                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1712746100000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    188374993676                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    192761562675                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -339,15 +338,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups               223536271                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         149385948                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12169974                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            157736918                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               103109650                       # Number of BTB hits
+system.cpu.branchPred.lookups               224688792                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         150206770                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          12191755                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            158635537                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               103690237                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             65.368115                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                30707782                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             342742                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             65.363814                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                30864801                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             343432                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -378,85 +377,85 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    935593                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                935593                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15313                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       154778                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore       425408                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       510185                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean  2222.203710                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 14681.416911                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535       506821     99.34%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071         1912      0.37%     99.72% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607          970      0.19%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143          202      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679          151      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215           19      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751           50      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::458752-524287           49      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::524288-589823            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       510185                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       473757                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23106.578900                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 18127.358359                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20599.365275                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       462892     97.71%     97.71% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071         7688      1.62%     99.33% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607         2250      0.47%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143          174      0.04%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679          494      0.10%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           87      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751          117      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287           41      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       473757                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 784064516876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.722483                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.520538                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1  781865994376     99.72%     99.72% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3    1176082000      0.15%     99.87% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5     477234000      0.06%     99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7     199500000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9     146109500      0.02%     99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11    120981500      0.02%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13     26256500      0.00%     99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15     49725000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17      2626500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::18-19         7500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 784064516876                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        154779     91.00%     91.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         15313      9.00%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       170092                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       935593                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks                    949667                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                949667                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        16250                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       155668                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore       435817                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       513850                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean  2276.559307                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 14912.808509                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535       510335     99.32%     99.32% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071         1958      0.38%     99.70% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607         1047      0.20%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143          218      0.04%     99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679          154      0.03%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215           27      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751           51      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287           54      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       513850                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       485169                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 23149.084134                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 18057.598080                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 21275.722761                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       473369     97.57%     97.57% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071         7953      1.64%     99.21% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         2827      0.58%     99.79% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143          192      0.04%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679          567      0.12%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215          106      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           98      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287           42      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       485169                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 791579212632                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.715441                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.525649                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1  789339278132     99.72%     99.72% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3    1195712000      0.15%     99.87% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5     474046500      0.06%     99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7     207567500      0.03%     99.95% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9     154449500      0.02%     99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11    121794500      0.02%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13     29070000      0.00%     99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15     54831500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17      2463000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 791579212632                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        155669     90.55%     90.55% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         16250      9.45%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       171919                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       949667                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       935593                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       170092                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       949667                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       171919                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       170092                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total      1105685                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       171919                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total      1121586                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    168870430                       # DTB read hits
-system.cpu.dtb.read_misses                     669785                       # DTB read misses
-system.cpu.dtb.write_hits                   146966916                       # DTB write hits
-system.cpu.dtb.write_misses                    265808                       # DTB write misses
+system.cpu.dtb.read_hits                    169633674                       # DTB read hits
+system.cpu.dtb.read_misses                     671728                       # DTB read misses
+system.cpu.dtb.write_hits                   147819857                       # DTB write hits
+system.cpu.dtb.write_misses                    277939                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid               39148                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid                    1017                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    71844                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                        98                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   9429                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid               39573                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid                    1021                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries                    72392                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                        97                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                   9958                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                     69613                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                169540215                       # DTB read accesses
-system.cpu.dtb.write_accesses               147232724                       # DTB write accesses
+system.cpu.dtb.perms_faults                     70151                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                170305402                       # DTB read accesses
+system.cpu.dtb.write_accesses               148097796                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         315837346                       # DTB hits
-system.cpu.dtb.misses                          935593                       # DTB misses
-system.cpu.dtb.accesses                     316772939                       # DTB accesses
+system.cpu.dtb.hits                         317453531                       # DTB hits
+system.cpu.dtb.misses                          949667                       # DTB misses
+system.cpu.dtb.accesses                     318403198                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -486,884 +485,885 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    161130                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                161130                       # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2         1443                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       121427                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore        17608                       # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples       143522                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean  1275.602347                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev  9467.048086                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767       142512     99.30%     99.30% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535          586      0.41%     99.70% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303           51      0.04%     99.74% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071           83      0.06%     99.80% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839          223      0.16%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607           32      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375            5      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks                    160444                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                160444                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2         1424                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       120836                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore        17536                       # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples       142908                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean  1360.753072                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 10149.850878                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767       141808     99.23%     99.23% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535          585      0.41%     99.64% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303           64      0.04%     99.68% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071          103      0.07%     99.76% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839          274      0.19%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607           31      0.02%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375            7      0.00%     99.97% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911           13      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911           17      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
 system.cpu.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       143522                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       140478                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 29089.590541                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24285.230021                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 22670.988579                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       137385     97.80%     97.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071          891      0.63%     98.43% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1925      1.37%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143           93      0.07%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679          119      0.08%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           27      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           23      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       140478                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 668097269884                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean     0.944108                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev     0.230056                       # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0     37393446856      5.60%      5.60% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1    630652469528     94.40%     99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2        50695000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3          657500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::4            1000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 668097269884                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        121427     98.83%     98.83% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M          1443      1.17%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       122870                       # Table walker page sizes translated
+system.cpu.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-425983            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       142908                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       139796                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 29385.243498                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24234.240486                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 24521.703817                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       136348     97.53%     97.53% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071          877      0.63%     98.16% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607         2201      1.57%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143          135      0.10%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679          151      0.11%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           29      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           40      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       139796                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 671317017344                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean     0.945059                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev     0.228245                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0     36939918060      5.50%      5.50% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1    634320646784     94.49%     99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2        55500500      0.01%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3          942000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::4           10000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 671317017344                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        120836     98.84%     98.84% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1424      1.16%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       122260                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       161130                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       161130                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       160444                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       160444                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       122870                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       122870                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       284000                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    355391745                       # ITB inst hits
-system.cpu.itb.inst_misses                     161130                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       122260                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       122260                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       282704                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    357283873                       # ITB inst hits
+system.cpu.itb.inst_misses                     160444                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid               39148                       # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid                    1017                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                    52871                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid               39573                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid                    1021                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries                    53225                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                    369048                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                    370647                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                355552875                       # ITB inst accesses
-system.cpu.itb.hits                         355391745                       # DTB hits
-system.cpu.itb.misses                          161130                       # DTB misses
-system.cpu.itb.accesses                     355552875                       # DTB accesses
-system.cpu.numCycles                       1639149006                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                357444317                       # ITB inst accesses
+system.cpu.itb.hits                         357283873                       # DTB hits
+system.cpu.itb.misses                          160444                       # DTB misses
+system.cpu.itb.accesses                     357444317                       # DTB accesses
+system.cpu.numCycles                       1651928956                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          642133876                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      997446842                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   223536271                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          133817432                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     910640256                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                25987402                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                    3814067                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                27748                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles       9296817                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      1023598                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          983                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 355005878                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               6082209                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                   48751                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples         1579931046                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.739715                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.145918                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          644904840                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1002675339                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   224688792                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          134555038                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     920067624                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                26040080                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                    3808104                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                29772                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles       9331769                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      1037128                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          949                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 356896495                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6093203                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                   48590                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples         1592200226                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.737909                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.145097                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0               1024858413     64.87%     64.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                213048750     13.48%     78.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 70422001      4.46%     82.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                271601882     17.19%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0               1034156168     64.95%     64.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                214254104     13.46%     78.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 70725246      4.44%     82.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                273064708     17.15%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1579931046                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.136373                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.608515                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                522505611                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             567007663                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 431520293                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              49702709                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9194770                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33525771                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred               3859042                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1080875290                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              28941730                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9194770                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                566963257                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                68325752                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles      370117398                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 436739828                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             128590041                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1061188804                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               6761282                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               5074872                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 331009                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 667465                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               77645177                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            20261                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1009236679                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1634390089                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1255037462                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1470821                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             943893813                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 65342863                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts           26761446                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts       23109655                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 101993436                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            172887729                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           150512713                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           9835963                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8956761                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1026341207                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded            27052915                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1041697414                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3264017                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60219112                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33542548                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         311458                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1579931046                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.659331                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.917837                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1592200226                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.136016                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.606972                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                524217376                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             575207225                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 433339906                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              50215792                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9219927                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             33654884                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred               3860028                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             1086626232                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              28988785                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9219927                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                568973528                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                70181306                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles      374019312                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 438766207                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             131039946                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1066849636                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6780403                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               5130065                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 345924                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 553258                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               79683463                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            20375                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1014727198                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1644037540                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1261867774                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1469696                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             949117253                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 65609942                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts           27037743                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts       23369810                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 103057716                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            173655780                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           151390357                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           9897841                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9017927                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1031708315                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded            27333559                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1047312719                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3286243                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        60487130                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33695071                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         315067                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1592200226                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.657777                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.917314                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           935073091     59.18%     59.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           332737212     21.06%     80.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           233873919     14.80%     95.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            71794095      4.54%     99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6433566      0.41%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               19163      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           943790813     59.28%     59.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           334741898     21.02%     80.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           234957148     14.76%     95.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            72204170      4.53%     99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6486970      0.41%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               19227      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1579931046                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1592200226                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                57548727     35.04%     35.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 100099      0.06%     35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                   26751      0.02%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              757      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44132085     26.87%     62.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              62410380     38.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                57844214     35.03%     35.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  99575      0.06%     35.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                   26721      0.02%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              685      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44353632     26.86%     61.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              62797684     38.03%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass                11      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             717342377     68.86%     68.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2532202      0.24%     69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                122567      0.01%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   8      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         121087      0.01%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            172736633     16.58%     85.71% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           148842483     14.29%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass                 1      0.00%      0.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             721297441     68.87%     68.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2539668      0.24%     69.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                122649      0.01%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         121234      0.01%     69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            173513888     16.57%     85.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           149717789     14.30%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1041697414                       # Type of FU issued
-system.cpu.iq.rate                           0.635511                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   164218799                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.157645                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3828331710                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1112806179                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1023834597                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             2476979                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             946356                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       909820                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1204359624                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1556578                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          4281868                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1047312719                       # Type of FU issued
+system.cpu.iq.rate                           0.633994                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   165122511                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.157663                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3852756863                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1118723028                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1029355100                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             2477554                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             946947                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       909717                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1210878214                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1557015                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          4319350                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13732493                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14369                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       140572                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6281305                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13798077                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14626                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       142237                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      6323389                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2514322                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1544139                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2533948                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1563961                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9194770                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6870613                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               9053250                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1053615244                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                9219927                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 7084785                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               9314562                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1059264038                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             172887729                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            150512713                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts           22684457                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  56400                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               8925068                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         140572                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3644333                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5090402                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8734735                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1030574997                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             168857481                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10197714                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             173655780                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            151390357                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts           22943670                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  58438                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               9182367                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         142237                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3657929                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5098518                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8756447                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1036137894                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             169621625                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10236296                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        221122                       # number of nop insts executed
-system.cpu.iew.exec_refs                    315819616                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                195518777                       # Number of branches executed
-system.cpu.iew.exec_stores                  146962135                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.628726                       # Inst execution rate
-system.cpu.iew.wb_sent                     1025549780                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1024744417                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 436186320                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 705504935                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.625169                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.618261                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        51156578                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls        26741457                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8371043                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1568002280                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.633402                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.269603                       # Number of insts commited each cycle
+system.cpu.iew.exec_nop                        222164                       # number of nop insts executed
+system.cpu.iew.exec_refs                    317437095                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                196547238                       # Number of branches executed
+system.cpu.iew.exec_stores                  147815470                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.627229                       # Inst execution rate
+system.cpu.iew.wb_sent                     1031075002                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1030264817                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 438532269                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 709380763                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.623674                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.618190                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        51390718                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls        27018492                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           8391642                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1580228062                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.631905                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.268654                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0   1058124948     67.48%     67.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    286691231     18.28%     85.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    120053535      7.66%     93.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     36420041      2.32%     95.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28336916      1.81%     97.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     13959603      0.89%     98.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8598360      0.55%     98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4160425      0.27%     99.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     11657221      0.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0   1067496193     67.55%     67.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    288499411     18.26%     85.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    120593665      7.63%     93.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     36542296      2.31%     95.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28489830      1.80%     97.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14035785      0.89%     98.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8641720      0.55%     98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4180750      0.26%     99.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     11748412      0.74%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1568002280                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            845255961                       # Number of instructions committed
-system.cpu.commit.committedOps              993175006                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1580228062                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            849784302                       # Number of instructions committed
+system.cpu.commit.committedOps              998554740                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      303386643                       # Number of memory references committed
-system.cpu.commit.loads                     159155235                       # Number of loads committed
-system.cpu.commit.membars                     6901293                       # Number of memory barriers committed
-system.cpu.commit.branches                  188640484                       # Number of branches committed
-system.cpu.commit.fp_insts                     896738                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 912506063                       # Number of committed integer instructions.
-system.cpu.commit.function_calls             25186659                       # Number of function calls committed.
+system.cpu.commit.refs                      304924670                       # Number of memory references committed
+system.cpu.commit.loads                     159857702                       # Number of loads committed
+system.cpu.commit.membars                     6942890                       # Number of memory barriers committed
+system.cpu.commit.branches                  189641559                       # Number of branches committed
+system.cpu.commit.fp_insts                     896155                       # Number of committed floating point instructions.
+system.cpu.commit.int_insts                 917432780                       # Number of committed integer instructions.
+system.cpu.commit.function_calls             25317062                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        687431731     69.22%     69.22% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult         2146648      0.22%     69.43% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv            97945      0.01%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc       111997      0.01%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead       159155235     16.02%     85.48% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite      144231408     14.52%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        691266097     69.23%     69.23% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult         2154064      0.22%     69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv            98002      0.01%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc       111865      0.01%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead       159857702     16.01%     85.47% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite      145066968     14.53%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         993175006                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              11657221                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2593153041                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2100498051                       # The number of ROB writes
-system.cpu.timesIdled                         8123602                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        59217960                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                 101023921760                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   845255961                       # Number of Instructions Simulated
-system.cpu.committedOps                     993175006                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.939234                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.939234                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.515668                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.515668                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1219925781                       # number of integer regfile reads
-system.cpu.int_regfile_writes               728690424                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   1462315                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   782072                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 224390859                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                225039549                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              2563491272                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               26777143                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9646522                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.972803                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           282175483                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9647034                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.249973                       # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total         998554740                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              11748412                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   2610868733                       # The number of ROB reads
+system.cpu.rob.rob_writes                  2111769063                       # The number of ROB writes
+system.cpu.timesIdled                         8146861                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59728730                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                 100931682357                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   849784302                       # Number of Instructions Simulated
+system.cpu.committedOps                     998554740                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.943939                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.943939                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.514419                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.514419                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1226658290                       # number of integer regfile reads
+system.cpu.int_regfile_writes               732482403                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   1461367                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   784012                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 225710355                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                226370154                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              2581410543                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               27063260                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           9708370                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.972782                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           283529628                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9708882                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.203118                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.972803                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.972782                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          376                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           35                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          379                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1232341715                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1232341715                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146679057                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146679057                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127793945                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127793945                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       377283                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        377283                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       324111                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       324111                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3281173                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3281173                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3676011                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3676011                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     274473002                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        274473002                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    274850285                       # number of overall hits
-system.cpu.dcache.overall_hits::total       274850285                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9506685                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9506685                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data     11193954                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total     11193954                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1163770                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1163770                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1231562                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1231562                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       446112                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       446112                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses        1238524544                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1238524544                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    147275132                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       147275132                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128498890                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128498890                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       378449                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        378449                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       323156                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       323156                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3306743                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3306743                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3702780                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3702780                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     275774022                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        275774022                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    276152471                       # number of overall hits
+system.cpu.dcache.overall_hits::total       276152471                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9562571                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9562571                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data     11295910                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total     11295910                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1177323                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1177323                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1234379                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1234379                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       448575                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       448575                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data     20700639                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       20700639                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21864409                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21864409                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 165615263000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 165615263000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 435458645679                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 435458645679                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  89047451888                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  89047451888                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6832433500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   6832433500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     20858481                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       20858481                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     22035804                       # number of overall misses
+system.cpu.dcache.overall_misses::total      22035804                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 169032232500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 169032232500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 449840740248                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 449840740248                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  90036958042                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  90036958042                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6928434500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   6928434500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       275500                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       275500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 601073908679                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 601073908679                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 601073908679                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 601073908679                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    156185742                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    156185742                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    138987899                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    138987899                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1541053                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1541053                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::cpu.data      1555673                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.WriteLineReq_accesses::total      1555673                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3727285                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3727285                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3676016                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3676016                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    295173641                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    295173641                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    296714694                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    296714694                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060868                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060868                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080539                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080539                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.755178                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.755178                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791659                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.791659                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119688                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119688                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_latency::cpu.data 618872972748                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 618872972748                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 618872972748                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 618872972748                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    156837703                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    156837703                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    139794800                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    139794800                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data      1555772                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total      1555772                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::cpu.data      1557535                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.WriteLineReq_accesses::total      1557535                       # number of WriteLineReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3755318                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3755318                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3702785                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3702785                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    296632503                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    296632503                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    298188275                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    298188275                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060971                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.060971                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080804                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080804                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.756745                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.756745                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.792521                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.792521                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119451                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119451                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.070130                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.070130                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.073688                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.073688                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17420.926748                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17420.926748                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38901.235942                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38901.235942                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72304.481535                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72304.481535                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15315.511576                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15315.511576                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.070318                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.070318                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.073899                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.073899                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17676.442089                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17676.442089                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39823.328997                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39823.328997                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72941.096731                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72941.096731                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15445.431645                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15445.431645                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        55100                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        55100                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29036.490549                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29036.490549                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27490.974427                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27490.974427                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     49516087                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29670.088284                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29670.088284                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28084.882800                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28084.882800                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     50470132                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1592102                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1604709                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.101077                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.451267                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7469877                       # number of writebacks
-system.cpu.dcache.writebacks::total           7469877                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4421127                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4421127                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9198347                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      9198347                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         6981                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.WriteLineReq_mshr_hits::total         6981                       # number of WriteLineReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218536                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total       218536                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data     13619474                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total     13619474                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data     13619474                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total     13619474                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5085558                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5085558                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1995607                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1995607                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1156964                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1156964                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224581                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1224581                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227576                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       227576                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      7520985                       # number of writebacks
+system.cpu.dcache.writebacks::total           7520985                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4446912                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4446912                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9285751                       # number of WriteReq MSHR hits
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+system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7178                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.WriteLineReq_mshr_hits::total         7178                       # number of WriteLineReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       219380                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total       219380                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data     13732663                       # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::cpu.data     13732663                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total     13732663                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5115659                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5115659                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2010159                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2010159                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1170514                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1170514                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1227201                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1227201                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       229195                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       229195                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      7081165                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      7081165                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      8238129                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      8238129                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      7125818                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      7125818                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      8296332                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      8296332                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  83741631500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  83741631500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  76263176167                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  76263176167                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  22882989500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  22882989500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  87447550388                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  87447550388                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3189935000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3189935000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  85157095500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  85157095500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  78478155174                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  78478155174                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  23792891000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  23792891000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  88415534042                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  88415534042                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3234901000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3234901000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       270500                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       270500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160004807667                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 160004807667                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182887797167                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 182887797167                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6192854000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6192854000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228264964                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228264964                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12421118964                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12421118964                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032561                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032561                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014358                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014358                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.750762                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.750762                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787171                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787171                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061057                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061057                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163635250674                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 163635250674                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187428141674                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 187428141674                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6191802000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6191802000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228377464                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228377464                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12420179464                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12420179464                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032618                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032618                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014379                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014379                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.752369                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.752369                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787912                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787912                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.061032                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.061032                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023990                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.023990                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027764                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027764                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16466.557160                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16466.557160                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38215.528492                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38215.528492                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19778.480143                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19778.480143                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71410.180615                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71410.180615                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14017.009702                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14017.009702                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.024022                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.024022                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027822                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027822                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16646.358856                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16646.358856                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39040.769996                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39040.769996                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20326.874348                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20326.874348                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 72046.497715                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 72046.497715                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14114.186610                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14114.186610                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        54100                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        54100                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22595.831006                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22595.831006                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22200.161853                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22200.161853                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183884.256785                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183884.256785                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184836.923196                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184836.923196                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184360.717250                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184360.717250                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22963.714576                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22963.714576                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22591.687709                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22591.687709                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183853.019776                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183853.019776                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184840.261871                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184840.261871                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184346.772702                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184346.772702                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          14982836                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.916862                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           339236129                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          14983348                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             22.640876                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements          15025014                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.916800                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           341084146                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          15025526                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             22.700313                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       24730722500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.916862                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999838                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999838                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.916800                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999837                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999837                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           97                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         369968151                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        369968151                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    339236129                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       339236129                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     339236129                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        339236129                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    339236129                       # number of overall hits
-system.cpu.icache.overall_hits::total       339236129                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     15748452                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      15748452                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     15748452                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       15748452                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     15748452                       # number of overall misses
-system.cpu.icache.overall_misses::total      15748452                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 212811738878                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 212811738878                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 212811738878                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 212811738878                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 212811738878                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 212811738878                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    354984581                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    354984581                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    354984581                       # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::cpu.inst    354984581                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    354984581                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044364                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.044364                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.044364                       # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::cpu.inst     0.044364                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.044364                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13513.184590                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13513.184590                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13513.184590                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13513.184590                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13513.184590                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13513.184590                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        22549                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         371900940                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        371900940                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    341084146                       # number of ReadReq hits
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst 213656099879                       # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::total 213656099879                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    356875197                       # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total    356875197                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044248                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.044248                       # miss rate for ReadReq accesses
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+system.cpu.icache.demand_miss_rate::total     0.044248                       # miss rate for demand accesses
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+system.cpu.icache.overall_miss_rate::total     0.044248                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13530.201370                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13530.201370                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13530.201370                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13530.201370                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13530.201370                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13530.201370                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        23378                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              1395                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              1447                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    16.164158                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    16.156185                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks     14982836                       # number of writebacks
-system.cpu.icache.writebacks::total          14982836                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst       764882                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total       764882                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst       764882                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total       764882                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst       764882                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total       764882                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst     14983570                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total     14983570                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst     14983570                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total     14983570                       # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total     14983570                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks     15025014                       # number of writebacks
+system.cpu.icache.writebacks::total          15025014                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst       765308                       # number of ReadReq MSHR hits
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 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190589950887                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 190589950887                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190589950887                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 190589950887                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190589950887                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 190589950887                       # number of overall MSHR miss cycles
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+system.cpu.icache.ReadReq_mshr_miss_latency::total 191350406888                       # number of ReadReq MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042209                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.042209                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042209                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.042209                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12719.929288                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12719.929288                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12719.929288                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12719.929288                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042104                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042104                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042104                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.042104                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042104                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.042104                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12734.838263                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12734.838263                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12734.838263                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12734.838263                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12734.838263                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12734.838263                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1120546                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65234.831512                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           45882504                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1182138                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            38.813154                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1160032                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65258.923808                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           46054624                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1222499                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            37.672525                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      22908442500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37014.981518                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   292.089334                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   422.524862                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8026.847283                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 19478.388514                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.564804                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004457                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006447                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.122480                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.297217                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995405                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023          295                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61297                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          295                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          558                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2697                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5154                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52826                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004501                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.935318                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        407493288                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       407493288                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       779225                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       298670                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1077895                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks      7469877                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      7469877                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     14980289                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     14980289                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         9372                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         9372                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 37170.221016                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   291.467899                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   431.621608                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7623.970972                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 19741.642313                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.567173                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004447                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006586                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.116333                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.301234                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.995772                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023          293                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        62174                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4          293                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          537                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2696                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5137                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53733                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004471                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.948700                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        409232486                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       409232486                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       784138                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       294772                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1078910                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks      7520985                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      7520985                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     15022476                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     15022476                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         9415                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         9415                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1568886                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1568886                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14901485                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total     14901485                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6220691                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6220691                       # number of ReadSharedReq hits
-system.cpu.l2cache.InvalidateReq_hits::cpu.data       731394                       # number of InvalidateReq hits
-system.cpu.l2cache.InvalidateReq_hits::total       731394                       # number of InvalidateReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       779225                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker       298670                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst     14901485                       # number of demand (read+write) hits
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-system.cpu.l2cache.demand_hits::total        23768957                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       779225                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker       298670                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst     14901485                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7789577                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       23768957                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3206                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3174                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         6380                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data        33876                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total        33876                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1567928                       # number of ReadExReq hits
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+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14941736                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total     14941736                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6252288                       # number of ReadSharedReq hits
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+system.cpu.l2cache.InvalidateReq_hits::cpu.data       727284                       # number of InvalidateReq hits
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 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       386656                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       386656                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        81874                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        81874                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       246229                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       246229                       # number of ReadSharedReq misses
-system.cpu.l2cache.InvalidateReq_misses::cpu.data       493187                       # number of InvalidateReq misses
-system.cpu.l2cache.InvalidateReq_misses::total       493187                       # number of InvalidateReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker         3206                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker         3174                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        81874                       # number of demand (read+write) misses
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-system.cpu.l2cache.demand_misses::total        721139                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker         3206                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker         3174                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        81874                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       632885                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       721139                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    444507000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    436877000                       # number of ReadReq miss cycles
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-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1421351500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total   1421351500                       # number of UpgradeReq miss cycles
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
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-system.cpu.l2cache.InvalidateReq_miss_latency::total  76472888000                       # number of InvalidateReq miss cycles
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-system.cpu.l2cache.WritebackDirty_accesses::total      7469877                       # number of WritebackDirty accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       787797                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       298353                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1086150                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      7520985                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      7520985                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     15022476                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     15022476                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43844                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total        43844                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1955542                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1955542                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     14983359                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     14983359                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6466920                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      6466920                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1224581                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1224581                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       782431                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker       301844                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst     14983359                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      8422462                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     24490096                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       782431                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker       301844                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst     14983359                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      8422462                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     24490096                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010515                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.005884                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.783296                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.783296                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1969613                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1969613                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     15025540                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total     15025540                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6512078                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      6512078                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1227201                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.InvalidateReq_accesses::total      1227201                       # number of InvalidateReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker       787797                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker       298353                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst     15025540                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      8481691                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     24593381                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker       787797                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker       298353                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst     15025540                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      8481691                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     24593381                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004645                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.012003                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.006666                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.785261                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.785261                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.600000                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.600000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.197723                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.197723                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005464                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005464                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.038075                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.038075                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.402739                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.402739                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.010515                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005464                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.075143                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.029446                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004097                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.010515                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005464                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.075143                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.029446                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137642.407057                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 138147.962382                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41957.477270                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41957.477270                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.203941                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.203941                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005577                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005577                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.039894                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.039894                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.407364                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.407364                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004645                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.012003                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005577                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.077989                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.030598                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004645                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.012003                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005577                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.077989                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.030598                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136977.999453                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137566.322256                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 137268.991713                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41410.221035                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41410.221035                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138807.494258                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138807.494258                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134607.335662                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134607.335662                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 138900.901194                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 138900.901194                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155058.604546                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155058.604546                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137642.407057                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134607.335662                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 138843.834978                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 138356.690596                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138648.471616                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137642.407057                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134607.335662                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 138843.834978                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 138356.690596                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138987.986855                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138987.986855                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134754.623884                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134754.623884                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139216.442126                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139216.442126                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 154976.918168                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 154976.918168                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136977.999453                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137566.322256                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134754.623884                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139077.711176                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 138578.870434                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136977.999453                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137566.322256                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134754.623884                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139077.711176                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 138578.870434                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1372,41 +1372,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       943662                       # number of writebacks
-system.cpu.l2cache.writebacks::total           943662                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       971973                       # number of writebacks
+system.cpu.l2cache.writebacks::total           971973                       # number of writebacks
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           19                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total           19                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           19                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           19                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           19                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3206                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3174                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         6380                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3659                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3581                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         7240                       # number of ReadReq MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        33876                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        33876                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        34429                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        34429                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       386656                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       386656                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        81874                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        81874                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       246210                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       246210                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       493187                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       493187                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3206                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3174                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        81874                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       632866                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       721120                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3206                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3174                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        81874                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       632866                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       721120                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       401685                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       401685                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        83804                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        83804                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       259771                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       259771                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       499917                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       499917                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3659                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3581                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        83804                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       661456                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       752500                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3659                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3581                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        83804                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       661456                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       752500                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54972                       # number of ReadReq MSHR uncacheable
@@ -1415,162 +1415,163 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    405137000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    817584000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2397445500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2397445500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    464612500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    456815000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    921427500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2436642500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2436642500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       212000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       212000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  49804190500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  49804190500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10202101000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10202101000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31736616500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31736616500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  71541018000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  71541018000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    405137000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10202101000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  81540807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  92560492000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    412447000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    405137000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10202101000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  81540807000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  92560492000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  51812539500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  51812539500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10454936500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10454936500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  33566675000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  33566675000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  72476426000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  72476426000                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    464612500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    456815000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10454936500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  85379214500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  96755578500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    464612500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    456815000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10454936500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  85379214500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  96755578500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5771724000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8190487000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836234500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836234500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770632000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189395000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836350500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836350500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607958500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14026721500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005884                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11606982500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14025745500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004645                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.012003                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.006666                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.783296                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.783296                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.785261                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.785261                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.197723                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.197723                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005464                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038072                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038072                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.402739                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.402739                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.075140                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.029445                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004097                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010515                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005464                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.075140                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.029445                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128147.962382                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70771.209706                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70771.209706                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.203941                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.203941                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005577                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005577                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039891                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039891                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.407364                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.407364                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004645                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.012003                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005577                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.077986                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.030598                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004645                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.012003                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005577                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.077986                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.030598                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126977.999453                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127566.322256                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127268.991713                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70772.967556                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70772.967556                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128807.494258                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128807.494258                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124607.335662                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128900.599082                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128900.599082                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145058.604546                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145058.604546                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128843.715731                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128356.573108                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127642.407057                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124607.335662                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128843.715731                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128356.573108                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128987.986855                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128987.986855                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124754.623884                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124754.623884                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129216.405988                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129216.405988                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 144976.918168                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 144976.918168                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126977.999453                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127566.322256                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124754.623884                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129077.692998                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128578.841860                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126977.999453                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127566.322256                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124754.623884                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129077.692998                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128578.841860                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171379.654374                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148993.796842                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173202.590812                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173202.590812                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171347.229645                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148973.932184                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.033357                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.033357                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172291.366106                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158193.728290                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172276.879805                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158182.720937                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     49994853                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     25364266                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3498                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2149                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2149                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     50209605                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     25474994                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3484                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2120                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2120                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq        1617841                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      23069110                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq        1623677                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      23162262                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      8520195                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     14980289                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2361594                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        43251                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8599615                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     15022476                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2383518                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        43847                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        43256                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1955542                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1955542                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     14983570                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6475758                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1331245                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1224581                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     44989806                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29161893                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       729252                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1917892                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          76798843                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1918014176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1017349854                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2414752                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6259448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2944038230                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1831110                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     27676926                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.025201                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.156737                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp        43852                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1969613                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1969613                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     15025743                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6520923                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1333865                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1227201                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45116347                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29348618                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       723959                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1930896                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          77119820                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1923413728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1024410462                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2386824                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6302376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2956513390                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1874549                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     27826881                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.025283                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.156985                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           26979426     97.48%     97.48% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             697500      2.52%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           27123321     97.47%     97.47% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             703560      2.53%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       27676926                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    47946942997                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       27826881                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    48147469995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1474889                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1446401                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   22505485675                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   22568730706                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13321051501                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13411529968                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     427763271                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     425937320                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy    1135810761                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy    1143472216                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40286                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40286                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40293                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40293                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1580,18 +1581,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230930                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230930                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230944                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230944                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353714                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353728                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1601,24 +1600,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334152                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334152                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334208                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334208                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492072                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             41870500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492128                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             41872500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               342000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
@@ -1631,79 +1629,73 @@ system.iobus.reqLayer16.occupancy               14500                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25173000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25139500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              168500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36500500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            36497500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           565848565                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              129000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565751099                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               44500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147690000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147704000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115446                       # number of replacements
-system.iocache.tags.tagsinuse               10.422238                       # Cycle average of tags in use
+system.iocache.tags.replacements               115453                       # number of replacements
+system.iocache.tags.tagsinuse               10.417914                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115462                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115469                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         13103145499000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.543896                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.878342                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221494                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429896                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651390                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ethernet     3.546638                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.871276                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221665                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.429455                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651120                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039542                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039542                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039605                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039605                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8801                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8838                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8808                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8845                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8801                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8841                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8808                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8848                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8801                       # number of overall misses
-system.iocache.overall_misses::total             8841                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1693888006                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1698957506                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8808                       # number of overall misses
+system.iocache.overall_misses::total             8848                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5070500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1690818481                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1695888981                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13866022593                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13866022593                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1693888006                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1699308506                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1693888006                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1699308506                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13865997584                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13865997584                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5421500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1690818481                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1696239981                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5421500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1690818481                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1696239981                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8801                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8838                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8808                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8845                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8801                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8841                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8808                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8848                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8801                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8841                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8808                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8848                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1717,55 +1709,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 192465.402341                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 192233.254809                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 191963.951067                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 191734.197965                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129997.211740                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129997.211740                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 192465.402341                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 192207.726049                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 192465.402341                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 192207.726049                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         36226                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129996.977274                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129996.977274                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 191963.951067                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 191708.858612                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 191963.951067                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 191708.858612                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         36185                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3621                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3641                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.004419                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.938204                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8801                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8838                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8808                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8845                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8801                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8841                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8808                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8848                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8801                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8841                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1253838006                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1257057506                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8808                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8848                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1250418481                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1253638981                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8532822593                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8532822593                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1253838006                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1257258506                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1253838006                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1257258506                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8532797584                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8532797584                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3421500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1250418481                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1253839981                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3421500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1250418481                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1253839981                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1779,73 +1771,73 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142465.402341                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 142233.254809                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141963.951067                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 141734.197965                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79997.211740                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79997.211740                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 142465.402341                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 142207.726049                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 142465.402341                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 142207.726049                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79996.977274                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79996.977274                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 141963.951067                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 141708.858612                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 141963.951067                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 141708.858612                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
-system.membus.trans_dist::ReadResp             398274                       # Transaction distribution
+system.membus.trans_dist::ReadResp             414632                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1050292                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           182485                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34687                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1078603                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           193680                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35229                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           34690                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            879035                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           879035                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        343302                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           35232                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            900805                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           900805                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        359660                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3662907                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3792527                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342336                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342336                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4134863                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3779727                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3909347                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342337                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342337                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4251684                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    138377164                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    138547134                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7264192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7264192                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               145811326                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2632                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2687314                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    142628812                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    142798782                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7263040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7263040                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               150061822                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2657                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2765486                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2687314    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2765486    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2687314                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           103976500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2765486                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           103948000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               32000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5452000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5458000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7124848125                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7323908114                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6613283400                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6816104590                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          227684837                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227615986                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -1900,6 +1892,6 @@ system.realview.mcc.osc_mcc.clock               20000                       # Cl
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    16105                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    16126                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal
index 27543035d..1b50f034a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal
@@ -104,13 +104,13 @@
 [    3.136841] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]

 [    3.136852] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]

 [    3.136885] pci_bus 0000:00: fixups for bus

-[    3.136894] pci_bus 0000:00: bus scan returning with max=00

+[    3.136893] pci_bus 0000:00: bus scan returning with max=00

 [    3.136906] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc

 [    3.136925] pci 0000:00:00.0: fixup irq: got 33

-[    3.136934] pci 0000:00:00.0: assigning IRQ 33

+[    3.136933] pci 0000:00:00.0: assigning IRQ 33

 [    3.136944] pci 0000:00:01.0: fixup irq: got 34

 [    3.136952] pci 0000:00:01.0: assigning IRQ 34

-[    3.136964] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

+[    3.136963] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

 [    3.136976] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]

 [    3.136989] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

 [    3.137002] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

@@ -119,17 +119,17 @@
 [    3.137036] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

 [    3.137048] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

 [    3.137493] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

-[    3.137734] ata_piix 0000:00:01.0: version 2.13

-[    3.137745] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

-[    3.137769] ata_piix 0000:00:01.0: enabling bus mastering

-[    3.138034] scsi0 : ata_piix

-[    3.138126] scsi1 : ata_piix

-[    3.138154] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

-[    3.138167] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

-[    3.138266] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

-[    3.138278] e1000: Copyright (c) 1999-2006 Intel Corporation.

-[    3.138293] e1000 0000:00:00.0: enabling device (0000 -> 0002)

-[    3.138304] e1000 0000:00:00.0: enabling bus mastering

+[    3.137735] ata_piix 0000:00:01.0: version 2.13

+[    3.137746] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

+[    3.137770] ata_piix 0000:00:01.0: enabling bus mastering

+[    3.138035] scsi0 : ata_piix

+[    3.138128] scsi1 : ata_piix

+[    3.138156] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

+[    3.138168] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

+[    3.138267] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

+[    3.138279] e1000: Copyright (c) 1999-2006 Intel Corporation.

+[    3.138294] e1000 0000:00:00.0: enabling device (0000 -> 0002)

+[    3.138306] e1000 0000:00:00.0: enabling bus mastering

 [    3.290915] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66

 [    3.290924] ata1.00: 2096640 sectors, multi 0: LBA 

 [    3.290951] ata1.00: configured for UDMA/33

@@ -160,7 +160,7 @@
 
 [    3.450398] udevd[607]: starting version 182

 Starting Bootlog daemon: bootlogd.


-[    3.543435] random: dd urandom read with 19 bits of entropy available

+[    3.533417] random: dd urandom read with 19 bits of entropy available

 Populating dev cache


 net.ipv4.conf.default.rp_filter = 1


 net.ipv4.conf.all.rp_filter = 1


@@ -168,7 +168,7 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory
 Mon Jan 27 08:00:00 UTC 2014


 hwclock: can't open '/dev/misc/rtc': No such file or directory


 
INIT: Entering runlevel: 5



-Configuring network interfaces... [    3.671120] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

+Configuring network interfaces... [    3.661125] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

 udhcpc (v1.21.1) started


 Sending discover...


 Sending discover...


diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini
index b3ebdc75c..78dc4998c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -419,10 +419,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -449,7 +448,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -512,12 +511,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -610,16 +606,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -635,7 +630,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -798,13 +793,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -814,9 +809,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -858,7 +852,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -939,14 +933,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -963,7 +956,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -978,7 +971,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1101,17 +1094,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1163,7 +1158,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1178,7 +1173,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json
index 776ebdfff..28d4955ee 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json
@@ -19,10 +19,6 @@
                 "role": "SLAVE"
             }, 
             "name": "iobus", 
-            "default": {
-                "peer": "system.realview.pciconfig.pio", 
-                "role": "MASTER"
-            }, 
             "forward_latency": 1, 
             "clk_domain": "system.clk_domain", 
             "width": 16, 
@@ -31,6 +27,7 @@
                 "peer": [
                     "system.realview.uart.pio", 
                     "system.realview.realview_io.pio", 
+                    "system.realview.pci_host.pio", 
                     "system.realview.timer0.pio", 
                     "system.realview.timer1.pio", 
                     "system.realview.clcd.pio", 
@@ -38,7 +35,6 @@
                     "system.realview.kmi0.pio", 
                     "system.realview.kmi1.pio", 
                     "system.realview.cf_ctrl.pio", 
-                    "system.realview.cf_ctrl.config", 
                     "system.realview.rtc.pio", 
                     "system.realview.vram.port", 
                     "system.realview.l2x0_fake.pio", 
@@ -53,9 +49,7 @@
                     "system.realview.mmc_fake.pio", 
                     "system.realview.energy_ctrl.pio", 
                     "system.realview.ide.pio", 
-                    "system.realview.ide.config", 
                     "system.realview.ethernet.pio", 
-                    "system.realview.ethernet.config", 
                     "system.iocache.cpu_side"
                 ], 
                 "role": "MASTER"
@@ -64,11 +58,11 @@
             "cxx_class": "NoncoherentXBar", 
             "path": "system.iobus", 
             "type": "NoncoherentXBar", 
-            "use_default_range": true, 
+            "use_default_range": false, 
             "frontend_latency": 2
         }, 
         "symbolfile": "", 
-        "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh", 
+        "readfile": "/work/gem5/outgoing/gem5_2/tests/halt.sh", 
         "have_large_asid_64": false, 
         "phys_addr_range_64": 40, 
         "have_lpae": false, 
@@ -115,7 +109,7 @@
                 "workaround_dma_line_count": true, 
                 "amba_id": 1314816, 
                 "pio": {
-                    "peer": "system.iobus.master[5]", 
+                    "peer": "system.iobus.master[6]", 
                     "role": "SLAVE"
                 }, 
                 "pio_latency": 10000, 
@@ -174,7 +168,23 @@
                 "pio_addr": 471269376, 
                 "type": "PL031"
             }, 
-            "pci_cfg_gen_offsets": true, 
+            "watchdog_fake": {
+                "name": "watchdog_fake", 
+                "pio": {
+                    "peer": "system.iobus.master[17]", 
+                    "role": "SLAVE"
+                }, 
+                "amba_id": 0, 
+                "ignore_access": false, 
+                "pio_latency": 100000, 
+                "clk_domain": "system.clk_domain", 
+                "system": "system", 
+                "eventq_index": 0, 
+                "cxx_class": "AmbaFake", 
+                "path": "system.realview.watchdog_fake", 
+                "pio_addr": 470745088, 
+                "type": "AmbaFake"
+            }, 
             "vgic": {
                 "system": "system", 
                 "name": "vgic", 
@@ -348,7 +358,7 @@
             "timer1": {
                 "name": "timer1", 
                 "pio": {
-                    "peer": "system.iobus.master[3]", 
+                    "peer": "system.iobus.master[4]", 
                     "role": "SLAVE"
                 }, 
                 "amba_id": 1316868, 
@@ -369,7 +379,7 @@
             "timer0": {
                 "name": "timer0", 
                 "pio": {
-                    "peer": "system.iobus.master[2]", 
+                    "peer": "system.iobus.master[3]", 
                     "role": "SLAVE"
                 }, 
                 "amba_id": 1316868, 
@@ -422,6 +432,26 @@
                 "pio_addr": 470286336
             }, 
             "type": "RealView", 
+            "pci_host": {
+                "conf_size": 268435456, 
+                "name": "pci_host", 
+                "conf_device_bits": 12, 
+                "pio": {
+                    "peer": "system.iobus.master[2]", 
+                    "role": "SLAVE"
+                }, 
+                "conf_base": 805306368, 
+                "clk_domain": "system.clk_domain", 
+                "system": "system", 
+                "pci_dma_base": 0, 
+                "platform": "system.realview", 
+                "eventq_index": 0, 
+                "cxx_class": "GenericPciHost", 
+                "path": "system.realview.pci_host", 
+                "pci_pio_base": 788529152, 
+                "type": "GenericPciHost", 
+                "pci_mem_base": 0
+            }, 
             "lan_fake": {
                 "system": "system", 
                 "ret_data8": 255, 
@@ -617,25 +647,6 @@
                     "type": "RealViewOsc"
                 }
             }, 
-            "pciconfig": {
-                "name": "pciconfig", 
-                "pio": {
-                    "peer": "system.iobus.default", 
-                    "role": "SLAVE"
-                }, 
-                "bus": 0, 
-                "pio_latency": 30000, 
-                "clk_domain": "system.clk_domain", 
-                "system": "system", 
-                "platform": "system.realview", 
-                "eventq_index": 0, 
-                "cxx_class": "PciConfigAll", 
-                "path": "system.realview.pciconfig", 
-                "pio_addr": 0, 
-                "type": "PciConfigAll", 
-                "size": 268435456
-            }, 
-            "pci_cfg_base": 805306368, 
             "path": "system.realview", 
             "vram": {
                 "range": "402653184:436207615", 
@@ -656,7 +667,6 @@
                 }, 
                 "in_addr_map": true
             }, 
-            "pci_io_base": 788529152, 
             "nvmem": {
                 "range": "0:67108863", 
                 "latency": 30000, 
@@ -685,7 +695,7 @@
                 "vnc": "system.vncserver", 
                 "name": "clcd", 
                 "pio": {
-                    "peer": "system.iobus.master[4]", 
+                    "peer": "system.iobus.master[5]", 
                     "role": "SLAVE"
                 }, 
                 "amba_id": 1315089, 
@@ -723,30 +733,13 @@
                 "pio_addr": 470351872, 
                 "type": "Pl011"
             }, 
-            "watchdog_fake": {
-                "name": "watchdog_fake", 
-                "pio": {
-                    "peer": "system.iobus.master[17]", 
-                    "role": "SLAVE"
-                }, 
-                "amba_id": 0, 
-                "ignore_access": false, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
-                "system": "system", 
-                "eventq_index": 0, 
-                "cxx_class": "AmbaFake", 
-                "path": "system.realview.watchdog_fake", 
-                "pio_addr": 470745088, 
-                "type": "AmbaFake"
-            }, 
             "intrctrl": "system.intrctrl", 
             "kmi1": {
                 "vnc": "system.vncserver", 
                 "name": "kmi1", 
                 "int_delay": 1000000, 
                 "pio": {
-                    "peer": "system.iobus.master[7]", 
+                    "peer": "system.iobus.master[8]", 
                     "role": "SLAVE"
                 }, 
                 "amba_id": 1314896, 
@@ -767,7 +760,7 @@
                 "name": "kmi0", 
                 "int_delay": 1000000, 
                 "pio": {
-                    "peer": "system.iobus.master[6]", 
+                    "peer": "system.iobus.master[7]", 
                     "role": "SLAVE"
                 }, 
                 "amba_id": 1314896, 
@@ -794,7 +787,6 @@
                 "Revision": 0, 
                 "LegacyIOBase": 0, 
                 "pio_latency": 30000, 
-                "platform": "system.realview", 
                 "PXCAPLinkCap": 0, 
                 "CapabilityPtr": 0, 
                 "MSIXCAPBaseOffset": 0, 
@@ -828,6 +820,7 @@
                 "PXCAPDevCap2": 0, 
                 "PXCAPDevCtrl": 0, 
                 "MSICAPMaskBits": 0, 
+                "host": "system.realview.pci_host", 
                 "Command": 1, 
                 "SubClassCode": 1, 
                 "pci_func": 0, 
@@ -862,7 +855,7 @@
                 "config_latency": 20000, 
                 "BAR1Size": 4096, 
                 "pio": {
-                    "peer": "system.iobus.master[8]", 
+                    "peer": "system.iobus.master[9]", 
                     "role": "SLAVE"
                 }, 
                 "pci_dev": 0, 
@@ -871,10 +864,6 @@
                 "clk_domain": "system.clk_domain", 
                 "SubsystemVendorID": 0, 
                 "PMCAPBaseOffset": 0, 
-                "config": {
-                    "peer": "system.iobus.master[9]", 
-                    "role": "SLAVE"
-                }, 
                 "MSICAPPendingBits": 0, 
                 "MSIXTableOffset": 0, 
                 "MSICAPMsgUpperAddr": 0, 
@@ -914,7 +903,6 @@
                 "hardware_address": "00:90:00:00:00:01", 
                 "LegacyIOBase": 0, 
                 "pio_latency": 30000, 
-                "platform": "system.realview", 
                 "PXCAPLinkCap": 0, 
                 "CapabilityPtr": 0, 
                 "MSIXCAPBaseOffset": 0, 
@@ -949,6 +937,7 @@
                 "PXCAPDevCap2": 0, 
                 "PXCAPDevCtrl": 0, 
                 "MSICAPMaskBits": 0, 
+                "host": "system.realview.pci_host", 
                 "Command": 0, 
                 "SubClassCode": 0, 
                 "pci_func": 0, 
@@ -986,7 +975,7 @@
                 "config_latency": 20000, 
                 "BAR1Size": 0, 
                 "pio": {
-                    "peer": "system.iobus.master[25]", 
+                    "peer": "system.iobus.master[24]", 
                     "role": "SLAVE"
                 }, 
                 "pci_dev": 0, 
@@ -997,10 +986,6 @@
                 "clk_domain": "system.clk_domain", 
                 "SubsystemVendorID": 32902, 
                 "PMCAPBaseOffset": 0, 
-                "config": {
-                    "peer": "system.iobus.master[26]", 
-                    "role": "SLAVE"
-                }, 
                 "MSICAPPendingBits": 0, 
                 "MSIXTableOffset": 0, 
                 "MSICAPMsgUpperAddr": 0, 
@@ -1025,7 +1010,6 @@
                 "Revision": 0, 
                 "LegacyIOBase": 0, 
                 "pio_latency": 30000, 
-                "platform": "system.realview", 
                 "PXCAPLinkCap": 0, 
                 "CapabilityPtr": 0, 
                 "MSIXCAPBaseOffset": 0, 
@@ -1061,6 +1045,7 @@
                 "PXCAPDevCap2": 0, 
                 "PXCAPDevCtrl": 0, 
                 "MSICAPMaskBits": 0, 
+                "host": "system.realview.pci_host", 
                 "Command": 0, 
                 "SubClassCode": 1, 
                 "pci_func": 0, 
@@ -1104,10 +1089,6 @@
                 "clk_domain": "system.clk_domain", 
                 "SubsystemVendorID": 0, 
                 "PMCAPBaseOffset": 0, 
-                "config": {
-                    "peer": "system.iobus.master[24]", 
-                    "role": "SLAVE"
-                }, 
                 "MSICAPPendingBits": 0, 
                 "MSIXTableOffset": 0, 
                 "MSICAPMsgUpperAddr": 0, 
@@ -1187,7 +1168,7 @@
         "eventq_index": 0, 
         "iocache": {
             "cpu_side": {
-                "peer": "system.iobus.master[27]", 
+                "peer": "system.iobus.master[25]", 
                 "role": "SLAVE"
             }, 
             "clusivity": "mostly_incl", 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
index 319abdef3..df4777d2f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 436679                       # Simulator instruction rate (inst/s)
-host_op_rate                                   513170                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            22668960410                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 677940                       # Number of bytes of host memory used
-host_seconds                                  2254.68                       # Real time elapsed on the host
+host_inst_rate                                 966487                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1135781                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            50172400532                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 679768                       # Number of bytes of host memory used
+host_seconds                                  1018.71                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -610,6 +610,7 @@ system.iobus.trans_dist::WriteReq              136515                       # Tr
 system.iobus.trans_dist::WriteResp             136515                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47598                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -619,10 +620,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122480                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230962                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total       230962                       # Packet count per connected master and slave (bytes)
@@ -631,6 +629,7 @@ system.iobus.pkt_count_system.realview.ethernet.dma::total           80
 system.iobus.pkt_count::total                  353522                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47618                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -640,10 +639,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334280                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      7334280                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
index 9c8115909..7268469a8 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -763,10 +763,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -793,7 +792,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -893,12 +892,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -991,16 +987,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1016,7 +1011,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1179,13 +1174,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1195,9 +1190,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1239,7 +1233,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1320,14 +1314,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1344,7 +1337,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1359,7 +1352,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1482,17 +1475,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1544,7 +1539,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1559,7 +1554,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout
index c42910ea7..722fe47ae 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 19:23:36
-gem5 executing on e104799-lin, pid 15250
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 13:36:23
+gem5 executing on e104799-lin, pid 11118
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
index 9e6c84550..1a0f4314f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 47.216814                       # Nu
 sim_ticks                                47216814145000                       # Number of ticks simulated
 final_tick                               47216814145000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 564335                       # Simulator instruction rate (inst/s)
-host_op_rate                                   663890                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27316522801                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 691236                       # Number of bytes of host memory used
-host_seconds                                  1728.51                       # Real time elapsed on the host
+host_inst_rate                                 919960                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1082251                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            44530469299                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 691012                       # Number of bytes of host memory used
+host_seconds                                  1060.33                       # Real time elapsed on the host
 sim_insts                                   975457230                       # Number of instructions simulated
 sim_ops                                    1147538415                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1178,6 +1178,7 @@ system.iobus.trans_dist::WriteReq              136634                       # Tr
 system.iobus.trans_dist::WriteResp             136634                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47636                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1187,10 +1188,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122570                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231208                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total       231208                       # Packet count per connected master and slave (bytes)
@@ -1199,6 +1197,7 @@ system.iobus.pkt_count_system.realview.ethernet.dma::total           80
 system.iobus.pkt_count::total                  353858                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47656                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1208,10 +1207,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155677                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338848                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      7338848                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
index b3ebdc75c..78dc4998c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -419,10 +419,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -449,7 +448,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -512,12 +511,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -610,16 +606,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -635,7 +630,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -798,13 +793,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -814,9 +809,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -858,7 +852,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -939,14 +933,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -963,7 +956,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -978,7 +971,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1101,17 +1094,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1163,7 +1158,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1178,7 +1173,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
index 40325ea54..7ce5547c3 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 18:43:21
-gem5 executing on e104799-lin, pid 8676
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 14:02:50
+gem5 executing on e104799-lin, pid 13724
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
index 65b0e7e57..3d9d35410 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 940801                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1105595                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            48838957578                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 678172                       # Number of bytes of host memory used
-host_seconds                                  1046.52                       # Real time elapsed on the host
+host_inst_rate                                 958498                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1126393                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            49757685011                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 676912                       # Number of bytes of host memory used
+host_seconds                                  1027.20                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -610,6 +610,7 @@ system.iobus.trans_dist::WriteReq              136515                       # Tr
 system.iobus.trans_dist::WriteResp             136515                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47598                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -619,10 +620,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122480                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230962                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total       230962                       # Packet count per connected master and slave (bytes)
@@ -631,6 +629,7 @@ system.iobus.pkt_count_system.realview.ethernet.dma::total           80
 system.iobus.pkt_count::total                  353522                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47618                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -640,10 +639,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334280                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      7334280                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
index 6ff10a08d..69d6e9538 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -755,10 +755,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -785,7 +784,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -949,12 +948,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -1047,16 +1043,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1072,7 +1067,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1235,13 +1230,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1251,9 +1246,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1295,7 +1289,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1376,14 +1370,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1400,7 +1393,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1415,7 +1408,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1538,17 +1531,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1600,7 +1595,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1615,7 +1610,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
index bee14beaf..fb6a763d8 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 19:52:38
-gem5 executing on e104799-lin, pid 27835
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 11:53:35
+gem5 executing on e104799-lin, pid 548
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 47602567962500 because m5_exit instruction encountered
+Exiting @ tick 47593744171500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index d1847bb61..afe64e1a8 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -1,167 +1,167 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 47.602568                       # Number of seconds simulated
-sim_ticks                                47602567962500                       # Number of ticks simulated
-final_tick                               47602567962500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 47.593744                       # Number of seconds simulated
+sim_ticks                                47593744171500                       # Number of ticks simulated
+final_tick                               47593744171500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 603747                       # Simulator instruction rate (inst/s)
-host_op_rate                                   710316                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            32933076215                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 740648                       # Number of bytes of host memory used
-host_seconds                                  1445.43                       # Real time elapsed on the host
-sim_insts                                   872675802                       # Number of instructions simulated
-sim_ops                                    1026715135                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 618435                       # Simulator instruction rate (inst/s)
+host_op_rate                                   727668                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            34163076444                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 740160                       # Number of bytes of host memory used
+host_seconds                                  1393.13                       # Real time elapsed on the host
+sim_insts                                   861562684                       # Number of instructions simulated
+sim_ops                                    1013739401                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker        97216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       105280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3176436                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         39189384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher     13261312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        67968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        64704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2473528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         13920528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher      8902656                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        417088                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81676100                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3176436                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2473528                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5649964                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     69006208                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        69440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        68224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3088500                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         37423496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher     12959872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        98944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       107776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2567544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         15084176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher      9154944                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        428992                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             81051908                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3088500                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2567544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         5656044                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     68863296                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          69026792                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1519                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1645                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             90039                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            612347                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       207208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         1062                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1011                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             38737                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            217521                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher       139104                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6517                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1316710                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1078222                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          68883880                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1085                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1066                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             88665                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            584755                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       202498                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         1546                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1684                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             40206                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            235703                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher       143046                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6703                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1306957                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1075989                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1080796                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2042                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2212                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               66728                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              823262                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher       278584                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1428                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          1359                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               51962                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              292432                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       187020                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8762                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1715792                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          66728                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          51962                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             118690                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1449632                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1078563                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1459                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1433                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               64893                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              786311                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher       272302                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2079                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               53947                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              316936                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       192356                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             9014                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1702995                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          64893                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          53947                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             118840                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1446898                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                432                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1450064                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1449632                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2042                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2212                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              66728                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             823694                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher       278584                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1428                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         1359                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              51962                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             292432                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       187020                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8762                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3165856                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1316710                       # Number of read requests accepted
-system.physmem.writeReqs                      1080796                       # Number of write requests accepted
-system.physmem.readBursts                     1316710                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1080796                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 84239104                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     30336                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  69025088                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  81676100                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               69026792                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      474                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2262                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         461546                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               74138                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               82827                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               74957                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               82122                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               83077                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               87558                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               81167                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               84127                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               76730                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              122410                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              70954                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              80684                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              75912                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              81292                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              78761                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              79520                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61777                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               69166                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               64147                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               68304                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               69323                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               73404                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               67894                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               70420                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65275                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               69986                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              62072                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              68038                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64002                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              68951                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              67347                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              68411                       # Per bank write bursts
+system.physmem.bw_write::total                1447331                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1446898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1459                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1433                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              64893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             786744                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher       272302                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2079                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              53947                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             316936                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       192356                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            9014                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3150326                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1306957                       # Number of read requests accepted
+system.physmem.writeReqs                      1078563                       # Number of write requests accepted
+system.physmem.readBursts                     1306957                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1078563                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 83609728                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     35520                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  68881216                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  81051908                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               68883880                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      555                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2266                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         450744                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               74137                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               79440                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               74164                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               81483                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               82988                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               89928                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               78492                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               81076                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               74414                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              117966                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              72212                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              83486                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              77461                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              81836                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              80080                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              77239                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               62409                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               67459                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               64157                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               68996                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               69521                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               74527                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               66146                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               68657                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               63193                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66730                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              63431                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              70210                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              65844                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              70148                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              68557                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              66284                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          25                       # Number of times write queue was full causing retry
-system.physmem.totGap                    47602564597000                       # Total gap between requests
+system.physmem.numWrRetry                          30                       # Number of times write queue was full causing retry
+system.physmem.totGap                    47593740806000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43195                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       5                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1273485                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1263732                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1078222                       # Write request sizes (log2)
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-system.physmem.rdQLenPdf::1                     69154                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     30759                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::4                     22457                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     19787                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     17170                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     15034                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     11894                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::10                      874                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::12                      434                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      323                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      240                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      218                       # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17                      144                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       84                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       59                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        6                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1075989                       # Write request sizes (log2)
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 system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -188,163 +188,163 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::58                       78                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::62                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       70                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       845861                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      181.192513                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     111.718720                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     240.356894                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         524023     61.95%     61.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       157589     18.63%     80.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52244      6.18%     86.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        27763      3.28%     90.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18582      2.20%     92.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11693      1.38%     93.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8942      1.06%     94.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         9176      1.08%     95.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        35849      4.24%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         845861                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60416                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.786182                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      329.918437                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          60413    100.00%    100.00% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::total         840117                       # Bytes accessed per row activation
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 system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::77824-81919            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60416                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60416                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.851513                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.268088                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.277078                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           56734     93.91%     93.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            1553      2.57%     96.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             255      0.42%     96.90% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::68-71              38      0.06%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              49      0.08%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             117      0.19%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              11      0.02%     99.91% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::samples         60330                       # Writes before turning the bus around for reads
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 system.physmem.wrPerTurnAround::104-107             1      0.00%     99.92% # Writes before turning the bus around for reads
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 system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.00%     99.93% # Writes before turning the bus around for reads
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 system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::128-131            24      0.04%     99.97% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             5      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60416                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    28673044871                       # Total ticks spent queuing
-system.physmem.totMemAccLat               53352469871                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   6581180000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       21784.12                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::132-135             2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             7      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           60330                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    28430560155                       # Total ticks spent queuing
+system.physmem.totMemAccLat               52925597655                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   6532010000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       21762.49                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  40534.12                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.77                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40512.49                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.76                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.45                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.72                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.70                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.45                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.42                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1054044                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    494841                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.08                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  45.88                       # Row buffer hit rate for writes
-system.physmem.avgGap                     19855034.61                       # Average gap between requests
-system.physmem.pageHitRate                      64.68                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 3265088400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1781546250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                5069789400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3527867520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3109168015200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1219382745750                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           27491903982750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             31834099035270                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.747581                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   45734675361714                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1589554200000                       # Time in different power states
+system.physmem.avgWrQLen                        26.65                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1047491                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    495062                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.18                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  46.00                       # Row buffer hit rate for writes
+system.physmem.avgGap                     19951096.95                       # Average gap between requests
+system.physmem.pageHitRate                      64.74                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 3221134560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1757563500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5005283400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3511330560                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3108591816720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1216360497735                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           27489261984750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             31827709611225                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.737288                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   45730304477620                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1589259620000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    278338023286                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    274179379380                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 3129537600                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1707585000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                5196804600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3460818960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3109168015200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1215349697925                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           27495441752250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             31833454211535                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.734035                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   45740562014248                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1589554200000                       # Time in different power states
+system.physmem_1.actEnergy                 3130149960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1707919125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5184613200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3462892560                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3108591816720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1215861151230                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           27489700008000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             31827638550795                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.735795                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   45731003279682                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1589259620000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    272450963752                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    273478576568                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -375,9 +375,9 @@ system.realview.nvmem.bw_total::total               4                       # To
 system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1671                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6846976                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1674                       # Number of DMA write transactions.
+system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
+system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -408,69 +408,68 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   111926                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               111926                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        10169                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        86471                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore           18                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       111908                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean     0.232334                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev    77.721788                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047       111907    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                    93408                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong                93408                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2         7983                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        70276                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore            7                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples        93401                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean     0.278370                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev    85.074143                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047        93400    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       111908                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples        96658                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23040.705374                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21274.900589                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 18509.319790                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535        95612     98.92%     98.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          152      0.16%     99.08% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          763      0.79%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           18      0.02%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           39      0.04%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           23      0.02%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           37      0.04%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total        96658                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples    444719432                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean    -3.785405                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     2128162704    478.54%    478.54% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    -1683443272   -378.54%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total    444719432                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        86471     89.48%     89.48% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        10169     10.52%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        96640                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       111926                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::total        93401                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples        78266                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22499.341988                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 20923.382111                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16650.912887                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535        77590     99.14%     99.14% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071          164      0.21%     99.35% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          417      0.53%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           22      0.03%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           25      0.03%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           29      0.04%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total        78266                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   5219685476                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.596746                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.490551                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     2104860204     40.33%     40.33% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1     3114825272     59.67%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   5219685476                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        70276     89.80%     89.80% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M         7983     10.20%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        78259                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        93408                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       111926                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        96640                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        93408                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        78259                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        96640                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       208566                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        78259                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       171667                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    87929647                       # DTB read hits
-system.cpu0.dtb.read_misses                     85158                       # DTB read misses
-system.cpu0.dtb.write_hits                   79744109                       # DTB write hits
-system.cpu0.dtb.write_misses                    26768                       # DTB write misses
+system.cpu0.dtb.read_hits                    80327529                       # DTB read hits
+system.cpu0.dtb.read_misses                     69973                       # DTB read misses
+system.cpu0.dtb.write_hits                   72902451                       # DTB write hits
+system.cpu0.dtb.write_misses                    23435                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              39890                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   37859                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              39478                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                   1020                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   34709                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  3884                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  4393                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    10087                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                88014805                       # DTB read accesses
-system.cpu0.dtb.write_accesses               79770877                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     8867                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                80397502                       # DTB read accesses
+system.cpu0.dtb.write_accesses               72925886                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        167673756                       # DTB hits
-system.cpu0.dtb.misses                         111926                       # DTB misses
-system.cpu0.dtb.accesses                    167785682                       # DTB accesses
+system.cpu0.dtb.hits                        153229980                       # DTB hits
+system.cpu0.dtb.misses                          93408                       # DTB misses
+system.cpu0.dtb.accesses                    153323388                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -500,94 +499,93 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    61252                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                61252                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2          842                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        54849                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        61252                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          61252    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        61252                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        55691                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26308.021045                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23499.981275                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 25689.449100                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        54619     98.08%     98.08% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071           42      0.08%     98.15% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          884      1.59%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           24      0.04%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           48      0.09%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           19      0.03%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           35      0.06%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::655360-720895            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        55691                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    52417                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                52417                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2          598                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        46386                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        52417                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          52417    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        52417                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        46984                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25232.568534                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 22985.913240                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 21269.412068                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        46328     98.60%     98.60% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071           41      0.09%     98.69% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          530      1.13%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           16      0.03%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           24      0.05%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           17      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           22      0.05%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        46984                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   1979242204                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     1979242204    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total   1979242204                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        54849     98.49%     98.49% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M          842      1.51%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        55691                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        46386     98.73%     98.73% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          598      1.27%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        46984                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        61252                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        61252                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        52417                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        52417                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        55691                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        55691                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       116943                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   467202921                       # ITB inst hits
-system.cpu0.itb.inst_misses                     61252                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        46984                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        46984                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total        99401                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   426699171                       # ITB inst hits
+system.cpu0.itb.inst_misses                     52417                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              39890                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   27100                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              39478                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                   1020                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   24801                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               467264173                       # ITB inst accesses
-system.cpu0.itb.hits                        467202921                       # DTB hits
-system.cpu0.itb.misses                          61252                       # DTB misses
-system.cpu0.itb.accesses                    467264173                       # DTB accesses
-system.cpu0.numCycles                     95205135902                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               426751588                       # ITB inst accesses
+system.cpu0.itb.hits                        426699171                       # DTB hits
+system.cpu0.itb.misses                          52417                       # DTB misses
+system.cpu0.itb.accesses                    426751588                       # DTB accesses
+system.cpu0.numCycles                     95186924479                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    5123                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  466948479                       # Number of instructions committed
-system.cpu0.committedOps                    548389991                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            504092161                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                464416                       # Number of float alu accesses
-system.cpu0.num_func_calls                   27983491                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     70438282                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   504092161                       # number of integer instructions
-system.cpu0.num_fp_insts                       464416                       # number of float instructions
-system.cpu0.num_int_register_reads          728885661                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         399652952                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              772857                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             344936                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           120908457                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          120465396                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    167663327                       # number of memory refs
-system.cpu0.num_load_insts                   87924608                       # Number of load instructions
-system.cpu0.num_store_insts                  79738719                       # Number of store instructions
-system.cpu0.num_idle_cycles              93943889977.646729                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1261245924.353277                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.013248                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.986752                       # Percentage of idle cycles
-system.cpu0.Branches                        104008564                       # Number of branches fetched
+system.cpu0.kern.inst.quiesce                    4674                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  426454163                       # Number of instructions committed
+system.cpu0.committedOps                    501120280                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            460758133                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                395268                       # Number of float alu accesses
+system.cpu0.num_func_calls                   25675920                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     64224693                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   460758133                       # number of integer instructions
+system.cpu0.num_fp_insts                       395268                       # number of float instructions
+system.cpu0.num_int_register_reads          666544840                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         365452769                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              661868                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             282064                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           110079606                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          109774743                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    153223313                       # number of memory refs
+system.cpu0.num_load_insts                   80324545                       # Number of load instructions
+system.cpu0.num_store_insts                  72898768                       # Number of store instructions
+system.cpu0.num_idle_cycles              94023627088.560516                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1163297390.439485                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.012221                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.987779                       # Percentage of idle cycles
+system.cpu0.Branches                         94888903                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                379698158     69.20%     69.20% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1212773      0.22%     69.42% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    66852      0.01%     69.43% # Class of executed instruction
+system.cpu0.op_class::IntAlu                346960051     69.20%     69.20% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1125201      0.22%     69.42% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    62694      0.01%     69.43% # Class of executed instruction
 system.cpu0.op_class::FloatAdd                      0      0.00%     69.43% # Class of executed instruction
 system.cpu0.op_class::FloatCmp                      0      0.00%     69.43% # Class of executed instruction
 system.cpu0.op_class::FloatCvt                      0      0.00%     69.43% # Class of executed instruction
@@ -610,127 +608,126 @@ system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.43% # Cl
 system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.43% # Class of executed instruction
 system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.43% # Class of executed instruction
 system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.43% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             46447      0.01%     69.44% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             37154      0.01%     69.44% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.44% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.44% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.44% # Class of executed instruction
-system.cpu0.op_class::MemRead                87924608     16.02%     85.47% # Class of executed instruction
-system.cpu0.op_class::MemWrite               79738719     14.53%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                80324545     16.02%     85.46% # Class of executed instruction
+system.cpu0.op_class::MemWrite               72898768     14.54%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 548687557                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          5767473                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          506.102777                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          161665939                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          5767985                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.028148                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 501408413                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          5237512                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.877232                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          147745204                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          5237891                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.207002                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       6293818000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   506.102777                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988482                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.988482                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          336                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        341141490                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       341141490                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     81909684                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       81909684                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     75364450                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      75364450                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       195602                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       195602                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       139312                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       139312                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1827663                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      1827663                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1798607                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      1798607                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    157274134                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       157274134                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    157469736                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      157469736                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3156555                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      3156555                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1440320                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1440320                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       651795                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       651795                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       776738                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total       776738                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       172749                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       172749                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data       200464                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total       200464                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4596875                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       4596875                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5248670                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      5248670                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  52100226500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  52100226500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  36687284500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  36687284500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  65915448000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  65915448000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2830376000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   2830376000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5792176500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total   5792176500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      4797000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      4797000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  88787511000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  88787511000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  88787511000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  88787511000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     85066239                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     85066239                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     76804770                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     76804770                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       847397                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       847397                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       916050                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total       916050                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2000412                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      2000412                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1999071                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      1999071                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    161871009                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    161871009                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    162718406                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    162718406                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037107                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.037107                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018753                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.018753                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.769173                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.769173                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.847921                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.847921                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086357                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086357                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.100279                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.100279                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028398                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.028398                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032256                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.032256                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16505.407477                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 16505.407477                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25471.620543                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 25471.620543                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 84861.881355                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 84861.881355                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16384.326393                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16384.326393                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28893.848771                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28893.848771                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.877232                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.988041                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.988041                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          379                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          370                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.740234                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        311719457                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       311719457                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     74802484                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       74802484                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     68840975                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      68840975                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       186514                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       186514                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       133741                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       133741                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1712983                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      1712983                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1673957                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      1673957                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    143643459                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       143643459                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    143829973                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      143829973                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      2859232                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      2859232                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1316810                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1316810                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       596453                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       596453                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       721743                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total       721743                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       153137                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       153137                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data       190741                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total       190741                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      4176042                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       4176042                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      4772495                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      4772495                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  45650819500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  45650819500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  34330450500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  34330450500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  65187396500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  65187396500                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2390631500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   2390631500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   5489081000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total   5489081000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      7149000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      7149000                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  79981270000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  79981270000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  79981270000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  79981270000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     77661716                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     77661716                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     70157785                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     70157785                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       782967                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       782967                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       855484                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total       855484                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1866120                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      1866120                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1864698                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      1864698                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    147819501                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    147819501                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    148602468                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    148602468                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.036816                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.036816                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018769                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.018769                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.761786                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.761786                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.843666                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.843666                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.082062                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.082062                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.102291                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.102291                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028251                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.028251                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032116                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.032116                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15966.112404                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15966.112404                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26070.921773                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 26070.921773                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90319.402474                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90319.402474                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15611.063949                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15611.063949                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28777.667098                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28777.667098                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19314.754262                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19314.754262                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16916.192293                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 16916.192293                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19152.410345                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19152.410345                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16758.795976                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 16758.795976                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -739,158 +736,156 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      5767473                       # number of writebacks
-system.cpu0.dcache.writebacks::total          5767473                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        27282                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        27282                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21266                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21266                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        44626                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        44626                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        48548                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        48548                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        48548                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        48548                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3129273                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3129273                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1419054                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1419054                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       650511                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       650511                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       776738                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       776738                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       128123                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       128123                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       200464                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total       200464                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4548327                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4548327                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5198838                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5198838                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15619                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        15619                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16479                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        16479                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32098                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        32098                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  47104061500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  47104061500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  34681725000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  34681725000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  15920895000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  15920895000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  65138711000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  65138711000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1795303000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1795303000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5591766500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5591766500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      4743000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      4743000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  81785786500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  81785786500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  97706681500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  97706681500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2690935500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2690935500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2795849000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2795849000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5486784500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5486784500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036786                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036786                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018476                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018476                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.767658                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.767658                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.847921                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.847921                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064048                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064048                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.100279                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.100279                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028098                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028098                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031950                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.031950                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15052.717197                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15052.717197                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24440.031880                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24440.031880                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24474.443937                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24474.443937                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 83861.882643                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 83861.882643                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14012.339705                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14012.339705                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27894.118146                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27894.118146                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      5237512                       # number of writebacks
+system.cpu0.dcache.writebacks::total          5237512                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25341                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        25341                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        21295                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21295                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        39838                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        39838                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        46636                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        46636                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        46636                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        46636                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2833891                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      2833891                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1295515                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1295515                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       595169                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       595169                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       721743                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       721743                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       113299                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       113299                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       190741                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total       190741                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      4129406                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4129406                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4724575                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4724575                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16746                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16746                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        17968                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        17968                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        34714                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        34714                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  41050881000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41050881000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32444395000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  32444395000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  14818032000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  14818032000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  64465653500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  64465653500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1564895500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1564895500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   5298419000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   5298419000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      7070000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      7070000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  73495276000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  73495276000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  88313308000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  88313308000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2897717500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2897717500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3102799000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3102799000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6000516500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6000516500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.036490                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.036490                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.018466                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018466                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.760146                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.760146                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.843666                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.843666                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.060714                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060714                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.102291                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.102291                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027935                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.027935                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031793                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.031793                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14485.695110                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14485.695110                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25043.627438                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25043.627438                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24897.183825                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24897.183825                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89319.402474                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89319.402474                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13812.085720                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.085720                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27778.081273                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27778.081273                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17981.509795                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17981.509795                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18793.946166                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18793.946166                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172286.029835                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172286.029835                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169661.326537                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169661.326537                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170938.516418                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170938.516418                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17798.026157                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17798.026157                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18692.328516                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18692.328516                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173039.382539                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173039.382539                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172684.717275                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172684.717275                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172855.807455                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172855.807455                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          5175196                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.827248                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          462027213                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          5175708                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            89.268408                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          4772370                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.827216                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          421926289                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          4772882                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            88.400738                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      59167640000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.827248                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.827216                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999663                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999663                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          114                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          395                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3          117                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        939581550                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       939581550                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    462027213                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      462027213                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    462027213                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       462027213                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    462027213                       # number of overall hits
-system.cpu0.icache.overall_hits::total      462027213                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5175708                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      5175708                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5175708                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       5175708                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5175708                       # number of overall misses
-system.cpu0.icache.overall_misses::total      5175708                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  57336545500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  57336545500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  57336545500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  57336545500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  57336545500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  57336545500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    467202921                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    467202921                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    467202921                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    467202921                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    467202921                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    467202921                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011078                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011078                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011078                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011078                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011078                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011078                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11078.010100                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 11078.010100                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11078.010100                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 11078.010100                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11078.010100                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 11078.010100                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        858171224                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       858171224                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    421926289                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      421926289                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    421926289                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       421926289                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    421926289                       # number of overall hits
+system.cpu0.icache.overall_hits::total      421926289                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      4772882                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      4772882                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      4772882                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       4772882                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      4772882                       # number of overall misses
+system.cpu0.icache.overall_misses::total      4772882                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  52975952000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  52975952000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  52975952000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  52975952000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  52975952000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  52975952000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    426699171                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    426699171                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    426699171                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    426699171                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    426699171                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    426699171                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011186                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.011186                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011186                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.011186                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011186                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.011186                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11099.363445                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 11099.363445                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11099.363445                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 11099.363445                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11099.363445                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 11099.363445                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -899,252 +894,248 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      5175196                       # number of writebacks
-system.cpu0.icache.writebacks::total          5175196                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      5175708                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      5175708                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      5175708                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      5175708                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      5175708                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      5175708                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      4772370                       # number of writebacks
+system.cpu0.icache.writebacks::total          4772370                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      4772882                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      4772882                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      4772882                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      4772882                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      4772882                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      4772882                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  54748691500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  54748691500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  54748691500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  54748691500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  54748691500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  54748691500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  50589511000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  50589511000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  50589511000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  50589511000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  50589511000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  50589511000                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5954209000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5954209000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   5954209000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   5954209000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011078                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011078                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011078                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.011078                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011078                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.011078                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10578.010100                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10578.010100                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10578.010100                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10578.010100                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10578.010100                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10578.010100                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011186                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011186                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011186                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.011186                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011186                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.011186                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10599.363445                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10599.363445                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10599.363445                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10599.363445                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10599.363445                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10599.363445                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      7857654                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      7857701                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      7230591                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      7230639                       # number of prefetch candidates identified
 system.cpu0.l2cache.prefetcher.pfBufferHit           41                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage      1019611                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements         2391891                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16167.019190                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs          15476667                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs         2407580                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs            6.428309                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       940745                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements         2188465                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16163.582102                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs          14109503                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs         2203636                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs            6.402828                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle      8764179000                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 15278.445219                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    61.058428                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    79.612606                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   747.902937                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.932522                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003727                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004859                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.045648                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.986757                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1309                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023           77                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        14303                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1          143                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          161                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          649                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          356                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           28                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           41                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            8                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          827                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         4392                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6793                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2165                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.079895                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004700                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.872986                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses       371635811                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses      371635811                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       264720                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       157843                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total        422563                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks      3807067                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total      3807067                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      7134877                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      7134877                       # number of WritebackClean hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          457                       # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total          457                       # number of UpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       928109                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       928109                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4693228                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      4693228                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2960524                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total      2960524                       # number of ReadSharedReq hits
-system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       208597                       # number of InvalidateReq hits
-system.cpu0.l2cache.InvalidateReq_hits::total       208597                       # number of InvalidateReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       264720                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker       157843                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      4693228                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data      3888633                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        9004424                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       264720                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker       157843                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      4693228                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data      3888633                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       9004424                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        10067                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         8203                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total        18270                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       246628                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total       246628                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       200453                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total       200453                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           11                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total           11                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data       262909                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total       262909                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       482480                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total       482480                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       947383                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total       947383                       # number of ReadSharedReq misses
-system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       566022                       # number of InvalidateReq misses
-system.cpu0.l2cache.InvalidateReq_misses::total       566022                       # number of InvalidateReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        10067                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker         8203                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst       482480                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data      1210292                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total      1711042                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        10067                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker         8203                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst       482480                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data      1210292                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total      1711042                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    425309500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    392962000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total    818271500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3546049000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total   3546049000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   2066053000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   2066053000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      4661500                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      4661500                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  16748515499                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total  16748515499                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  18800277000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total  18800277000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  39672427000                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total  39672427000                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  62566205500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.InvalidateReq_miss_latency::total  62566205500                       # number of InvalidateReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    425309500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    392962000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst  18800277000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data  56420942499                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total  76039490999                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    425309500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    392962000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst  18800277000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data  56420942499                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total  76039490999                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       274787                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       166046                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total       440833                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3807067                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total      3807067                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      7134877                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      7134877                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       247085                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total       247085                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       200453                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total       200453                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           11                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           11                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1191018                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total      1191018                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5175708                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      5175708                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3907907                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total      3907907                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       774619                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.InvalidateReq_accesses::total       774619                       # number of InvalidateReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       274787                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       166046                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst      5175708                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data      5098925                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total     10715466                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       274787                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       166046                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      5175708                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data      5098925                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total     10715466                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.036636                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.049402                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.041444                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998150                       # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998150                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.tags.occ_blocks::writebacks 15163.258465                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    49.967950                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    74.840251                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   875.515436                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.925492                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.003050                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.004568                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.053437                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.986547                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1542                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023           68                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        13561                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2           58                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          726                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          758                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           36                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           32                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2          590                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         6261                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         6710                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.094116                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.004150                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.827698                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses       339677714                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses      339677714                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       214201                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       132495                       # number of ReadReq hits
+system.cpu0.l2cache.ReadReq_hits::total        346696                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks      3462500                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total      3462500                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      6546722                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      6546722                       # number of WritebackClean hits
+system.cpu0.l2cache.UpgradeReq_hits::cpu0.data          323                       # number of UpgradeReq hits
+system.cpu0.l2cache.UpgradeReq_hits::total          323                       # number of UpgradeReq hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       835467                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total       835467                       # number of ReadExReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4337083                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadCleanReq_hits::total      4337083                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2670834                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total      2670834                       # number of ReadSharedReq hits
+system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       164201                       # number of InvalidateReq hits
+system.cpu0.l2cache.InvalidateReq_hits::total       164201                       # number of InvalidateReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       214201                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker       132495                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst      4337083                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data      3506301                       # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total        8190080                       # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       214201                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.itb.walker       132495                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      4337083                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data      3506301                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       8190080                       # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker         9167                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker         7221                       # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total        16388                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       234409                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total       234409                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       190710                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total       190710                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           31                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total           31                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data       244449                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total       244449                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       435799                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total       435799                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       871525                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total       871525                       # number of ReadSharedReq misses
+system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       555346                       # number of InvalidateReq misses
+system.cpu0.l2cache.InvalidateReq_misses::total       555346                       # number of InvalidateReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker         9167                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker         7221                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst       435799                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data      1115974                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total      1568161                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker         9167                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker         7221                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst       435799                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data      1115974                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total      1568161                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    351604000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    298997000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total    650601000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data   3324963500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total   3324963500                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data   1970779500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total   1970779500                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      6951500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      6951500                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  15779075998                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total  15779075998                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  17377629000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total  17377629000                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  34720917000                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total  34720917000                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data  62263259000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.InvalidateReq_miss_latency::total  62263259000                       # number of InvalidateReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    351604000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    298997000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst  17377629000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data  50499992998                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total  68528222998                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    351604000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    298997000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst  17377629000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data  50499992998                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total  68528222998                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       223368                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       139716                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total       363084                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks      3462500                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total      3462500                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      6546722                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      6546722                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       234732                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total       234732                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       190710                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total       190710                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           31                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           31                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1079916                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total      1079916                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      4772882                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      4772882                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      3542359                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total      3542359                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       719547                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.InvalidateReq_accesses::total       719547                       # number of InvalidateReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       223368                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       139716                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      4772882                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data      4622275                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      9758241                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       223368                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       139716                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      4772882                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data      4622275                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      9758241                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.041040                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.051683                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.045136                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.998624                       # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.998624                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.220743                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.220743                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.093220                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.093220                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.242427                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.242427                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.730710                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.730710                       # miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.036636                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.049402                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.093220                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.237362                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.159680                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.036636                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.049402                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.093220                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.237362                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.159680                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42247.889143                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47904.669024                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44787.712096                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14378.128193                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14378.128193                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10306.919827                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10306.919827                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 423772.727273                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 423772.727273                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63704.610717                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63704.610717                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38965.919831                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38965.919831                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41875.806300                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41875.806300                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 110536.702637                       # average InvalidateReq miss latency
-system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 110536.702637                       # average InvalidateReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42247.889143                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47904.669024                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38965.919831                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46617.628224                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 44440.458504                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42247.889143                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47904.669024                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38965.919831                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46617.628224                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 44440.458504                       # average overall miss latency
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.226359                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.226359                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.091307                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.091307                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.246030                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.246030                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.771799                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.771799                       # miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.041040                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.051683                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.091307                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.241434                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.160701                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.041040                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.051683                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.091307                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.241434                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.160701                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38355.405258                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41406.591885                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39699.841347                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14184.453242                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14184.453242                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10333.907504                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10333.907504                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 224241.935484                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 224241.935484                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64549.562477                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64549.562477                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39875.330141                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39875.330141                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39839.266802                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39839.266802                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 112116.156414                       # average InvalidateReq miss latency
+system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 112116.156414                       # average InvalidateReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38355.405258                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41406.591885                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39875.330141                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45251.944040                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 43699.736824                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38355.405258                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41406.591885                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39875.330141                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45251.944040                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 43699.736824                       # average overall miss latency
 system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -1153,219 +1144,219 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks      1521426                       # number of writebacks
-system.cpu0.l2cache.writebacks::total         1521426                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         5411                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         5411                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data          533                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total          533                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         5944                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         5944                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         5944                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         5944                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        10067                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker         8203                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total        18270                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       721686                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       721686                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       246628                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total       246628                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       200453                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       200453                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           11                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           11                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       257498                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total       257498                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       482480                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       482480                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data       946850                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total       946850                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       566022                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.InvalidateReq_mshr_misses::total       566022                       # number of InvalidateReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        10067                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker         8203                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       482480                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1204348                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total      1705098                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        10067                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       482480                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1204348                       # number of overall MSHR misses
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-system.cpu0.l2cache.overall_mshr_misses::total      2426784                       # number of overall MSHR misses
+system.cpu0.l2cache.writebacks::writebacks      1408018                       # number of writebacks
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        15619                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        58744                       # number of ReadReq MSHR uncacheable
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 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        32098                       # number of overall MSHR uncacheable misses
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-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  38668799279                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7913903000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   7913903000                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   4087252500                       # number of SCUpgradeReq MSHR miss cycles
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-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      4337500                       # number of SCUpgradeFailReq MSHR miss cycles
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-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  14600636999                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  15905397000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  15905397000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  33944380000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  33944380000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  59170079500                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  59170079500                       # number of InvalidateReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    364907500                       # number of demand (read+write) MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    364907500                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  15905397000                       # number of overall MSHR miss cycles
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-system.cpu0.l2cache.overall_mshr_miss_latency::total 103827864778                       # number of overall MSHR miss cycles
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+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  37620512818                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  37620512818                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   7511827000                       # number of UpgradeReq MSHR miss cycles
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+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3867075000                       # number of SCUpgradeReq MSHR miss cycles
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 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2565627500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   8196399000                       # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   2967633500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   5630771500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5237484500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  10868256000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.036636                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.049402                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.041444                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   5730813000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  11361584500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.041040                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.051683                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.045136                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998150                       # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998150                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.998624                       # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.998624                       # mshr miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.216200                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.216200                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.093220                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.093220                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.242291                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.242291                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.730710                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.730710                       # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.036636                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.049402                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.093220                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.236196                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.159125                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.036636                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.049402                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.093220                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.236196                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.221481                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.221481                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.091307                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.091307                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.245879                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.245879                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.771799                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.771799                       # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.041040                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.051683                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.091307                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.240179                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.160107                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.041040                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.051683                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.091307                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.240179                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.226475                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38787.712096                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53581.196364                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32088.420617                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32088.420617                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.078971                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20390.078971                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 394318.181818                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 394318.181818                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56701.943312                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56701.943312                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32965.919831                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32965.919831                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35849.796694                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35849.796694                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 104536.713237                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 104536.713237                       # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32965.919831                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40308.131038                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38214.264224                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32965.919831                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40308.131038                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42784.139329                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229099                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33699.841347                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55879.462450                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32045.813087                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32045.813087                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20277.253421                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20277.253421                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 208951.612903                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 208951.612903                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57464.330352                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57464.330352                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33875.330141                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33875.330141                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33812.007674                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33812.007674                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 106116.156414                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 106116.156414                       # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33875.330141                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38907.773014                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37449.415339                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33875.330141                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38907.773014                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42999.554401                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164263.237083                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139527.424077                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162137.083561                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162137.083561                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165005.344560                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 140200.614655                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165162.149377                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165162.149377                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 163171.677363                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144480.491339                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165086.506885                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145962.621565                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests     22685684                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests     11636633                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          725                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops      1868386                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1868205                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          181                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq        566458                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      9760546                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        16479                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        16479                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty      5331858                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      7134877                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict      2347214                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       886122                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq       438453                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       361903                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       524601                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           85                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          128                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq      1264261                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp      1203854                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5175708                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4797612                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq       779730                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp       774618                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     15612584                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     18673898                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       348811                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       599734                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total         35235027                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    662612564                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    703409885                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1328368                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2198296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total        1369549113                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                    6346450                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples     18158816                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.116500                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.320855                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests     20776945                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests     10662406                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests          659                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops      1726264                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops      1726085                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops          179                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq        488069                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      8911186                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        17968                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        17968                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty      4874700                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      6546722                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict      2139143                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       829102                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq       434919                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       350602                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       501065                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           90                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          138                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq      1159158                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp      1092705                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      4772882                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4419934                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq       726049                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp       719547                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     14404114                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     17037537                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       296236                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       495044                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total         32232931                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    611051348                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    638823901                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1117728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1786944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total        1252779921                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                    5965413                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples     16750116                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.116655                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.321042                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0          16043491     88.35%     88.35% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1           2115144     11.65%    100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2               181      0.00%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0          14796306     88.34%     88.34% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1           1953631     11.66%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2               179      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total      18158816                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy   22462112497                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total      16750116                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy   20546913496                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    223807892                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    219185391                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   7806687000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   7202448000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   8283648998                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   7531952589                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy    182765499                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy    156520499                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy    324947000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy    271676000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1396,69 +1387,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    92112                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong                92112                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         7185                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        70441                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore            5                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        92107                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.086856                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    26.359895                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-511        92106    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                   101882                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               101882                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         8030                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        79527                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            9                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       101873                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     0.078529                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev    25.064580                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511       101872    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::7680-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        92107                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        77631                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 22794.154397                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21108.718713                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 17037.529740                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        76846     98.99%     98.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          174      0.22%     99.21% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          527      0.68%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143           17      0.02%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           28      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           18      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        77631                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -5456316576                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.616394                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.486264                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0    -2093077220     38.36%     38.36% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    -3363239356     61.64%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -5456316576                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        70442     90.74%     90.74% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         7185      9.26%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        77627                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        92112                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total       101873                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        87566                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23519.505287                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21365.105207                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 20825.826742                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535        86337     98.60%     98.60% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071          178      0.20%     98.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          904      1.03%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143           19      0.02%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           55      0.06%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215           12      0.01%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           42      0.05%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           12      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        87566                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples    239339024                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     9.661342                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -2072997220   -866.13%   -866.13% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1     2312336244    966.13%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total    239339024                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        79528     90.83%     90.83% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         8030      9.17%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total        87558                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       101882                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        92112                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        77627                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       101882                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        87558                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        77627                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       169739                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        87558                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       189440                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    76812549                       # DTB read hits
-system.cpu1.dtb.read_misses                     67403                       # DTB read misses
-system.cpu1.dtb.write_hits                   69811450                       # DTB write hits
-system.cpu1.dtb.write_misses                    24709                       # DTB write misses
+system.cpu1.dtb.read_hits                    82176038                       # DTB read hits
+system.cpu1.dtb.read_misses                     74927                       # DTB read misses
+system.cpu1.dtb.write_hits                   74775352                       # DTB write hits
+system.cpu1.dtb.write_misses                    26955                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              39890                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   34729                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              39478                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                   1020                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   37701                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4304                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  4186                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     9295                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                76879952                       # DTB read accesses
-system.cpu1.dtb.write_accesses               69836159                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    10277                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                82250965                       # DTB read accesses
+system.cpu1.dtb.write_accesses               74802307                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        146623999                       # DTB hits
-system.cpu1.dtb.misses                          92112                       # DTB misses
-system.cpu1.dtb.accesses                    146716111                       # DTB accesses
+system.cpu1.dtb.hits                        156951390                       # DTB hits
+system.cpu1.dtb.misses                         101882                       # DTB misses
+system.cpu1.dtb.accesses                    157053272                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1488,236 +1479,236 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    54749                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                54749                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          360                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        49211                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        54749                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          54749    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        54749                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        49571                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 25509.592302                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23251.815503                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 21686.807401                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        48865     98.58%     98.58% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071           34      0.07%     98.64% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          581      1.17%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           14      0.03%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           29      0.06%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           16      0.03%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           25      0.05%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        49571                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    63786                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                63786                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2          574                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        58046                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        63786                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          63786    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        63786                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        58620                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 26694.208461                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 23680.273613                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 26398.773524                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        57379     97.88%     97.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071           45      0.08%     97.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607         1025      1.75%     99.71% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           33      0.06%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           48      0.08%     99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           24      0.04%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           49      0.08%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            9      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        58620                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples  -2103779220                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0    -2103779220    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total  -2103779220                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        49211     99.27%     99.27% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          360      0.73%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        49571                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        58046     99.02%     99.02% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          574      0.98%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        58620                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        54749                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        54749                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        63786                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        63786                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        49571                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        49571                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       104320                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   406021553                       # ITB inst hits
-system.cpu1.itb.inst_misses                     54749                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        58620                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        58620                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       122406                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   435405767                       # ITB inst hits
+system.cpu1.itb.inst_misses                     63786                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                          14                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              39890                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                   1034                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   24319                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              39478                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                   1020                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   26334                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               406076302                       # ITB inst accesses
-system.cpu1.itb.hits                        406021553                       # DTB hits
-system.cpu1.itb.misses                          54749                       # DTB misses
-system.cpu1.itb.accesses                    406076302                       # DTB accesses
-system.cpu1.numCycles                     95205135925                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               435469553                       # ITB inst accesses
+system.cpu1.itb.hits                        435405767                       # DTB hits
+system.cpu1.itb.misses                          63786                       # DTB misses
+system.cpu1.itb.accesses                    435469553                       # DTB accesses
+system.cpu1.numCycles                     95187488343                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   14029                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  405727323                       # Number of instructions committed
-system.cpu1.committedOps                    478325144                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            439907771                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                446670                       # Number of float alu accesses
-system.cpu1.num_func_calls                   24605699                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     61596178                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   439907771                       # number of integer instructions
-system.cpu1.num_fp_insts                       446670                       # number of float instructions
-system.cpu1.num_int_register_reads          637924838                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         348926241                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              708486                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             403472                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           104772444                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          104573998                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    146614371                       # number of memory refs
-system.cpu1.num_load_insts                   76808885                       # Number of load instructions
-system.cpu1.num_store_insts                  69805486                       # Number of store instructions
-system.cpu1.num_idle_cycles              94195407146.248016                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1009728778.751979                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.010606                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.989394                       # Percentage of idle cycles
-system.cpu1.Branches                         90553045                       # Number of branches fetched
+system.cpu1.kern.inst.quiesce                   14345                       # number of quiesce instructions executed
+system.cpu1.committedInsts                  435108521                       # Number of instructions committed
+system.cpu1.committedOps                    512619121                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            471360298                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                517037                       # Number of float alu accesses
+system.cpu1.num_func_calls                   26310177                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     66181606                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   471360298                       # number of integer instructions
+system.cpu1.num_fp_insts                       517037                       # number of float instructions
+system.cpu1.num_int_register_reads          683625420                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         373659475                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              819092                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             470852                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           112718016                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          112414585                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    156939308                       # number of memory refs
+system.cpu1.num_load_insts                   82171340                       # Number of load instructions
+system.cpu1.num_store_insts                  74767968                       # Number of store instructions
+system.cpu1.num_idle_cycles              94109373851.176025                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1078114491.823977                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.011326                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.988674                       # Percentage of idle cycles
+system.cpu1.Branches                         97258514                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                330876771     69.13%     69.13% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1002715      0.21%     69.34% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    57816      0.01%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             67767      0.01%     69.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.37% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.37% # Class of executed instruction
-system.cpu1.op_class::MemRead                76808885     16.05%     85.42% # Class of executed instruction
-system.cpu1.op_class::MemWrite               69805486     14.58%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                354775953     69.17%     69.17% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1066461      0.21%     69.38% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    59336      0.01%     69.39% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.39% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             75375      0.01%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.40% # Class of executed instruction
+system.cpu1.op_class::MemRead                82171340     16.02%     85.42% # Class of executed instruction
+system.cpu1.op_class::MemWrite               74767968     14.58%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 478619483                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements          4731492                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          440.215275                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs          141682703                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs          4732003                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            29.941381                       # Average number of references to valid blocks.
+system.cpu1.op_class::total                 512916476                       # Class of executed instruction
+system.cpu1.dcache.tags.replacements          5113111                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          443.711015                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs          151630595                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs          5113623                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.652283                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle     8408412782000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   440.215275                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.859795                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.859795                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          405                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses        297963795                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses       297963795                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data     71617652                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total       71617652                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data     66171444                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total      66171444                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data       174206                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total       174206                       # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data       185116                       # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total       185116                       # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1590024                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total      1590024                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1548743                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total      1548743                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data    137789096                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total       137789096                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data    137963302                       # number of overall hits
-system.cpu1.dcache.overall_hits::total      137963302                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data      2694357                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total      2694357                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1213090                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1213090                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data       558664                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total       558664                       # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data       466794                       # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total       466794                       # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       154053                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total       154053                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data       194127                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total       194127                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      3907447                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       3907447                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      4466111                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      4466111                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  40157954500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total  40157954500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  28157091500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  28157091500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  20750751000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total  20750751000                       # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2380134500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total   2380134500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5345117000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total   5345117000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      6929500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      6929500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  68315046000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  68315046000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  68315046000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  68315046000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data     74312009                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total     74312009                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data     67384534                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total     67384534                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       732870                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total       732870                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       651910                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total       651910                       # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1744077                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total      1744077                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1742870                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total      1742870                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data    141696543                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total    141696543                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data    142429413                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total    142429413                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036257                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.036257                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018002                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.018002                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.762296                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.762296                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.716041                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total     0.716041                       # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.088329                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.088329                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.111384                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.111384                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027576                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.027576                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031357                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.031357                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14904.466817                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14904.466817                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23211.049057                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 23211.049057                       # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 44453.765473                       # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 44453.765473                       # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15450.101588                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15450.101588                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27534.124568                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27534.124568                       # average StoreCondReq miss latency
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   443.711015                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.866623                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.866623                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          402                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses        319002554                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses       319002554                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data     76632055                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total       76632055                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data     70902064                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total      70902064                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data       183506                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total       183506                       # number of SoftPFReq hits
+system.cpu1.dcache.WriteLineReq_hits::cpu1.data       192465                       # number of WriteLineReq hits
+system.cpu1.dcache.WriteLineReq_hits::total       192465                       # number of WriteLineReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1673719                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total      1673719                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1647145                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total      1647145                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data    147534119                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total       147534119                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data    147717625                       # number of overall hits
+system.cpu1.dcache.overall_hits::total      147717625                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data      2895739                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total      2895739                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1291835                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1291835                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data       599128                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total       599128                       # number of SoftPFReq misses
+system.cpu1.dcache.WriteLineReq_misses::cpu1.data       515597                       # number of WriteLineReq misses
+system.cpu1.dcache.WriteLineReq_misses::total       515597                       # number of WriteLineReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       170116                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total       170116                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data       195350                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total       195350                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      4187574                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       4187574                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      4786702                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      4786702                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  44430252500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total  44430252500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  29275459500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  29275459500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  21176769000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.WriteLineReq_miss_latency::total  21176769000                       # number of WriteLineReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   2717509500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total   2717509500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   5539928000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total   5539928000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      5730000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      5730000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  73705712000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  73705712000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  73705712000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  73705712000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data     79527794                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total     79527794                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data     72193899                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total     72193899                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       782634                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total       782634                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       708062                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total       708062                       # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      1843835                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total      1843835                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      1842495                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total      1842495                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data    151721693                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total    151721693                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data    152504327                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total    152504327                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036412                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.036412                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.017894                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.017894                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.765528                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.765528                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.728181                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total     0.728181                       # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.092262                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.092262                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106025                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106025                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027600                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.027600                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.031387                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.031387                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.320824                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.320824                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22661.918511                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22661.918511                       # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41072.327806                       # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41072.327806                       # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.449787                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.449787                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28358.986435                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28358.986435                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17483.294335                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17483.294335                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.316191                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15296.316191                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17601.053020                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17601.053020                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15398.015586                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15398.015586                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1726,157 +1717,158 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks      4731492                       # number of writebacks
-system.cpu1.dcache.writebacks::total          4731492                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        13909                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        13909                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          323                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total          323                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        44168                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        44168                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data        14232                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total        14232                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data        14232                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total        14232                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2680448                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total      2680448                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1212767                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total      1212767                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       558664                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total       558664                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       466794                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total       466794                       # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       109885                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total       109885                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       194127                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total       194127                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data      3893215                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total      3893215                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data      4451879                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total      4451879                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        23611                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total        23611                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        22620                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total        22620                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        46231                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total        46231                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  36382655000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total  36382655000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26928760500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26928760500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12609688500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  12609688500                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  20283957000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  20283957000                       # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1540230500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1540230500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5151064000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5151064000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      6855500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      6855500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  63311415500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total  63311415500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  75921104000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total  75921104000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   4287453000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   4287453000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   4160988000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   4160988000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   8448441000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   8448441000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036070                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036070                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017998                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017998                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.762296                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.762296                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.716041                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.716041                       # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063005                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.063005                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.111384                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.111384                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027476                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.027476                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031257                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.031257                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13573.348560                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13573.348560                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22204.397465                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22204.397465                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22571.149206                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22571.149206                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 43453.765473                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 43453.765473                       # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14016.749329                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14016.749329                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26534.505762                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26534.505762                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks      5113111                       # number of writebacks
+system.cpu1.dcache.writebacks::total          5113111                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        16657                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        16657                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data          402                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total          402                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        46028                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        46028                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data        17059                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total        17059                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data        17059                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total        17059                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      2879082                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total      2879082                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1291433                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total      1291433                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       599128                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total       599128                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       515597                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::total       515597                       # number of WriteLineReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       124088                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total       124088                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       195350                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total       195350                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data      4170515                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total      4170515                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data      4769643                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total      4769643                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        21793                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total        21793                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        20416                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total        20416                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        42209                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total        42209                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  40268780500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total  40268780500                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  27960090500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total  27960090500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  13604579000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  13604579000                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  20661172000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  20661172000                       # number of WriteLineReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1751690500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1751690500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   5344637000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   5344637000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      5671000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      5671000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  68228871000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total  68228871000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  81833450000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total  81833450000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   4030825000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   4030825000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3797015500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total   3797015500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   7827840500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   7827840500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036202                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036202                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.017888                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.017888                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.765528                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.765528                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.728181                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.728181                       # mshr miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.067299                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.067299                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106025                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106025                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027488                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.027488                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031275                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.031275                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.673704                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.673704                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21650.438312                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21650.438312                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22707.299609                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22707.299609                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40072.327806                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40072.327806                       # average WriteLineReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14116.518116                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14116.518116                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27359.288457                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27359.288457                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16261.987971                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16261.987971                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17053.721361                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17053.721361                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181587.099233                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181587.099233                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183951.724138                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183951.724138                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182744.067833                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182744.067833                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16359.819111                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16359.819111                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17157.143627                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17157.143627                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184959.620061                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184959.620061                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 185982.342281                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 185982.342281                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185454.298846                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 185454.298846                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements          4831573                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          495.969883                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs          401189463                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs          4832085                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            83.026160                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements          5153049                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          495.966911                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs          430252201                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs          5153561                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            83.486390                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle     8408381586000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   495.969883                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.968691                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.968691                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   495.966911                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.968685                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.968685                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1          278                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          132                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses        816875196                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses       816875196                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst    401189463                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total      401189463                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst    401189463                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total       401189463                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst    401189463                       # number of overall hits
-system.cpu1.icache.overall_hits::total      401189463                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst      4832090                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total      4832090                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst      4832090                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total       4832090                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst      4832090                       # number of overall misses
-system.cpu1.icache.overall_misses::total      4832090                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  52408341000                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  52408341000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  52408341000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  52408341000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  52408341000                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  52408341000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst    406021553                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total    406021553                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst    406021553                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total    406021553                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst    406021553                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total    406021553                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011901                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.011901                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011901                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.011901                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011901                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.011901                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10845.895047                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 10845.895047                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10845.895047                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 10845.895047                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10845.895047                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 10845.895047                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses        875965100                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses       875965100                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst    430252201                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total      430252201                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst    430252201                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total       430252201                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst    430252201                       # number of overall hits
+system.cpu1.icache.overall_hits::total      430252201                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst      5153566                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total      5153566                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst      5153566                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total       5153566                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst      5153566                       # number of overall misses
+system.cpu1.icache.overall_misses::total      5153566                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  55699016000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  55699016000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  55699016000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  55699016000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  55699016000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  55699016000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst    435405767                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total    435405767                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst    435405767                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total    435405767                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst    435405767                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total    435405767                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.011836                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.011836                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.011836                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.011836                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.011836                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.011836                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10807.859257                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 10807.859257                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10807.859257                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 10807.859257                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10807.859257                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 10807.859257                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1885,252 +1877,252 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks      4831573                       # number of writebacks
-system.cpu1.icache.writebacks::total          4831573                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      4832090                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total      4832090                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst      4832090                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total      4832090                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst      4832090                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total      4832090                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks      5153049                       # number of writebacks
+system.cpu1.icache.writebacks::total          5153049                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5153566                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total      5153566                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst      5153566                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total      5153566                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst      5153566                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total      5153566                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          110                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          110                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  49992296000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total  49992296000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  49992296000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total  49992296000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  49992296000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total  49992296000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  53122233000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total  53122233000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  53122233000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total  53122233000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  53122233000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total  53122233000                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     14799500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     14799500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     14799500                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total     14799500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011901                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011901                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011901                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.011901                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011901                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.011901                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10345.895047                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10345.895047                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10345.895047                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 10345.895047                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10345.895047                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 10345.895047                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011836                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.011836                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.011836                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.011836                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.011836                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.011836                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10307.859257                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10307.859257                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10307.859257                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 10307.859257                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10307.859257                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 10307.859257                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134540.909091                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134540.909091                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued      6380299                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified      6380331                       # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit           28                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.num_hwpf_issued      6859303                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified      6859383                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit           70                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage       802101                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements         1778912                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       13269.685648                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs          14051315                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs         1794926                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs            7.828353                       # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle    10084696105000                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 12213.003078                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    33.894206                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    34.650770                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   988.137594                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.745423                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002069                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.002115                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.060311                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.809917                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1110                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           86                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14818                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          249                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          669                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          184                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           13                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           72                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1          972                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4464                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         8114                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1200                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.067749                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005249                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.904419                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses       324313053                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses      324313053                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       211999                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       140481                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total        352480                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks      2988895                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total      2988895                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks      6573071                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total      6573071                       # number of WritebackClean hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          239                       # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total          239                       # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data       778234                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total       778234                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4410501                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total      4410501                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2517428                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total      2517428                       # number of ReadSharedReq hits
-system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       200602                       # number of InvalidateReq hits
-system.cpu1.l2cache.InvalidateReq_hits::total       200602                       # number of InvalidateReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       211999                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker       140481                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst      4410501                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data      3295662                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total        8058643                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       211999                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker       140481                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst      4410501                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data      3295662                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total       8058643                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9285                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         7506                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total        16791                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       201343                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total       201343                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       194101                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total       194101                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           26                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total           26                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data       235513                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total       235513                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       421589                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total       421589                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       831569                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total       831569                       # number of ReadSharedReq misses
-system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       263822                       # number of InvalidateReq misses
-system.cpu1.l2cache.InvalidateReq_misses::total       263822                       # number of InvalidateReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker         9285                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker         7506                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst       421589                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data      1067082                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total      1505462                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker         9285                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker         7506                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst       421589                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data      1067082                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total      1505462                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    349092500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    301051000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total    650143500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3162483500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total   3162483500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1860693500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1860693500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      6744500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      6744500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  12440298999                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total  12440298999                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  16234081000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total  16234081000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  29105216000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total  29105216000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  18219271500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.InvalidateReq_miss_latency::total  18219271500                       # number of InvalidateReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    349092500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    301051000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst  16234081000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data  41545514999                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total  58429739499                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    349092500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    301051000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst  16234081000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data  41545514999                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total  58429739499                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       221284                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       147987                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total       369271                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks      2988895                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total      2988895                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks      6573071                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total      6573071                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       201582                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total       201582                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       194101                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total       194101                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           26                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           26                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1013747                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total      1013747                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4832090                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total      4832090                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3348997                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total      3348997                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       464424                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.InvalidateReq_accesses::total       464424                       # number of InvalidateReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       221284                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       147987                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst      4832090                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data      4362744                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total      9564105                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       221284                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       147987                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst      4832090                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data      4362744                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total      9564105                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.041960                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.050721                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.045471                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.998814                       # miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.998814                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.prefetcher.pfSpanPage       859985                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements         1911702                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       13239.490812                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs          15125743                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs         1927829                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs            7.845998                       # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.warmup_cycle    10087167671000                       # Cycle when the warmup percentage was hit.
+system.cpu1.l2cache.tags.occ_blocks::writebacks 12280.954827                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    52.921711                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    73.687685                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   831.926589                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.749570                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.003230                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.004498                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.050777                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.808074                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022         1375                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           54                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14698                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           12                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          186                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          718                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          459                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           36                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1004                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         4268                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         6358                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         2989                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.083923                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.003296                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.897095                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses       347994589                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses      347994589                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       237538                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       166264                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total        403802                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks      3233759                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total      3233759                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks      7031230                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total      7031230                       # number of WritebackClean hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data          362                       # number of UpgradeReq hits
+system.cpu1.l2cache.UpgradeReq_hits::total          362                       # number of UpgradeReq hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data       841313                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total       841313                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4702873                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total      4702873                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2730195                       # number of ReadSharedReq hits
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+system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       242884                       # number of InvalidateReq hits
+system.cpu1.l2cache.InvalidateReq_hits::total       242884                       # number of InvalidateReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       237538                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker       166264                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.inst      4702873                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.data      3571508                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total        8678183                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       237538                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker       166264                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst      4702873                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data      3571508                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total       8678183                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker         9658                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         8172                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total        17830                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       204136                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total       204136                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       195335                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total       195335                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data           15                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.SCUpgradeFailReq_misses::total           15                       # number of SCUpgradeFailReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data       248244                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total       248244                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       450693                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total       450693                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       872103                       # number of ReadSharedReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::total       872103                       # number of ReadSharedReq misses
+system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       270299                       # number of InvalidateReq misses
+system.cpu1.l2cache.InvalidateReq_misses::total       270299                       # number of InvalidateReq misses
+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker         9658                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.itb.walker         8172                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.inst       450693                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data      1120347                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total      1588870                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker         9658                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker         8172                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst       450693                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data      1120347                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total      1588870                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    420391500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    400950500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total    821342000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data   3230006000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total   3230006000                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data   1996070000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total   1996070000                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      5582500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      5582500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  12845706999                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total  12845706999                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  17128169000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total  17128169000                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  32431804500                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total  32431804500                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data  18248876500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.InvalidateReq_miss_latency::total  18248876500                       # number of InvalidateReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    420391500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    400950500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst  17128169000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data  45277511499                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total  63227022499                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    420391500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    400950500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst  17128169000                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data  45277511499                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total  63227022499                       # number of overall miss cycles
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+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       174436                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total       421632                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3233759                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total      3233759                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks      7031230                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total      7031230                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       204498                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total       204498                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       195335                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total       195335                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data           15                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeFailReq_accesses::total           15                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1089557                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total      1089557                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5153566                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total      5153566                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3602298                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total      3602298                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       513183                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.InvalidateReq_accesses::total       513183                       # number of InvalidateReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       247196                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       174436                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst      5153566                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data      4691855                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total     10267053                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       247196                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       174436                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst      5153566                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data      4691855                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total     10267053                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.039070                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.046848                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.042288                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.998230                       # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.998230                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.232319                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.232319                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.087248                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.087248                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.248304                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.248304                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.568063                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.568063                       # miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.041960                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.050721                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.087248                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.244590                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.157408                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.041960                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.050721                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.087248                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.244590                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.157408                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37597.469036                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40108.046896                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 38719.760586                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15706.945362                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15706.945362                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  9586.212848                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  9586.212848                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 259403.846154                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 259403.846154                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52822.132957                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52822.132957                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38506.889411                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38506.889411                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35000.361966                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35000.361966                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69058.954522                       # average InvalidateReq miss latency
-system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69058.954522                       # average InvalidateReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37597.469036                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40108.046896                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38506.889411                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38933.760479                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 38811.832845                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37597.469036                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40108.046896                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38506.889411                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38933.760479                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 38811.832845                       # average overall miss latency
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.227839                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.227839                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.087453                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.087453                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.242096                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.242096                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.526711                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.526711                       # miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.039070                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.046848                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.087453                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.238786                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.154754                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.039070                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.046848                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.087453                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.238786                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.154754                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 43527.800787                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 49063.937837                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 46065.171060                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15822.814202                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15822.814202                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10218.701206                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10218.701206                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 372166.666667                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 372166.666667                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51746.293965                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51746.293965                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38004.071508                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38004.071508                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37188.043729                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37188.043729                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 67513.666347                       # average InvalidateReq miss latency
+system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 67513.666347                       # average InvalidateReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 43527.800787                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 49063.937837                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38004.071508                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40413.828483                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 39793.704015                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 43527.800787                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 49063.937837                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38004.071508                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40413.828483                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 39793.704015                       # average overall miss latency
 system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
@@ -2139,228 +2131,227 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks       983057                       # number of writebacks
-system.cpu1.l2cache.writebacks::total          983057                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         3912                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total         3912                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data          475                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          475                       # number of ReadSharedReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            1                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.InvalidateReq_mshr_hits::total            1                       # number of InvalidateReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4387                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total         4387                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data         4387                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total         4387                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker         9285                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         7506                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total        16791                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       603476                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total       603476                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       201343                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total       201343                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       194101                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       194101                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data           26                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total           26                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       231601                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total       231601                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       421589                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       421589                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       831094                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       831094                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       263821                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.InvalidateReq_mshr_misses::total       263821                       # number of InvalidateReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker         9285                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         7506                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       421589                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1062695                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total      1501075                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker         9285                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         7506                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       421589                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1062695                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       603476                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total      2104551                       # number of overall MSHR misses
+system.cpu1.l2cache.writebacks::writebacks      1066343                       # number of writebacks
+system.cpu1.l2cache.writebacks::total         1066343                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data         3931                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total         3931                       # number of ReadExReq MSHR hits
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+system.cpu1.l2cache.ReadSharedReq_mshr_hits::total          513                       # number of ReadSharedReq MSHR hits
+system.cpu1.l2cache.demand_mshr_hits::cpu1.data         4444                       # number of demand (read+write) MSHR hits
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+system.cpu1.l2cache.InvalidateReq_mshr_misses::total       270299                       # number of InvalidateReq MSHR misses
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+system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1115903                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total      2228915                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        23611                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        23721                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        22620                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        22620                       # number of WriteReq MSHR uncacheable
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 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        46231                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        46341                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    293382500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    256015000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    549397500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  27540952434                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  27540952434                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   6429356000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   6429356000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3693933999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3693933999                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      6300500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      6300500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data  10580800999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total  10580800999                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  13704547000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  13704547000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  24076200000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  24076200000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  16636263000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  16636263000                       # number of InvalidateReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    293382500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    256015000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  13704547000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  34657000999                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total  48910945499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    293382500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    256015000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  13704547000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  34657000999                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  27540952434                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total  76451897933                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        42209                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        42319                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    362443500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    351918500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    714362000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  28219162309                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  28219162309                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   6506833500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   6506833500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   3878333500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   3878333500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      5228500                       # number of SCUpgradeFailReq MSHR miss cycles
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+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  14424011000                       # number of ReadCleanReq MSHR miss cycles
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+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  27157045000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data  16627082500                       # number of InvalidateReq MSHR miss cycles
+system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total  16627082500                       # number of InvalidateReq MSHR miss cycles
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+system.cpu1.l2cache.overall_mshr_miss_latency::total  81437970308                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     13974500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   4098070000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   4112044500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3990752000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3990752000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3856157500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3870132000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data   3643453500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total   3643453500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     13974500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   8088822000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   8102796500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.041960                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.050721                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.045471                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   7499611000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   7513585500                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.039070                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.046848                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.042288                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.998814                       # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.998814                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.998230                       # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.998230                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.228460                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.228460                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.087248                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.087248                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.248162                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.248162                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.568061                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.568061                       # mshr miss rate for InvalidateReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.041960                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.050721                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.087248                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.243584                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.156949                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.041960                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.050721                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.087248                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.243584                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.224231                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.224231                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.087453                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.087453                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.241954                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.241954                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.526711                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.526711                       # mshr miss rate for InvalidateReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.039070                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.046848                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.087453                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.237838                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.154321                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.039070                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.046848                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.087453                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.237838                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.220047                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.760586                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45637.195902                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31932.354241                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31932.354241                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19030.989016                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19030.989016                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242326.923077                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242326.923077                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.471993                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.471993                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32506.889411                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32506.889411                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28969.286266                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28969.286266                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63058.903575                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63058.903575                       # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32506.889411                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32612.368553                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32583.945172                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32506.889411                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32612.368553                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36326.940014                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.217094                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 40065.171060                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43785.328080                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31874.992652                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31874.992652                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19854.780249                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19854.780249                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 348566.666667                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 348566.666667                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44710.637580                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44710.637580                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32004.071508                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32004.071508                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31158.050230                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31158.050230                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61513.666347                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61513.666347                       # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32004.071508                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34125.219664                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33588.698998                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32004.071508                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34125.219664                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36537.046190                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173566.134429                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173350.385734                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176425.817860                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176425.817860                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176944.775845                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176694.151486                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178460.692594                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178460.692594                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174965.326296                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174851.567726                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 177678.007060                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 177546.385784                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests     19832170                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10173061                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1095                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops      1632026                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1631848                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          178                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq        456067                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp      8724452                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq        22620                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp        22620                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty      3978006                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean      6573071                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict      2099842                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq       741149                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq       395876                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       358205                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp       460652                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           80                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          128                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq      1084167                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp      1021480                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4832090                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4231593                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq       474723                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp       464424                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14495311                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     15429373                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       311743                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       489874                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total         30726301                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    618432504                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    588237954                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1183896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1770272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total        1209624626                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                    5375046                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples     15685523                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.117781                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.322383                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests     21257827                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests     10899393                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1168                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops      1702072                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops      1701871                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops          201                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq        509534                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp      9349922                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq        20416                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp        20416                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty      4305236                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean      7031230                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict      2216107                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq       785182                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq       389899                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       353464                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp       462412                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           94                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          138                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq      1157273                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp      1096575                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5153566                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4436249                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq       522065                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp       513183                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     15459725                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     16561050                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       365076                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       544187                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total         32930038                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    659580536                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    633491086                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1395488                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1977568                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total        1296444678                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                    5547167                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples     16615326                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.116559                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.320932                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0          13838252     88.22%     88.22% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1           1847093     11.78%    100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2               178      0.00%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0          14678862     88.35%     88.35% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1           1936263     11.65%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2               201      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total      15685523                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy   19622729498                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total      16615326                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy   21053645498                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy    175341179                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy    168856163                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy   7248245000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy   7730459000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy   7009474930                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy   7526670911                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy    163756499                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy    190640499                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy    268590000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy    296991000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40469                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40469                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              137017                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             137017                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47986                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                40402                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40402                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136652                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136652                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47834                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2369,19 +2360,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29808                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       123128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231764                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231764                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122768                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231260                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231260                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  354972                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48006                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  354108                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47854                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2390,25 +2379,24 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17703                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       156143                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7355408                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7355408                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155875                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339056                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7339056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7513637                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             37181500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7497017                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             37033500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                12500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               319500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy                 8500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                 8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                8500                       # Layer occupancy (ticks)
@@ -2421,86 +2409,82 @@ system.iobus.reqLayer16.occupancy               13000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            26640000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            26450500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              168000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            37419000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            37419000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           565570401                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              122000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           566572505                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            93098000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            92847000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           148204000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147956000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115869                       # number of replacements
-system.iocache.tags.tagsinuse               11.294988                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      4                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115885                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000035                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         9206093766000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.821408                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     7.473580                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.238838                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.467099                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.705937                       # Average percentage of cache occupancy
+system.iocache.tags.replacements               115605                       # number of replacements
+system.iocache.tags.tagsinuse               11.294118                       # Cycle average of tags in use
+system.iocache.tags.total_refs                     10                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs               115621                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                 0.000086                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         9206098021000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.822126                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     7.471992                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.238883                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.466999                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.705882                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1043293                       # Number of tag accesses
-system.iocache.tags.data_accesses             1043293                       # Number of data accesses
+system.iocache.tags.tag_accesses              1041013                       # Number of tag accesses
+system.iocache.tags.data_accesses             1041013                       # Number of data accesses
+system.iocache.WriteLineReq_hits::realview.ide            5                       # number of WriteLineReq hits
+system.iocache.WriteLineReq_hits::total             5                       # number of WriteLineReq hits
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8898                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8935                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8902                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8939                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106984                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106984                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::realview.ide       106723                       # number of WriteLineReq misses
+system.iocache.WriteLineReq_misses::total       106723                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8898                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8938                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8902                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8942                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8898                       # number of overall misses
-system.iocache.overall_misses::total             8938                       # number of overall misses
+system.iocache.overall_misses::realview.ide         8902                       # number of overall misses
+system.iocache.overall_misses::total             8942                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5199500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1681517592                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1686717092                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1679170514                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1684370014                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  14021691413                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  14021691413                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13974494387                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13974494387                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5568500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1681517592                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1687086092                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1679170514                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1684739014                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5568500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1681517592                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1687086092                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1679170514                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1684739014                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8898                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8935                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8902                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8939                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106984                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106984                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
+system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8898                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8938                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8902                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8942                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8898                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8938                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8902                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8942                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::realview.ide     0.999953                       # miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_miss_rate::total     0.999953                       # miss rate for WriteLineReq accesses
 system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
@@ -2508,61 +2492,61 @@ system.iocache.overall_miss_rate::realview.ethernet            1
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 188977.027647                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 188776.395299                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 188628.455853                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 188429.356080                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 131063.443253                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 131063.443253                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130941.731276                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130941.731276                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 188977.027647                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 188754.317744                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 188628.455853                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 188407.404831                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 188977.027647                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 188754.317744                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         36073                       # number of cycles access was blocked
+system.iocache.overall_avg_miss_latency::realview.ide 188628.455853                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 188407.404831                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         35755                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3617                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3742                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.973182                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.555051                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks          106957                       # number of writebacks
-system.iocache.writebacks::total               106957                       # number of writebacks
+system.iocache.writebacks::writebacks          106695                       # number of writebacks
+system.iocache.writebacks::total               106695                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8898                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8935                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8902                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8939                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106984                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106984                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide       106723                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total       106723                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8898                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8938                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8902                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8942                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8898                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8938                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         8902                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8942                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3349500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1236617592                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1239967092                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1234070514                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1237420014                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8672491413                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8672491413                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8638344387                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8638344387                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3568500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1236617592                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1240186092                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1234070514                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1237639014                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3568500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1236617592                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1240186092                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1234070514                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1237639014                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.999953                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.999953                       # mshr miss rate for WriteLineReq accesses
 system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
@@ -2570,613 +2554,612 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet            1
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138977.027647                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 138776.395299                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138628.455853                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 138429.356080                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 81063.443253                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 81063.443253                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80941.731276                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80941.731276                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 138977.027647                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 138754.317744                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 138628.455853                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 138407.404831                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 138977.027647                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 138754.317744                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 138628.455853                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 138407.404831                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1210264                       # number of replacements
-system.l2c.tags.tagsinuse                62755.466878                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    5212344                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1269955                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     4.104353                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1201728                       # number of replacements
+system.l2c.tags.tagsinuse                62776.329461                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    5149298                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1259663                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     4.087838                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   23285.968480                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   218.650031                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   386.944281                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4588.836094                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    10476.813165                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 13833.010748                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    53.974082                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    79.219380                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3039.104298                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3132.206690                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  3660.739630                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.355316                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003336                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.005904                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.070020                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.159863                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.211075                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000824                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.001209                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.046373                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.047794                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.055858                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.957572                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        10565                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023          231                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        48895                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1           43                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          159                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         1447                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4         8916                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          229                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1774                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3        10274                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        36522                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022     0.161209                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023     0.003525                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.746078                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 66950820                       # Number of tag accesses
-system.l2c.tags.data_accesses                66950820                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks      2504481                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         2504481                       # number of WritebackDirty hits
-system.l2c.UpgradeReq_hits::cpu0.data          166895                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data          113960                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total              280855                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data         38875                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data         34247                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total             73122                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           158326                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           166214                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               324540                       # number of ReadExReq hits
-system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         5191                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4009                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.inst       435451                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       562405                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       296765                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.dtb.walker         5208                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4285                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.inst       382834                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       480125                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       262665                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          2438938                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          5191                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4009                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              435451                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              720731                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher       296765                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5208                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          4285                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              382834                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              646339                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher       262665                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2763478                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         5191                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4009                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             435451                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             720731                       # number of overall hits
-system.l2c.overall_hits::cpu0.l2cache.prefetcher       296765                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5208                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         4285                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             382834                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             646339                       # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher       262665                       # number of overall hits
-system.l2c.overall_hits::total                2763478                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data         67422                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         57259                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total            124681                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data        14532                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data        11014                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total           25546                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         480698                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         148334                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             629032                       # number of ReadExReq misses
-system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         1519                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.itb.walker         1645                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.inst        47029                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       136142                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       207239                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         1062                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1011                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.inst        38755                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data        73388                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       139305                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         647095                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1519                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1645                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             47029                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            616840                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.l2cache.prefetcher       207239                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         1062                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         1011                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             38755                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            221722                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher       139305                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1276127                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1519                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1645                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            47029                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           616840                       # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher       207239                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         1062                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         1011                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            38755                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           221722                       # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher       139305                       # number of overall misses
-system.l2c.overall_misses::total              1276127                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data    993921500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data    971150500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total   1965072000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data    192356500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data    170135500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total    362492000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  63553941500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  19410172500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  82964114000                       # number of ReadExReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    210107500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    226821000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6321092000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  18616948500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  33395811187                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    146053000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    143461000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5220292500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  10187553500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  22750846819                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  97218987006                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    210107500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    226821000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   6321092000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  82170890000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  33395811187                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    146053000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    143461000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   5220292500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  29597726000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  22750846819                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total    180183101006                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    210107500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    226821000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   6321092000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  82170890000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  33395811187                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    146053000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    143461000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   5220292500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  29597726000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  22750846819                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total   180183101006                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks      2504481                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      2504481                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data       234317                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data       171219                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total          405536                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data        53407                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data        45261                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total         98668                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       639024                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       314548                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           953572                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         6710                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         5654                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.inst       482480                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       698547                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       504004                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         6270                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         5296                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.inst       421589                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       553513                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       401970                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      3086033                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         6710                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         5654                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          482480                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1337571                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.l2cache.prefetcher       504004                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         6270                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5296                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          421589                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          868061                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.l2cache.prefetcher       401970                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             4039605                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         6710                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         5654                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         482480                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1337571                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.l2cache.prefetcher       504004                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         6270                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5296                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         421589                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         868061                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.l2cache.prefetcher       401970                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            4039605                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.287738                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.334420                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.307447                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.272099                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.243344                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.258909                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.752238                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.471578                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.659659                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.226379                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.290944                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.097473                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.194893                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.169378                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.190899                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.091926                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.132586                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.209685                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.226379                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.290944                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.097473                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.461164                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.169378                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.190899                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.091926                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.255422                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.315904                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.226379                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.290944                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.097473                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.461164                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.169378                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.190899                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.091926                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.255422                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.315904                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14741.797929                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16960.661206                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 15760.797555                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13236.753372                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15447.203559                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 14189.775307                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 132211.786818                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130854.507395                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 131891.722520                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138319.618170                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 137885.106383                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134408.386315                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136746.547722                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 137526.365348                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141900.098912                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134699.845181                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138817.701804                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 150239.125640                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138319.618170                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 137885.106383                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 134408.386315                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 133212.648337                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137526.365348                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141900.098912                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 134699.845181                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 133490.253561                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 141195.273673                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138319.618170                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 137885.106383                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 134408.386315                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 133212.648337                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137526.365348                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141900.098912                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 134699.845181                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 133490.253561                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 141195.273673                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs               366                       # number of cycles access was blocked
+system.l2c.tags.occ_blocks::writebacks   23700.762045                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   102.528322                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   175.969290                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4011.755779                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     5217.555279                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher  7227.978697                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   166.263944                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   281.111554                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3722.000784                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     8039.407020                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10130.996747                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.361645                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001564                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.002685                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.061215                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.079614                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.110290                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002537                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.004289                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.056793                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.122672                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.154587                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.957891                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1022         9737                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1023          265                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        47933                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::2           59                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::3          277                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1022::4         9401                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          264                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          129                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1658                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5230                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        40901                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1022     0.148575                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1023     0.004044                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.731400                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 66235328                       # Number of tag accesses
+system.l2c.tags.data_accesses                66235328                       # Number of data accesses
+system.l2c.WritebackDirty_hits::writebacks      2474359                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         2474359                       # number of WritebackDirty hits
+system.l2c.UpgradeReq_hits::cpu0.data          150616                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data          127305                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total              277921                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data         34718                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data         37539                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total             72257                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           146279                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data           167990                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               314269                       # number of ReadExReq hits
+system.l2c.ReadSharedReq_hits::cpu0.dtb.walker         4627                       # number of ReadSharedReq hits
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+system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       291033                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          2399649                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          4627                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu0.inst              390104                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              660168                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.data              684444                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.l2cache.prefetcher       291033                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2713918                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         4627                       # number of overall hits
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+system.l2c.overall_hits::cpu1.l2cache.prefetcher       291033                       # number of overall hits
+system.l2c.overall_hits::total                2713918                       # number of overall hits
+system.l2c.UpgradeReq_misses::cpu0.data         62469                       # number of UpgradeReq misses
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+system.l2c.UpgradeReq_misses::total            119955                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data        13684                       # number of SCUpgradeReq misses
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+system.l2c.SCUpgradeReq_misses::total           26593                       # number of SCUpgradeReq misses
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+system.l2c.ReadExReq_misses::total             625555                       # number of ReadExReq misses
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+system.l2c.ReadSharedReq_misses::cpu0.data       111052                       # number of ReadSharedReq misses
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+system.l2c.ReadSharedReq_misses::total         640180                       # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker         1085                       # number of demand (read+write) misses
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+system.l2c.demand_misses::cpu0.data            588429                       # number of demand (read+write) misses
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+system.l2c.demand_misses::cpu1.data            240248                       # number of demand (read+write) misses
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+system.l2c.overall_misses::cpu0.dtb.walker         1085                       # number of overall misses
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+system.l2c.UpgradeReq_miss_latency::cpu1.data   1025251000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total   1953921500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data    178207000                       # number of SCUpgradeReq miss cycles
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+system.l2c.SCUpgradeReq_miss_latency::total    360745500                       # number of SCUpgradeReq miss cycles
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+system.l2c.ReadExReq_miss_latency::cpu1.data  19400961500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  82517892000                       # number of ReadExReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    153728000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    149604000                       # number of ReadSharedReq miss cycles
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+system.l2c.ReadSharedReq_miss_latency::cpu0.data  15249907500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  32848298905                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    212651500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    233752000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.inst   5417778000                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data  12722216500                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  23071745004                       # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total  96202750409                       # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker    153728000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker    149604000                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  32848298905                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker    212651500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker    233752000                       # number of demand (read+write) miss cycles
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+system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  23071745004                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total    178720642409                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker    153728000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker    149604000                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::cpu0.data  78366838000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  32848298905                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker    212651500                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  23071745004                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total   178720642409                       # number of overall miss cycles
+system.l2c.WritebackDirty_accesses::writebacks      2474359                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      2474359                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data       213085                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data       184791                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total          397876                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data        48402                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data        50448                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total         98850                       # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::cpu1.data       316168                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           939824                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker         5712                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu0.inst       435799                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data       624941                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker         6938                       # number of ReadSharedReq accesses(hits+misses)
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+system.l2c.ReadSharedReq_accesses::cpu1.inst       450693                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       608524                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       434158                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      3039829                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         5712                       # number of demand (read+write) accesses
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+system.l2c.demand_accesses::cpu1.data          924692                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.l2cache.prefetcher       434158                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             3979653                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         5712                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::cpu0.l2cache.prefetcher       462262                       # number of overall (read+write) accesses
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+system.l2c.overall_accesses::total            3979653                       # number of overall (read+write) accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.293165                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.311087                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.301488                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.282716                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.255887                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.269024                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.765449                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.468669                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.665609                       # miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.189951                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.230486                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.104853                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.177700                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.438396                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.222831                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.272624                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.089203                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.151301                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.329661                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.210597                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.189951                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.230486                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.104853                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.471272                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.438396                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.222831                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.272624                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.089203                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.259814                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.329661                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.318052                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.189951                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.230486                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.104853                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.471272                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.438396                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.222831                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.272624                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.089203                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.259814                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.329661                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.318052                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14866.101586                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17834.794559                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 16288.787462                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13023.019585                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14140.405918                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 13565.430752                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 132216.111166                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130930.107708                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 131911.489797                       # average ReadExReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141684.792627                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140341.463415                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134436.349710                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137322.222923                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 162090.552888                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 137549.482536                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 138807.600950                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134760.540258                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138179.825133                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 150274.532802                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141684.792627                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140341.463415                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 134436.349710                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 133179.768502                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.data 133708.409643                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 141199.099661                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141684.792627                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 141199.099661                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        6                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs            61                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              971265                       # number of writebacks
-system.l2c.writebacks::total                   971265                       # number of writebacks
-system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           78                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data            8                       # number of ReadSharedReq MSHR hits
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-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           26                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total          224                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst             78                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data              8                       # number of demand (read+write) MSHR hits
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-system.l2c.demand_mshr_hits::cpu1.data             26                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                224                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst            78                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data             8                       # number of overall MSHR hits
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-system.l2c.overall_mshr_hits::total               224                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks        38370                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total        38370                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        67422                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        57259                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total       124681                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data        14532                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data        11014                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total        25546                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       480698                       # number of ReadExReq MSHR misses
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-system.l2c.ReadExReq_mshr_misses::total        629032                       # number of ReadExReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         1519                       # number of ReadSharedReq MSHR misses
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+system.l2c.writebacks::writebacks              969294                       # number of writebacks
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        43125                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        15619                       # number of ReadReq MSHR uncacheable
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 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst          110                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        23609                       # number of ReadReq MSHR uncacheable
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 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        43125                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        32098                       # number of overall MSHR uncacheable misses
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 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst          110                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        46229                       # number of overall MSHR uncacheable misses
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   4976293000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   4208598500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   9184891500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data   1113938500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    842688500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total   1956627000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  58746961500                       # number of ReadExReq MSHR miss cycles
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-system.l2c.ReadExReq_mshr_miss_latency::total  76673794000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    194917500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    210371000                       # number of ReadSharedReq MSHR miss cycles
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-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  17254770500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  31323421187                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    135433000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    133351000                       # number of ReadSharedReq MSHR miss cycles
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-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   9450937500                       # number of ReadSharedReq MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    194917500                       # number of demand (read+write) MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::total 167397350006                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data        42207                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total       120156                       # number of overall MSHR uncacheable misses
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   4224060500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total   8827525000                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data    988070500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total   2036710000                       # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  17919181500                       # number of ReadExReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::total 166035911409                       # number of demand (read+write) MSHR miss cycles
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   4854521000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2284412000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2461668000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     11994000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3673036000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  10823963000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2391400000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3605950000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   5997350000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3463851500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  10792034500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2661815500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3296062500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   5957878000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   4854521000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4675812000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5123483500                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     11994000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   7278986000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  16821313000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6759914000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  16749912500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.287738                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.334420                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.307447                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.272099                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.243344                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.258909                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.752238                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.471578                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.659659                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.226379                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.290944                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.097312                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.194882                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.169378                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.190899                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.091660                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.132539                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.209612                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.226379                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.290944                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.097312                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.461158                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.169378                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.190899                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.091660                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.255392                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.315848                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.226379                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.290944                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.097312                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.461158                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.411185                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.169378                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.190899                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.091660                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.255392                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.346556                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.315848                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73808.148676                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73501.082799                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73667.130517                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76654.176989                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76510.668240                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76592.304079                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122211.786818                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120854.507395                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 121891.722520                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124431.598901                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126748.428019                       # average ReadSharedReq mshr miss latency
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-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124741.078591                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128826.061176                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140249.842714                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124431.598901                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123213.017483                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124741.078591                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123492.394991                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 131199.119373                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124431.598901                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123213.017483                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124741.078591                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123492.394991                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 131199.119373                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.293165                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.311087                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.301488                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.282716                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.255887                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.269024                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.765449                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.468669                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.665609                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.189951                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.230486                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.104583                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.177657                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.438396                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.222831                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.272624                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.089001                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.151263                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.329661                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.210512                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.189951                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.230486                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.104583                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.471251                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.438396                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.222831                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.272624                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.089001                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.259789                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.329661                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.317987                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.189951                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.230486                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.104583                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.471251                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.438396                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.222831                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.272624                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.089001                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.259789                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.329661                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.317987                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73691.983224                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73479.812476                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73590.304698                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76632.527039                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76541.211558                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76588.199902                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122216.111166                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120930.107708                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 121911.489797                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124474.954473                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127327.340689                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124826.785002                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128180.440427                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140288.519066                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124474.954473                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123180.544084                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124826.785002                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123708.217296                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 131204.314747                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124474.954473                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123180.544084                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124826.785002                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123708.217296                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 131204.314747                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146258.531276                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 147000.358295                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155577.788132                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131258.418927                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145118.029007                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 159414.235190                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153388.833474                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158957.895461                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131977.137651                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148142.002449                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161445.067594                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155217.746978                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145673.001433                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147591.274414                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157454.974150                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 138376.408746                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160160.968560                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 139401.382370                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               82463                       # Transaction distribution
-system.membus.trans_dist::ReadResp             738269                       # Transaction distribution
-system.membus.trans_dist::WriteReq              39099                       # Transaction distribution
-system.membus.trans_dist::WriteResp             39099                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1078222                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           196131                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           410883                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq         321341                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          158448                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            644070                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           620815                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        655806                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        106983                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       106983                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123128                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq               81772                       # Transaction distribution
+system.membus.trans_dist::ReadResp             730632                       # Transaction distribution
+system.membus.trans_dist::WriteReq              38384                       # Transaction distribution
+system.membus.trans_dist::WriteResp             38384                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1075989                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           189758                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           405662                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq         313696                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          154281                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            640388                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           617827                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        648860                       # Transaction distribution
+system.membus.trans_dist::InvalidateReq        106721                       # Transaction distribution
+system.membus.trans_dist::InvalidateResp       106721                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122768                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        28306                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4701222                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4852748                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342712                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342712                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5195460                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156143                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25854                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4655021                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4803735                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342369                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342369                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5146104                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155875                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        56612                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    143440556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    143653515                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7262336                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7262336                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               150915851                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           600183                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3537604                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        51708                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    142678316                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    142886103                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7257472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7257472                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               150143575                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           590609                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3503595                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3537604    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3503595    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3537604                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           101645000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3503595                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           101306500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               54500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            23516499                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            21492499                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          7437675124                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          7402591959                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         7217345032                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7154332547                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          228825593                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          228436684                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3230,52 +3213,52 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     10517449                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      5725465                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests      1766756                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops         114752                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops       104186                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops        10566                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              82465                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           3940978                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             39099                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            39099                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      3582727                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         1240251                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          683521                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq        394463                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp        1077983                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq          128                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp          128                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1083401                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1083400                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      3865739                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq       106983                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      8168699                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6135080                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              14303779                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    247232417                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    172105066                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              419337483                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2918298                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          7581961                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.362851                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.483712                       # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests     10356989                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      5641244                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests      1705825                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops         115755                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops       104698                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops        11057                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              81774                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           3879147                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             38384                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            38384                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      3550378                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         1245199                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          675855                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq        385953                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp        1061806                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq          138                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp          138                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1071844                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1071844                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      3804622                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq       106721                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      7596632                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      6529428                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              14126060                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    228502049                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    185064310                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              413566359                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2887820                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          7482662                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.359179                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.482830                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4841404     63.85%     63.85% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                2729991     36.01%     99.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                  10566      0.14%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                4806103     64.23%     64.23% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                2665502     35.62%     99.85% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                  11057      0.15%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            7581961                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         8230397518                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            7482662                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         8118734038                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          2646637                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          2606433                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4512530115                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4223747952                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        3554923231                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        3725557524                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
index 8ffe023cb..247552639 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
@@ -104,10 +104,10 @@
 [    2.139655] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]

 [    2.139667] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]

 [    2.139709] pci_bus 0000:00: fixups for bus

-[    2.139718] pci_bus 0000:00: bus scan returning with max=00

+[    2.139717] pci_bus 0000:00: bus scan returning with max=00

 [    2.139730] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc

-[    2.139753] pci 0000:00:00.0: fixup irq: got 33

-[    2.139762] pci 0000:00:00.0: assigning IRQ 33

+[    2.139752] pci 0000:00:00.0: fixup irq: got 33

+[    2.139761] pci 0000:00:00.0: assigning IRQ 33

 [    2.139773] pci 0000:00:01.0: fixup irq: got 34

 [    2.139782] pci 0000:00:01.0: assigning IRQ 34

 [    2.139794] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

@@ -116,51 +116,51 @@
 [    2.139835] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

 [    2.139847] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]

 [    2.139859] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]

-[    2.139871] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

-[    2.139883] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

+[    2.139870] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

+[    2.139882] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

 [    2.140477] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

-[    2.140811] ata_piix 0000:00:01.0: version 2.13

-[    2.140822] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

-[    2.140865] ata_piix 0000:00:01.0: enabling bus mastering

-[    2.141220] scsi0 : ata_piix

-[    2.141324] scsi1 : ata_piix

-[    2.141362] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

-[    2.141375] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

-[    2.141526] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

-[    2.141538] e1000: Copyright (c) 1999-2006 Intel Corporation.

-[    2.141554] e1000 0000:00:00.0: enabling device (0000 -> 0002)

-[    2.141566] e1000 0000:00:00.0: enabling bus mastering

+[    2.140812] ata_piix 0000:00:01.0: version 2.13

+[    2.140823] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

+[    2.140866] ata_piix 0000:00:01.0: enabling bus mastering

+[    2.141222] scsi0 : ata_piix

+[    2.141325] scsi1 : ata_piix

+[    2.141364] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

+[    2.141376] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

+[    2.141528] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

+[    2.141540] e1000: Copyright (c) 1999-2006 Intel Corporation.

+[    2.141556] e1000 0000:00:00.0: enabling device (0000 -> 0002)

+[    2.141568] e1000 0000:00:00.0: enabling bus mastering

 [    2.301209] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66

-[    2.301219] ata1.00: 2096640 sectors, multi 0: LBA 

+[    2.301220] ata1.00: 2096640 sectors, multi 0: LBA 

 [    2.301250] ata1.00: configured for UDMA/33

 [    2.301329] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5

 [    2.301473] sd 0:0:0:0: Attached scsi generic sg0 type 0

-[    2.301485] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)

-[    2.301561] sd 0:0:0:0: [sda] Write Protect is off

-[    2.301570] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00

-[    2.301591] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA

-[    2.301765]  sda: sda1

-[    2.301899] sd 0:0:0:0: [sda] Attached SCSI disk

+[    2.301486] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)

+[    2.301562] sd 0:0:0:0: [sda] Write Protect is off

+[    2.301571] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00

+[    2.301592] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA

+[    2.301766]  sda: sda1

+[    2.301900] sd 0:0:0:0: [sda] Attached SCSI disk

 [    2.421494] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01

 [    2.421508] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection

-[    2.421532] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k

+[    2.421533] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k

 [    2.421543] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.

-[    2.421566] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k

-[    2.421578] igb: Copyright (c) 2007-2014 Intel Corporation.

-[    2.421668] usbcore: registered new interface driver usb-storage

-[    2.421737] mousedev: PS/2 mouse device common for all mice

-[    2.421933] usbcore: registered new interface driver usbhid

+[    2.421567] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k

+[    2.421579] igb: Copyright (c) 2007-2014 Intel Corporation.

+[    2.421669] usbcore: registered new interface driver usb-storage

+[    2.421738] mousedev: PS/2 mouse device common for all mice

+[    2.421934] usbcore: registered new interface driver usbhid

 [    2.421944] usbhid: USB HID core driver

 [    2.421984] TCP: cubic registered

 [    2.421992] NET: Registered protocol family 17

-
-[    2.422517] devtmpfs: mounted

-[    2.422651] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)

+
+[    2.422519] devtmpfs: mounted

+[    2.422652] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)

 
 
-[    2.463113] udevd[609]: starting version 182

+[    2.463118] udevd[609]: starting version 182

 Starting Bootlog daemon: bootlogd.


-[    2.544458] random: dd urandom read with 18 bits of entropy available

+[    2.544444] random: dd urandom read with 18 bits of entropy available

 Populating dev cache


 net.ipv4.conf.default.rp_filter = 1


 net.ipv4.conf.all.rp_filter = 1


@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory


 
INIT: Entering runlevel: 5



 Configuring network interfaces... udhcpc (v1.21.1) started


-[    2.681395] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

+[    2.681396] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

 Sending discover...


 Sending discover...


 Sending discover...


@@ -181,4 +181,3 @@ rpcbind: cannot get uid of '': Success
 done.


 creating NFS state directory: done


 starting statd: done


-Starting auto-serial-console: done


diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
index ae7f271b3..27116f25e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -415,10 +415,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -445,7 +444,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -572,12 +571,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -670,16 +666,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -695,7 +690,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -858,13 +853,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -874,9 +869,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -918,7 +912,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -999,14 +993,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1023,7 +1016,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1038,7 +1031,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1161,17 +1154,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1223,7 +1218,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1238,7 +1233,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
index 481cfe065..9326fddff 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 19:39:30
-gem5 executing on e104799-lin, pid 27757
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 14:13:19
+gem5 executing on e104799-lin, pid 14780
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
 info: Using kernel entry physical address at 0x80080000
 info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 51811412441500 because m5_exit instruction encountered
+Exiting @ tick 51811415265500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
index 9c2ca116d..b27222f80 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -1,138 +1,138 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.811412                       # Number of seconds simulated
-sim_ticks                                51811412441500                       # Number of ticks simulated
-final_tick                               51811412441500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.811415                       # Number of seconds simulated
+sim_ticks                                51811415265500                       # Number of ticks simulated
+final_tick                               51811415265500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 643802                       # Simulator instruction rate (inst/s)
-host_op_rate                                   756584                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            40241687351                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 677920                       # Number of bytes of host memory used
-host_seconds                                  1287.51                       # Real time elapsed on the host
-sim_insts                                   828899207                       # Number of instructions simulated
-sim_ops                                     974107036                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 625298                       # Simulator instruction rate (inst/s)
+host_op_rate                                   734839                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            39084409400                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 677180                       # Number of bytes of host memory used
+host_seconds                                  1325.63                       # Real time elapsed on the host
+sim_insts                                   828913449                       # Number of instructions simulated
+sim_ops                                     974124045                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker       133568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker       141632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           4651380                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          65025608                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        401792                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             70353980                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      4651380                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         4651380                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     61199552                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker       133696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker       141376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           4656308                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          65123848                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        401856                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             70457084                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      4656308                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         4656308                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     61286080                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          61220132                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker         2087                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker         2213                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             113085                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1016038                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6278                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1139701                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          956243                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          61306660                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker         2089                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker         2209                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst             113162                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1017573                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6279                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1141312                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          957595                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               958816                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker           2578                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker           2734                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst                89775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1255044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7755                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1357886                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           89775                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              89775                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1181198                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               960168                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker           2580                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker           2729                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                89870                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1256940                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7756                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1359876                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           89870                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              89870                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1182868                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                 397                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1181596                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1181198                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          2578                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker          2734                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               89775                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1255441                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7755                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2539481                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1139701                       # Number of read requests accepted
-system.physmem.writeReqs                       958816                       # Number of write requests accepted
-system.physmem.readBursts                     1139701                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     958816                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 72891072                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     49792                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  61218752                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  70353980                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               61220132                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      778                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         295779                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               70381                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               75813                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               71139                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               67493                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               63564                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               70698                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               65929                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               63583                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               66194                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              109788                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              68376                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              70520                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              68080                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              71994                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              69489                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              65882                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               58404                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               62356                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60883                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               59981                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               56389                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               60703                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               57931                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               57426                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               58562                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               60878                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              59750                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              62184                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              59419                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              62742                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              60987                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              57948                       # Per bank write bursts
+system.physmem.bw_write::total                1183265                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1182868                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          2580                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker          2729                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               89870                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1257337                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7756                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2543141                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1141312                       # Number of read requests accepted
+system.physmem.writeReqs                       960168                       # Number of write requests accepted
+system.physmem.readBursts                     1141312                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     960168                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 72995200                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     48768                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  61305216                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  70457084                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               61306660                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      762                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                    2248                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         295918                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               70676                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               76921                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               71652                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               67938                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               64385                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               70205                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               66024                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               63727                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               65795                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              109889                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              68785                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              70022                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              67859                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              71968                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              68874                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              65830                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               58715                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               63168                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               61317                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               60411                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               56741                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               60657                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               57878                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               57357                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               58434                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               60882                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              59842                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              61839                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              59187                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              62791                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              60690                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              57985                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          40                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51811409612500                       # Total gap between requests
+system.physmem.numWrRetry                          35                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51811412436500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1096585                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1098196                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 956243                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1112094                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     21162                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       399                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       340                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       547                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       537                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1194                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       625                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       281                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      324                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      169                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      151                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      109                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      108                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 957595                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1113641                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     21217                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       401                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       327                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       463                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       549                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       543                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1170                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       660                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       297                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      334                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      161                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      148                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      115                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      113                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      105                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                       95                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                       91                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       71                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       51                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       69                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       50                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -159,104 +159,103 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    13699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    16507                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    54180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    55051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    57086                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    56677                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    57597                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    58012                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    59157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    58593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    58964                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    62926                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    58374                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    57067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    57736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    55832                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    55140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    54594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      869                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      656                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      609                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      521                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      503                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      325                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      322                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      231                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      290                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      331                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      295                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      174                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      155                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       450541                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      297.663263                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     171.634069                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.395643                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         180604     40.09%     40.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       109821     24.38%     64.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        39191      8.70%     73.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        22619      5.02%     78.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        15643      3.47%     81.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11800      2.62%     84.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10101      2.24%     86.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8767      1.95%     88.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        51995     11.54%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         450541                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         53849                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.149826                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      337.005181                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095          53847    100.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                    13676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    16408                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    54291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    55219                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    56988                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    56655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    57800                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    58177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    59164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    58681                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    59112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    63114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    58508                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    57267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    57924                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    55949                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    55254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    54682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      579                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      493                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      499                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      420                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      342                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      370                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      372                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      296                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      299                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                      112                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                      113                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       451440                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      297.492681                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     171.675079                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.019607                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         180783     40.05%     40.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       110069     24.38%     64.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        39371      8.72%     73.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        22726      5.03%     78.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        15993      3.54%     81.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        11772      2.61%     84.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         9986      2.21%     86.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         8783      1.95%     88.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        51957     11.51%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         451440                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         53917                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.153458                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      336.779025                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095          53915    100.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::20480-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::73728-77823            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           53849                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         53849                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.763431                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.132779                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.573717                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           51569     95.77%     95.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             271      0.50%     96.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              82      0.15%     96.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             312      0.58%     97.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              52      0.10%     97.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             350      0.65%     97.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             234      0.43%     98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              17      0.03%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              58      0.11%     98.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             145      0.27%     98.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              23      0.04%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              22      0.04%     98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             441      0.82%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              31      0.06%     99.55% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           53917                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         53917                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.766085                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.131013                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.603955                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           51657     95.81%     95.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             251      0.47%     96.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              85      0.16%     96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             305      0.57%     97.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              61      0.11%     97.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             347      0.64%     97.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             210      0.39%     98.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              16      0.03%     98.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              56      0.10%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             148      0.27%     98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              29      0.05%     98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              23      0.04%     98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             456      0.85%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              29      0.05%     99.55% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::72-75              32      0.06%     99.61% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::76-79             152      0.28%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               4      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               4      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               7      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               3      0.01%     99.91% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::88-91               2      0.00%     99.91% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::100-103             4      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             3      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             4      0.01%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::128-131            26      0.05%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
@@ -264,13 +263,13 @@ system.physmem.wrPerTurnAround::140-143             1      0.00%     99.99% # Wr
 system.physmem.wrPerTurnAround::152-155             3      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::164-167             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           53849                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    14314490470                       # Total ticks spent queuing
-system.physmem.totMemAccLat               35669296720                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5694615000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12568.44                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           53917                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    14358242809                       # Total ticks spent queuing
+system.physmem.totMemAccLat               35743555309                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5702750000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12588.88                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31318.44                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31338.88                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.41                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.18                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.36                       # Average system read bandwidth in MiByte/s
@@ -280,40 +279,40 @@ system.physmem.busUtil                           0.02                       # Da
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        27.89                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     918030                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    726894                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.61                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.99                       # Row buffer hit rate for writes
-system.physmem.avgGap                     24689535.33                       # Average gap between requests
-system.physmem.pageHitRate                      78.50                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1704243240                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  929894625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4279041000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3071993040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3384069106080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1294968358125                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29950905933000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34639928569110                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.577285                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49825452803142                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1730096680000                       # Time in different power states
+system.physmem.avgWrQLen                        25.21                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     919470                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    727533                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.62                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.95                       # Row buffer hit rate for writes
+system.physmem.avgGap                     24654725.45                       # Average gap between requests
+system.physmem.pageHitRate                      78.49                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1712392920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  934341375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4301879400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3086061120                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3384069614640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1295992039365                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29950012638750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34640108967570                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.580666                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49823953491004                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1730096940000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    255862301858                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    257364177996                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1701846720                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  928587000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4604519400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3126405600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3384069106080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1295387816850                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29950537986750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34640356268400                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.585540                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49824790858475                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1730096680000                       # Time in different power states
+system.physmem_1.actEnergy                 1700493480                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  927848625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4594371600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3121092000                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3384069614640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1294725453480                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29951123679000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34640262552825                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.583630                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49825763906946                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1730096940000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    256517624025                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    255552101804                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
@@ -367,70 +366,71 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.walks                    185269                       # Table walker walks requested
-system.cpu.dtb.walker.walksLong                185269                       # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2        12948                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3       144056                       # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore           19                       # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples       185250                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean     0.215924                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev    70.777306                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-2047       185248    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks                    185222                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                185222                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2        12899                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3       144060                       # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore           17                       # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples       185205                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean     0.215977                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev    70.785904                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-2047       185203    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total       185250                       # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples       157023                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 24782.458621                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 20866.161950                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 18013.175833                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535       155872     99.27%     99.27% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071            4      0.00%     99.27% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607          991      0.63%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143           17      0.01%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679           68      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215           22      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751           34      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287            6      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total       157023                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples   3934185148                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean     0.600903                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev     0.489713                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0      1570120704     39.91%     39.91% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::1      2364064444     60.09%    100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total   3934185148                       # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K        144057     91.75%     91.75% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M         12948      8.25%    100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total       157005                       # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       185269                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::total       185205                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples       156976                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 24757.998038                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 20851.674753                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 17681.260030                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535       155823     99.27%     99.27% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071            3      0.00%     99.27% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607         1006      0.64%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143           12      0.01%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679           72      0.05%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215           20      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751           30      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total       156976                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples   3935879148                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean     0.602257                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev     0.489432                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0      1565466704     39.77%     39.77% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::1      2370412444     60.23%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total   3935879148                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        144061     91.78%     91.78% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         12899      8.22%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       156960                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       185222                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total       185269                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       157005                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       185222                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       156960                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total       157005                       # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total       342274                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       156960                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       342182                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                    156094559                       # DTB read hits
-system.cpu.dtb.read_misses                     137688                       # DTB read misses
-system.cpu.dtb.write_hits                   141675607                       # DTB write hits
-system.cpu.dtb.write_misses                     47581                       # DTB write misses
+system.cpu.dtb.read_hits                    156096920                       # DTB read hits
+system.cpu.dtb.read_misses                     137670                       # DTB read misses
+system.cpu.dtb.write_hits                   141678029                       # DTB write hits
+system.cpu.dtb.write_misses                     47552                       # DTB write misses
 system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid               37806                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                     999                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                    70732                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                    70722                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                   6720                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                   6709                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                     18565                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                156232247                       # DTB read accesses
-system.cpu.dtb.write_accesses               141723188                       # DTB write accesses
+system.cpu.dtb.read_accesses                156234590                       # DTB read accesses
+system.cpu.dtb.write_accesses               141725581                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                         297770166                       # DTB hits
-system.cpu.dtb.misses                          185269                       # DTB misses
-system.cpu.dtb.accesses                     297955435                       # DTB accesses
+system.cpu.dtb.hits                         297774949                       # DTB hits
+system.cpu.dtb.misses                          185222                       # DTB misses
+system.cpu.dtb.accesses                     297960171                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -460,43 +460,44 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.walks                    118504                       # Table walker walks requested
-system.cpu.itb.walker.walksLong                118504                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walks                    118503                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                118503                       # Table walker walks initiated with long descriptors
 system.cpu.itb.walker.walksLongTerminationLevel::Level2         1110                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3       107076                       # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples       118504                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0          118504    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total       118504                       # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples       108186                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 28679.602721                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24825.752216                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 21031.513378                       # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535       106793     98.71%     98.71% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071            1      0.00%     98.71% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607         1215      1.12%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksLongTerminationLevel::Level3       107075                       # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples       118503                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          118503    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       118503                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples       108185                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28674.682257                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24804.583165                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 21241.542539                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535       106795     98.72%     98.72% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607         1213      1.12%     99.84% # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walkCompletionTime::196608-262143           32      0.03%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679           67      0.06%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215           29      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751           34      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total       108186                       # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679           69      0.06%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215           26      0.02%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751           33      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total       108185                       # Table walker service (enqueue to completion) latency
 system.cpu.itb.walker.walksPending::samples   1449611704                       # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::0      1449611704    100.00%    100.00% # Table walker pending requests distribution
 system.cpu.itb.walker.walksPending::total   1449611704                       # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K        107076     98.97%     98.97% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K        107075     98.97%     98.97% # Table walker page sizes translated
 system.cpu.itb.walker.walkPageSizes::2M          1110      1.03%    100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total       108186                       # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       108185                       # Table walker page sizes translated
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       118504                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total       118504                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       118503                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       118503                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       108186                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total       108186                       # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total       226690                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    829409821                       # ITB inst hits
-system.cpu.itb.inst_misses                     118504                       # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       108185                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       108185                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       226688                       # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits                    829424054                       # ITB inst hits
+system.cpu.itb.inst_misses                     118503                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -512,41 +513,41 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                829528325                       # ITB inst accesses
-system.cpu.itb.hits                         829409821                       # DTB hits
-system.cpu.itb.misses                          118504                       # DTB misses
-system.cpu.itb.accesses                     829528325                       # DTB accesses
-system.cpu.numCycles                     103622824883                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                829542557                       # ITB inst accesses
+system.cpu.itb.hits                         829424054                       # DTB hits
+system.cpu.itb.misses                          118503                       # DTB misses
+system.cpu.itb.accesses                     829542557                       # DTB accesses
+system.cpu.numCycles                     103622830531                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    15973                       # number of quiesce instructions executed
-system.cpu.committedInsts                   828899207                       # Number of instructions committed
-system.cpu.committedOps                     974107036                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             895578515                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 899571                       # Number of float alu accesses
-system.cpu.num_func_calls                    49817464                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    125652530                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    895578515                       # number of integer instructions
-system.cpu.num_fp_insts                        899571                       # number of float instructions
-system.cpu.num_int_register_reads          1295563811                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          709708276                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads              1453001                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              757712                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            214507812                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes           213899539                       # number of times the CC registers were written
-system.cpu.num_mem_refs                     297748170                       # number of memory refs
-system.cpu.num_load_insts                   156084233                       # Number of load instructions
-system.cpu.num_store_insts                  141663937                       # Number of store instructions
-system.cpu.num_idle_cycles               100539253419.334061                       # Number of idle cycles
-system.cpu.num_busy_cycles               3083571463.665941                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.029758                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.970242                       # Percentage of idle cycles
-system.cpu.Branches                         184944487                       # Number of branches fetched
+system.cpu.committedInsts                   828913449                       # Number of instructions committed
+system.cpu.committedOps                     974124045                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             895594684                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 899411                       # Number of float alu accesses
+system.cpu.num_func_calls                    49818288                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts    125653589                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    895594684                       # number of integer instructions
+system.cpu.num_fp_insts                        899411                       # number of float instructions
+system.cpu.num_int_register_reads          1295586183                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          709722189                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads              1452745                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              757584                       # number of times the floating registers were written
+system.cpu.num_cc_register_reads            214510161                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes           213901888                       # number of times the CC registers were written
+system.cpu.num_mem_refs                     297752944                       # number of memory refs
+system.cpu.num_load_insts                   156086585                       # Number of load instructions
+system.cpu.num_store_insts                  141666359                       # Number of store instructions
+system.cpu.num_idle_cycles               100538909625.142059                       # Number of idle cycles
+system.cpu.num_busy_cycles               3083920905.857941                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.029761                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.970239                       # Percentage of idle cycles
+system.cpu.Branches                         184946450                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                 674583276     69.21%     69.21% # Class of executed instruction
-system.cpu.op_class::IntMult                  2119587      0.22%     69.43% # Class of executed instruction
-system.cpu.op_class::IntDiv                     97316      0.01%     69.44% # Class of executed instruction
+system.cpu.op_class::IntAlu                 674595310     69.21%     69.21% # Class of executed instruction
+system.cpu.op_class::IntMult                  2119774      0.22%     69.43% # Class of executed instruction
+system.cpu.op_class::IntDiv                     97321      0.01%     69.44% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     69.44% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     69.44% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     69.44% # Class of executed instruction
@@ -573,120 +574,120 @@ system.cpu.op_class::SimdFloatMisc             112382      0.01%     69.45% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     69.45% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.45% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.45% # Class of executed instruction
-system.cpu.op_class::MemRead                156084233     16.01%     85.47% # Class of executed instruction
-system.cpu.op_class::MemWrite               141663937     14.53%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                156086585     16.01%     85.47% # Class of executed instruction
+system.cpu.op_class::MemWrite               141666359     14.53%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  974660774                       # Class of executed instruction
-system.cpu.dcache.tags.replacements           9257757                       # number of replacements
+system.cpu.op_class::total                  974677774                       # Class of executed instruction
+system.cpu.dcache.tags.replacements           9257096                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.942792                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           288314388                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9258269                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             31.141284                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs           288320002                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9257608                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             31.144114                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        5830299500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.942792                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999888                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999888                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          351                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          110                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          400                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1200005027                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1200005027                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146175483                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146175483                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    134535173                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      134535173                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       372977                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        372977                       # number of SoftPFReq hits
-system.cpu.dcache.WriteLineReq_hits::cpu.data       334025                       # number of WriteLineReq hits
-system.cpu.dcache.WriteLineReq_hits::total       334025                       # number of WriteLineReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      3285857                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      3285857                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      3569334                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      3569334                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     280710656                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        280710656                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    281083633                       # number of overall hits
-system.cpu.dcache.overall_hits::total       281083633                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4833353                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4833353                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1968837                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1968837                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data      1108112                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total      1108112                       # number of SoftPFReq misses
-system.cpu.dcache.WriteLineReq_misses::cpu.data      1218438                       # number of WriteLineReq misses
-system.cpu.dcache.WriteLineReq_misses::total      1218438                       # number of WriteLineReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data       285095                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total       285095                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      6802190                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        6802190                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      7910302                       # number of overall misses
-system.cpu.dcache.overall_misses::total       7910302                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  82947634000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  82947634000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  66857595000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  66857595000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  73267815000                       # number of WriteLineReq miss cycles
-system.cpu.dcache.WriteLineReq_miss_latency::total  73267815000                       # number of WriteLineReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4367237000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total   4367237000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       165500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       165500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 149805229000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 149805229000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 149805229000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 149805229000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    151008836                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    151008836                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    136504010                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    136504010                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data      1481089                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total      1481089                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses        1200023494                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1200023494                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    146178724                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146178724                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    134536913                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      134536913                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       373150                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        373150                       # number of SoftPFReq hits
+system.cpu.dcache.WriteLineReq_hits::cpu.data       333652                       # number of WriteLineReq hits
+system.cpu.dcache.WriteLineReq_hits::total       333652                       # number of WriteLineReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      3286715                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      3286715                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      3569347                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      3569347                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     280715637                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        280715637                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    281088787                       # number of overall hits
+system.cpu.dcache.overall_hits::total       281088787                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      4832437                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       4832437                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1969504                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1969504                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data      1107960                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total      1107960                       # number of SoftPFReq misses
+system.cpu.dcache.WriteLineReq_misses::cpu.data      1218811                       # number of WriteLineReq misses
+system.cpu.dcache.WriteLineReq_misses::total      1218811                       # number of WriteLineReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data       284252                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total       284252                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            3                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      6801941                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        6801941                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      7909901                       # number of overall misses
+system.cpu.dcache.overall_misses::total       7909901                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  82966383500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  82966383500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  66911897500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  66911897500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  73402202000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.WriteLineReq_miss_latency::total  73402202000                       # number of WriteLineReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4352844000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total   4352844000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       248500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       248500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 149878281000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 149878281000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 149878281000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 149878281000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    151011161                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    151011161                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    136506417                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    136506417                       # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.SoftPFReq_accesses::total      1481110                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.WriteLineReq_accesses::cpu.data      1552463                       # number of WriteLineReq accesses(hits+misses)
 system.cpu.dcache.WriteLineReq_accesses::total      1552463                       # number of WriteLineReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3570952                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      3570952                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      3569336                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      3569336                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    287512846                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    287512846                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    288993935                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    288993935                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032007                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032007                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014423                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.014423                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.748174                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.748174                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.784842                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total     0.784842                       # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.079837                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.079837                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3570967                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      3570967                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      3569350                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      3569350                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    287517578                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    287517578                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    288998688                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    288998688                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032001                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.032001                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014428                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.014428                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.748061                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.748061                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.785082                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_miss_rate::total     0.785082                       # miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.079601                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.079601                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023659                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023659                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.027372                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.027372                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17161.509619                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17161.509619                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33957.912717                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33957.912717                       # average WriteReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60132.575478                       # average WriteLineReq miss latency
-system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60132.575478                       # average WriteLineReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15318.532419                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15318.532419                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82750                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82750                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.088005                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22023.088005                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18937.991116                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18937.991116                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023657                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023657                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.027370                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.027370                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17168.642550                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17168.642550                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33973.984059                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33973.984059                       # average WriteReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60224.433485                       # average WriteLineReq miss latency
+system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60224.433485                       # average WriteLineReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15313.327611                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15313.327611                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82833.333333                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82833.333333                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22034.634085                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22034.634085                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 18948.186709                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18948.186709                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -695,154 +696,154 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      7254734                       # number of writebacks
-system.cpu.dcache.writebacks::total           7254734                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        23450                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        23450                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21299                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        21299                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        67486                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        67486                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        44749                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        44749                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        44749                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        44749                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      4809903                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      4809903                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1947538                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1947538                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1106332                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total      1106332                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1218438                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.WriteLineReq_mshr_misses::total      1218438                       # number of WriteLineReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       217609                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total       217609                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      6757441                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      6757441                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      7863773                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      7863773                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks      7253164                       # number of writebacks
+system.cpu.dcache.writebacks::total           7253164                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        23327                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        23327                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21303                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        21303                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        67434                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        67434                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        44630                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        44630                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        44630                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        44630                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      4809110                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      4809110                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1948201                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1948201                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1106180                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total      1106180                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1218811                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.WriteLineReq_mshr_misses::total      1218811                       # number of WriteLineReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       216818                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total       216818                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            3                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      6757311                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      6757311                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      7863491                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      7863491                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33702                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33702                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33708                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        33708                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67410                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        67410                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  76766734500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  76766734500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  63925265000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  63925265000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20988734000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20988734000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  72049377000                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  72049377000                       # number of WriteLineReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2989622500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2989622500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       163500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       163500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140691999500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 140691999500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161680733500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 161680733500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6200659500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6200659500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6217612000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6217612000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12418271500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12418271500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.031852                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.031852                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.746972                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.746972                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.784842                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.784842                       # mshr miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060939                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060939                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  76783212500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  76783212500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  63978351000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  63978351000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  20966645000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  20966645000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  72183391000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  72183391000                       # number of WriteLineReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2984919500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2984919500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       245500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       245500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140761563500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 140761563500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161728208500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 161728208500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6199745000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6199745000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6217608000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6217608000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12417353000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  12417353000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.031846                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.031846                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014272                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014272                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.746859                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.746859                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.785082                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.785082                       # mshr miss rate for WriteLineReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060717                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060717                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023503                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.023503                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027211                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027211                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15960.141920                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15960.141920                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32823.629115                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32823.629115                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18971.460647                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18971.460647                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59132.575478                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59132.575478                       # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13738.505760                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13738.505760                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81750                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81750                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20820.307495                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20820.307495                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20560.198457                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20560.198457                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183984.911875                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183984.911875                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.084846                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.084846                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184220.019285                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184220.019285                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023502                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.023502                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027209                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027209                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15966.200087                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15966.200087                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32839.707505                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32839.707505                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18954.098790                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18954.098790                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59224.433485                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59224.433485                       # average WriteLineReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13766.935863                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13766.935863                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81833.333333                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81833.333333                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20831.002673                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20831.002673                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20566.973180                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20566.973180                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183957.776987                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183957.776987                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.966180                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.966180                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184206.393710                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184206.393710                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements          13402148                       # number of replacements
+system.cpu.icache.tags.replacements          13398086                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.782420                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           816007156                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs          13402660                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             60.883970                       # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs           816025451                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs          13398598                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             60.903794                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       61704805500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.782420                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999575                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999575                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          198                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          255                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          185                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         842812486                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        842812486                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    816007156                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       816007156                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     816007156                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        816007156                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    816007156                       # number of overall hits
-system.cpu.icache.overall_hits::total       816007156                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst     13402665                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total      13402665                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst     13402665                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total       13402665                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst     13402665                       # number of overall misses
-system.cpu.icache.overall_misses::total      13402665                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 183016744500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 183016744500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 183016744500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 183016744500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 183016744500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 183016744500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    829409821                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    829409821                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    829409821                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    829409821                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    829409821                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    829409821                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016159                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016159                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016159                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016159                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016159                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016159                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13655.250243                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13655.250243                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13655.250243                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13655.250243                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13655.250243                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13655.250243                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         842822657                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        842822657                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    816025451                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       816025451                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     816025451                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        816025451                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    816025451                       # number of overall hits
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+system.cpu.icache.ReadReq_miss_rate::total     0.016154                       # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::total 13656.593116                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13656.593116                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13656.593116                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13656.593116                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13656.593116                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -851,230 +852,231 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks     13402148                       # number of writebacks
-system.cpu.icache.writebacks::total          13402148                       # number of writebacks
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 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 169614079500                       # number of ReadReq MSHR miss cycles
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 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   5436787000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   5436787000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   5436787000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total   5436787000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016159                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016159                       # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12655.250243                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12655.250243                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12655.250243                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12655.250243                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12655.250243                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12655.250243                       # average overall mshr miss latency
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 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1000398                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65223.179314                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           41597566                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1062477                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            39.151498                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1001888                       # number of replacements
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+system.cpu.l2cache.tags.total_refs           41566827                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1063831                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            39.072773                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      56076472500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37712.043475                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   216.479752                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   326.532168                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8422.895801                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 18545.228118                       # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024        61886                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4          193                       # Occupied blocks per task id
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 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
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-system.cpu.l2cache.UpgradeReq_accesses::total        41537                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     13402665                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total     13402665                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6133844                       # number of ReadSharedReq accesses(hits+misses)
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-system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1218438                       # number of InvalidateReq accesses(hits+misses)
-system.cpu.l2cache.InvalidateReq_accesses::total      1218438                       # number of InvalidateReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.itb.walker       244191                       # number of demand (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       311814                       # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.006693                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.009063                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.007734                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.787154                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.787154                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          410                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2436                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5535                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53334                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.002899                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.942276                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        371499011                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       371499011                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       309547                       # number of ReadReq hits
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+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.787990                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.787990                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.166390                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.166390                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005223                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005223                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.035964                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.035964                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.393538                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_miss_rate::total     0.393538                       # miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006693                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.009063                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005223                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.066884                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.027822                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.006693                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.009063                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005223                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.066884                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.027822                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137105.414471                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137321.057388                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 137216.395349                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41543.522143                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41543.522143                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        80250                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        80250                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130983.207732                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130983.207732                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132181.686358                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132181.686358                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133185.935765                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133185.935765                       # average ReadSharedReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 130266.161559                       # average InvalidateReq miss latency
-system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 130266.161559                       # average InvalidateReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137105.414471                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137321.057388                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132181.686358                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 131886.832734                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 131957.998928                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137105.414471                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137321.057388                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132181.686358                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 131886.832734                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 131957.998928                       # average overall miss latency
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+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005230                       # miss rate for ReadCleanReq accesses
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+system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.394312                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_miss_rate::total     0.394312                       # miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.006703                       # miss rate for demand accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 138343.368040                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 137189.157748                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41473.226300                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41473.226300                       # average UpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80333.333333                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80333.333333                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131018.798556                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131018.798556                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132271.570055                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132271.570055                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133142.288005                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133142.288005                       # average ReadSharedReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 130264.067026                       # average InvalidateReq miss latency
+system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 130264.067026                       # average InvalidateReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135968.645285                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 138343.368040                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132271.570055                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 131889.851499                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 131970.701984                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135968.645285                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 138343.368040                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132271.570055                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 131889.851499                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 131970.701984                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1083,33 +1085,33 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       849613                       # number of writebacks
-system.cpu.l2cache.writebacks::total           849613                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         2087                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         2213                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4300                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        32696                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total        32696                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       317140                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       317140                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        69997                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        69997                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       220595                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       220595                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       479502                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.InvalidateReq_mshr_misses::total       479502                       # number of InvalidateReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         2087                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         2213                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        69997                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       537735                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       612032                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         2087                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         2213                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        69997                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       537735                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       612032                       # number of overall MSHR misses
+system.cpu.l2cache.writebacks::writebacks       850965                       # number of writebacks
+system.cpu.l2cache.writebacks::total           850965                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         2089                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         2209                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4298                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        32700                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total        32700                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       317418                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       317418                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        70074                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        70074                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       220760                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       220760                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       480592                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.InvalidateReq_mshr_misses::total       480592                       # number of InvalidateReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         2089                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         2209                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        70074                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       538178                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       612550                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         2089                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         2209                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        70074                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       538178                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       612550                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33702                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        76827                       # number of ReadReq MSHR uncacheable
@@ -1118,160 +1120,161 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33708
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67410                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total       110535                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    265269000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    281761500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    547030500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2311098000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2311098000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       140500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       140500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  38368614500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  38368614500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   8552351500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   8552351500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  27174201500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  27174201500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  57667865000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  57667865000                       # number of InvalidateReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    265269000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    281761500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8552351500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  65542816000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  74642198000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    265269000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    281761500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8552351500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  65542816000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  74642198000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    263148500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    283510500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    546659000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2311356000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2311356000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       211000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       211000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  38413545000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  38413545000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   8568058000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   8568058000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  27184891500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  27184891500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  57797948500                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  57797948500                       # number of InvalidateReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    263148500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    283510500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8568058000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  65598436500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  74713153500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    263148500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    283510500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8568058000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  65598436500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  74713153500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5778581000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  10676305500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5829959000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5829959000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5777666500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  10675391000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5829955000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5829955000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11608540000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  16506264500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006693                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.009063                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.007734                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.787154                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.787154                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607621500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  16505346000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.006703                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.009052                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.007735                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.787990                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.787990                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.166390                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.166390                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005223                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005223                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.035964                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.035964                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.393538                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.393538                       # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006693                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.009063                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005223                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.066884                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.027822                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006693                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.009063                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005223                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.066884                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.027822                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127321.057388                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127216.395349                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70684.426230                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70684.426230                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        70250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        70250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120983.207732                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120983.207732                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122181.686358                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122181.686358                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123185.935765                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123185.935765                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120266.161559                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120266.161559                       # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127321.057388                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122181.686358                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121886.832734                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121957.998928                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127321.057388                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122181.686358                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121886.832734                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121957.998928                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.166475                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.166475                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005230                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005230                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.036001                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.036001                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.394312                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.394312                       # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.006703                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.009052                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005230                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.066947                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.027852                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.006703                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.009052                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005230                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.066947                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.027852                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128343.368040                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127189.157748                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70683.669725                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70683.669725                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70333.333333                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70333.333333                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121018.798556                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121018.798556                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122271.570055                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122271.570055                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123142.288005                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123142.288005                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120264.067026                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120264.067026                       # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128343.368040                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122271.570055                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121889.851499                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121970.701984                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128343.368040                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122271.570055                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121889.851499                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121970.701984                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171461.070560                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138965.539459                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.758514                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.758514                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171433.935671                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138953.636091                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.639848                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.639848                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172207.981012                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149330.659972                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172194.355437                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149322.350387                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     45838189                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     23177247                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1749                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2695                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2695                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     45828995                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     23172776                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1754                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2709                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2709                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq         972617                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp      20509993                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq         972528                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp      20504109                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         33708                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        33708                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      8211016                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     13400558                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      2162503                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq        41540                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp        41542                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1906001                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1906001                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq     13402665                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      6142720                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq      1325102                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp      1218438                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     40292138                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27992932                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       598317                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       853478                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          69736865                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1715578772                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    979098990                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1953528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2494512                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2699125802                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1572119                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     24940276                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.019256                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.137423                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::WritebackDirty      8210793                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     13396481                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      2163559                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq        41501                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            3                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp        41504                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1906703                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1906703                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq     13398603                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      6140983                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq      1325475                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp      1218811                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     40279937                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27990886                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       598158                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       853214                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          69722195                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1715057876                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    978932526                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1952280                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2493088                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2698435770                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1573850                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     24936909                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.019271                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.137475                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           24460029     98.07%     98.07% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             480247      1.93%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           24456353     98.07%     98.07% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             480556      1.93%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       24940276                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    43858094500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       24936909                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    43847676000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy      1606889                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy      1611389                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy   20147122500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy   20141029500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   12740327469                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   12738944468                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy     354126000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy     354123000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     541664000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     541578000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                40324                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40324                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                40323                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40323                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1281,18 +1284,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231006                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231006                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231004                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231004                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353790                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353788                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1302,24 +1303,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334456                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334456                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334448                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334448                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492376                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             42148000                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492368                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             42147000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               321500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
@@ -1332,79 +1332,73 @@ system.iobus.reqLayer16.occupancy               16500                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25746500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25743500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              169000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            38603500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            38603000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           565463411                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              122000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565448922                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147766000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147764000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115484                       # number of replacements
-system.iocache.tags.tagsinuse               10.446943                       # Cycle average of tags in use
+system.iocache.tags.replacements               115483                       # number of replacements
+system.iocache.tags.tagsinuse               10.446937                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115500                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115499                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         13183709784000                       # Cycle when the warmup percentage was hit.
 system.iocache.tags.occ_blocks::realview.ethernet     3.511467                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.935476                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.935470                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.219467                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::realview.ide     0.433467                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.652934                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039884                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039884                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039875                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039875                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8839                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8876                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8838                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8875                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8839                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8879                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8838                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8878                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8839                       # number of overall misses
-system.iocache.overall_misses::total             8879                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5070000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1627645138                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1632715138                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8838                       # number of overall misses
+system.iocache.overall_misses::total             8878                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5070500                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1645846130                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1650916630                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13865007784                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13865007784                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5421000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1627645138                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1633066138                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5421000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1627645138                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1633066138                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13863091781                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13863091781                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5421500                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1645846130                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1651267630                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5421500                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1645846130                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1651267630                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8839                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8876                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8838                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8875                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8839                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8879                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8838                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8878                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8839                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8879                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8838                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8878                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1418,55 +1412,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 184143.583890                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 183947.176431                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 186223.821000                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 186018.775211                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129987.697667                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129987.697667                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 184143.583890                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183924.556594                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 184143.583890                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183924.556594                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         33671                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129969.734690                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129969.734690                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 186223.821000                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 185995.452805                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 186223.821000                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 185995.452805                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         33963                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3496                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3509                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.631293                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.678826                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106630                       # number of writebacks
 system.iocache.writebacks::total               106630                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8839                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8876                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8838                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8875                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8839                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8879                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8838                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8878                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8839                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8879                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1185695138                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1188915138                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8838                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8878                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220500                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1203946130                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1207166630                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8531807784                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8531807784                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3421000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1185695138                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1189116138                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3421000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1185695138                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1189116138                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8529891781                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8529891781                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3421500                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1203946130                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1207367630                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3421500                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1203946130                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1207367630                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1480,73 +1474,73 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134143.583890                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 133947.176431                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136223.821000                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 136018.775211                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79987.697667                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79987.697667                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 134143.583890                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 133924.556594                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 134143.583890                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 133924.556594                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79969.734690                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79969.734690                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 136223.821000                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 135995.452805                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 136223.821000                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 135995.452805                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               76827                       # Transaction distribution
-system.membus.trans_dist::ReadResp             380595                       # Transaction distribution
+system.membus.trans_dist::ReadResp             380834                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33708                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33708                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       956243                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           155849                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            33272                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           33274                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            796069                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           796069                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        303768                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       957595                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           155985                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            33274                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           33277                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            797439                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           797439                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        304007                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6930                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3338566                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3468258                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341194                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       341194                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3809452                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3343278                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3472970                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341196                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       341196                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3814166                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13860                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    124348000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total    124517826                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7226112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7226112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               131743938                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3260                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2465217                       # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    124537568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total    124707394                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7226176                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7226176                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               131933570                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3258                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2468309                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2465217    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2468309    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2465217                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           106924000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2468309                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           106920500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5793500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5785500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          6289776705                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          6298398949                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         6042674003                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         6051404500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          227496341                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227572547                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
index 282713d4d..dd5c13da3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
@@ -110,26 +110,26 @@
 [    3.145140] pci 0000:00:00.0: assigning IRQ 33

 [    3.145154] pci 0000:00:01.0: fixup irq: got 34

 [    3.145164] pci 0000:00:01.0: assigning IRQ 34

-[    3.145179] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

-[    3.145194] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]

+[    3.145178] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

+[    3.145193] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]

 [    3.145208] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

-[    3.145223] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

+[    3.145222] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

 [    3.145236] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]

 [    3.145249] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]

-[    3.145263] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

+[    3.145262] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

 [    3.145276] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

 [    3.146194] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

-[    3.146723] ata_piix 0000:00:01.0: version 2.13

+[    3.146724] ata_piix 0000:00:01.0: version 2.13

 [    3.146736] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

 [    3.146781] ata_piix 0000:00:01.0: enabling bus mastering

-[    3.147382] scsi0 : ata_piix

-[    3.147567] scsi1 : ata_piix

-[    3.147621] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

-[    3.147634] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

-[    3.147838] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

-[    3.147851] e1000: Copyright (c) 1999-2006 Intel Corporation.

-[    3.147874] e1000 0000:00:00.0: enabling device (0000 -> 0002)

-[    3.147887] e1000 0000:00:00.0: enabling bus mastering

+[    3.147384] scsi0 : ata_piix

+[    3.147568] scsi1 : ata_piix

+[    3.147622] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

+[    3.147635] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

+[    3.147840] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

+[    3.147853] e1000: Copyright (c) 1999-2006 Intel Corporation.

+[    3.147876] e1000 0000:00:00.0: enabling device (0000 -> 0002)

+[    3.147889] e1000 0000:00:00.0: enabling bus mastering

 [    3.301640] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66

 [    3.301651] ata1.00: 2096640 sectors, multi 0: LBA 

 [    3.301686] ata1.00: configured for UDMA/33

@@ -160,7 +160,7 @@
 
 [    3.470418] udevd[607]: starting version 182

 Starting Bootlog daemon: bootlogd.


-[    3.586550] random: dd urandom read with 21 bits of entropy available

+[    3.586551] random: dd urandom read with 21 bits of entropy available

 Populating dev cache


 net.ipv4.conf.default.rp_filter = 1


 net.ipv4.conf.all.rp_filter = 1


@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory


 
INIT: Entering runlevel: 5



 Configuring network interfaces... udhcpc (v1.21.1) started


-[    3.791839] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

+[    3.791840] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

 Sending discover...


 Sending discover...


 Sending discover...


diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
index bd04e69be..43d12537e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -511,10 +511,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -541,7 +540,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -641,12 +640,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -739,16 +735,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -764,7 +759,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -927,13 +922,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -943,9 +938,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -987,7 +981,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1068,14 +1062,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1092,7 +1085,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1107,7 +1100,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1230,17 +1223,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1292,7 +1287,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1307,7 +1302,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
index 703a7cc19..9f2f9de0b 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 20:01:11
-gem5 executing on e104799-lin, pid 27942
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 12:10:26
+gem5 executing on e104799-lin, pid 2423
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
index 665041840..c8bf2f829 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.111153                       # Nu
 sim_ticks                                51111152682000                       # Number of ticks simulated
 final_tick                               51111152682000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 987530                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1160510                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            51264798094                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 676380                       # Number of bytes of host memory used
-host_seconds                                   997.00                       # Real time elapsed on the host
+host_inst_rate                                 965225                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1134298                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            50106889543                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 675900                       # Number of bytes of host memory used
+host_seconds                                  1020.04                       # Real time elapsed on the host
 sim_insts                                   984570519                       # Number of instructions simulated
 sim_ops                                    1157031967                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -682,6 +682,7 @@ system.iobus.trans_dist::WriteReq              136515                       # Tr
 system.iobus.trans_dist::WriteResp             136515                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47598                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -691,10 +692,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122480                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230962                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total       230962                       # Packet count per connected master and slave (bytes)
@@ -703,6 +701,7 @@ system.iobus.pkt_count_system.realview.ethernet.dma::total           80
 system.iobus.pkt_count::total                  353522                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47618                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -712,10 +711,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155610                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334280                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      7334280                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
index 267ce426c..be51ba10d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -1612,10 +1612,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -1642,7 +1641,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1806,12 +1805,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -1904,16 +1900,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1929,7 +1924,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -2092,13 +2087,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -2108,9 +2103,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -2152,7 +2146,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -2233,14 +2227,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -2257,7 +2250,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -2272,7 +2265,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -2395,17 +2388,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -2457,7 +2452,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -2472,7 +2467,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
index fa0b6dca7..14afb57bc 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
@@ -48,19 +48,17 @@ warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
 WARNING: Bank is already active!
 Command: 0, Timestamp: 11264, Bank: 3
 WARNING: Bank is already active!
-Command: 0, Timestamp: 9230, Bank: 3
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 8878, Bank: 3
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 12188, Bank: 4
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -107,6 +105,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -137,8 +139,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -155,6 +163,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -163,22 +175,22 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10181, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10357, Bank: 0
+Command: 0, Timestamp: 6453, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8188, Bank: 4
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9018, Bank: 6
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -186,29 +198,17 @@ warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 9265, Bank: 2
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 11838, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10817, Bank: 1
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -218,15 +218,15 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9882, Bank: 6
+Command: 0, Timestamp: 6477, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -235,10 +235,16 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 12028, Bank: 7
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -257,6 +263,12 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -279,6 +291,16 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6774, Bank: 7
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10642, Bank: 6
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -288,19 +310,27 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6857, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10777, Bank: 3
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 9126, Bank: 4
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6534, Bank: 3
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -309,6 +339,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11016, Bank: 1
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -321,10 +357,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6653, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10981, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -339,8 +373,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -351,6 +383,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -367,54 +401,36 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6585, Bank: 3
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11489, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11979, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10843, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -423,8 +439,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -435,16 +449,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8812, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -459,8 +471,8 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 6
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -489,22 +501,20 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10981, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -541,6 +551,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -563,16 +575,12 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9067, Bank: 2
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -585,12 +593,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -609,10 +611,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -621,14 +619,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10900, Bank: 5
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -645,22 +639,20 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10772, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6635, Bank: 4
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -673,8 +665,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -687,18 +677,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10047, Bank: 2
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -711,8 +705,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -727,22 +723,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6754, Bank: 5
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -779,6 +767,20 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7197, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8763, Bank: 2
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8788, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10548, Bank: 1
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -809,16 +811,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -831,10 +827,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -843,6 +835,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -855,10 +849,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -887,14 +889,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -911,18 +921,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -941,28 +943,36 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7475, Bank: 3
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9111, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -971,10 +981,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -993,12 +999,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1015,12 +1015,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1041,6 +1039,22 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7611, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 6
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1049,8 +1063,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -1067,8 +1079,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7929, Bank: 3
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1079,6 +1089,9 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1086,15 +1099,20 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9985, Bank: 2
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8266, Bank: 1
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1111,10 +1129,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1123,10 +1137,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1145,18 +1159,24 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1171,14 +1191,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7131, Bank: 5
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6480, Bank: 7
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -1209,18 +1225,14 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11574, Bank: 5
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1231,8 +1243,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1253,20 +1263,10 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10090, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1287,10 +1287,6 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -1311,14 +1307,12 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6452, Bank: 1
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout
index a3a2a6967..aea4301d6 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 20:04:32
-gem5 executing on e104799-lin, pid 27965
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 13:54:27
+gem5 executing on e104799-lin, pid 12846
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
index 3e2accf44..13ac1b801 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
@@ -1,193 +1,193 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.278388                       # Number of seconds simulated
-sim_ticks                                51278388278000                       # Number of ticks simulated
-final_tick                               51278388278000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.318151                       # Number of seconds simulated
+sim_ticks                                51318151431000                       # Number of ticks simulated
+final_tick                               51318151431000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 269488                       # Simulator instruction rate (inst/s)
-host_op_rate                                   316679                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            16295713635                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 687640                       # Number of bytes of host memory used
-host_seconds                                  3146.74                       # Real time elapsed on the host
-sim_insts                                   848009832                       # Number of instructions simulated
-sim_ops                                     996505618                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 262276                       # Simulator instruction rate (inst/s)
+host_op_rate                                   308198                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15864240835                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 687920                       # Number of bytes of host memory used
+host_seconds                                  3234.83                       # Real time elapsed on the host
+sim_insts                                   848418690                       # Number of instructions simulated
+sim_ops                                     996969189                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker        80512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        85376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2480372                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         43948744                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        23424                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        20864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           458368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5839488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker        24512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker        21952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst          1437632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          8179392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker        64832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.itb.walker        58944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst          1702784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data         14408960                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        423680                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             79259836                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2480372                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       458368                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst      1437632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst      1702784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6079156                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     67469760                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        76672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        79744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2462068                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         43565640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        25536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        20992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           433216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          6171840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker        28864                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker        29440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst          1450304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          8009024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker        65344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.itb.walker        58432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst          1793920                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data         14730432                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        421568                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             79423036                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2462068                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       433216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst      1450304                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst      1793920                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         6139508                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     67636992                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          67490340                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1258                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1334                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             79163                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            686712                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          366                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          326                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              7162                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             91242                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker          383                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker          343                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst             22463                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data            127803                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker         1013                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.itb.walker          921                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst             26606                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data            225140                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6620                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1278855                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1054215                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          67657572                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1198                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1246                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             78877                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            680726                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          399                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker          328                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              6769                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             96435                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker          451                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker          460                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst             22661                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data            125141                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker         1021                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.itb.walker          913                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst             28030                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data            230163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6587                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1281405                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1056828                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1056788                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1570                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1665                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               48371                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              857062                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           457                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker           407                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst                8939                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              113878                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           478                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker           428                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               28036                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              159510                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker          1264                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.itb.walker          1149                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst               33207                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data              280995                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8262                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1545677                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          48371                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst           8939                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          28036                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst          33207                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             118552                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1315754                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1059401                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1494                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1554                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               47977                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              848932                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           498                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker           409                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst                8442                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              120266                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           562                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker           574                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               28261                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              156066                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker          1273                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.itb.walker          1139                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst               34957                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data              287041                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8215                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1547660                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          47977                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst           8442                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          28261                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst          34957                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             119636                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1317994                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1316156                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1315754                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1570                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1665                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              48371                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             857463                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          457                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker          407                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst               8939                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             113878                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          478                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker          428                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              28036                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             159510                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker         1264                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.itb.walker         1149                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst              33207                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data             280995                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8262                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2861833                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        508133                       # Number of read requests accepted
-system.physmem.writeReqs                       442708                       # Number of write requests accepted
-system.physmem.readBursts                      508133                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     442708                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 32496192                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     24320                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  28331264                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  32520512                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               28333312                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      380                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      16                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         172464                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28425                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               32222                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               31678                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               29785                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               32093                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               37258                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               31249                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               31793                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               30380                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               34315                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              33552                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              33985                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              32112                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              32580                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28200                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28126                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               25043                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               27380                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               27369                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               27020                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               28395                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               31777                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               27205                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               28447                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               27006                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               30006                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              27888                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              28964                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              27392                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              28158                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              25051                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              25575                       # Per bank write bursts
+system.physmem.bw_write::total                1318395                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1317994                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1494                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1554                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              47977                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             849333                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          498                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker          409                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst               8442                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             120266                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          562                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker          574                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              28261                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             156066                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker         1273                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.itb.walker         1139                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst              34957                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data             287041                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8215                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2866054                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        517103                       # Number of read requests accepted
+system.physmem.writeReqs                       450227                       # Number of write requests accepted
+system.physmem.readBursts                      517103                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     450227                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 33073280                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21312                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  28812544                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  33094592                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               28814528                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      333                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs         174284                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               32820                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               35061                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               31334                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               30738                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               32772                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               36727                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               31736                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               32381                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               29681                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               35684                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              31546                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              32698                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              33025                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              31465                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              29673                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              29429                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               27864                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               28674                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               26960                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               27504                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               29012                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               31175                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               28381                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               29346                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               26700                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               31017                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              26800                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              28289                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              28254                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              27295                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              26424                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              26501                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51277388057000                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51317151101500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  508133                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  517103                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 442708                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    359636                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     94580                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     31194                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     18770                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       422                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       374                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 450227                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    365842                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     95262                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     32310                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     19750                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       435                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       384                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                       374                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       769                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       482                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      260                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       98                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       83                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       77                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       75                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       68                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       60                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       48                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       741                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       491                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       222                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      244                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      108                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       92                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                       83                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                       80                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       73                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       66                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       51                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -198,193 +198,187 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       597                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       588                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       576                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       570                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       566                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      550                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      552                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       600                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       586                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       582                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       578                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       569                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      565                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      560                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      556                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                      551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     7362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     8022                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    18082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    21480                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    24501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    25734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    26594                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    26643                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    27137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    27291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    27367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    29561                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    27445                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    27298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    29173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    25766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    25736                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    24591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      514                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      260                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      149                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       46                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       256507                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      237.135361                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     143.751053                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     277.773032                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         118370     46.15%     46.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        63779     24.86%     71.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        23560      9.18%     80.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        11879      4.63%     84.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         8772      3.42%     88.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         5502      2.14%     90.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4497      1.75%     92.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3462      1.35%     93.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16686      6.51%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         256507                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         24650                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.597972                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       13.431676                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-31            22290     90.43%     90.43% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32-63            2167      8.79%     99.22% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-95             156      0.63%     99.85% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::14                      550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     7435                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     8261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    18409                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    21789                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    24777                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    26143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    27073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    27056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    27725                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    27794                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    27996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    30008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    27705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    27676                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    29590                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    26243                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    26383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    25171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      575                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      250                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      253                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      241                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       260816                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      237.276486                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     143.923814                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     277.776542                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         119999     46.01%     46.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        65306     25.04%     71.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        23923      9.17%     80.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        11962      4.59%     84.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         8906      3.41%     88.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         5685      2.18%     90.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4538      1.74%     92.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3514      1.35%     93.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16983      6.51%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         260816                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         25134                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        20.558447                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev       13.007693                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-31            22781     90.64%     90.64% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32-63            2174      8.65%     99.29% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::64-95             141      0.56%     99.85% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::96-127             17      0.07%     99.92% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::128-159             6      0.02%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::160-191             3      0.01%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::192-223             1      0.00%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::224-255             2      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-287             2      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::320-351             1      0.00%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::416-447             1      0.00%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::448-479             1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::544-575             1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::640-671             1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::192-223             6      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::224-255             3      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-287             1      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::320-351             2      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::576-607             1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::608-639             1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::672-703             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           24650                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         24650                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.958458                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.276383                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.669540                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                25      0.10%      0.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                12      0.05%      0.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11               19      0.08%      0.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              47      0.19%      0.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           22852     92.71%     93.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             503      2.04%     95.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             178      0.72%     95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             262      1.06%     96.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              56      0.23%     97.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             180      0.73%     97.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              74      0.30%     98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              10      0.04%     98.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              29      0.12%     98.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              72      0.29%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              15      0.06%     98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              17      0.07%     98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             194      0.79%     99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.02%     99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              14      0.06%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              52      0.21%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               7      0.03%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           25134                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         25134                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.911833                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.251303                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.505158                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                24      0.10%      0.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                17      0.07%      0.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               14      0.06%      0.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              60      0.24%      0.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           23322     92.79%     93.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             527      2.10%     95.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             146      0.58%     95.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             283      1.13%     97.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              54      0.21%     97.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             168      0.67%     97.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              80      0.32%     98.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              22      0.09%     98.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              25      0.10%     98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              58      0.23%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              20      0.08%     98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               9      0.04%     98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             213      0.85%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71              11      0.04%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               9      0.04%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              35      0.14%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               2      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.01%     99.90% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::104-107             1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.00%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            10      0.04%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           24650                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    10544434255                       # Total ticks spent queuing
-system.physmem.totMemAccLat               20064803005                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2538765000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20766.86                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::108-111             1      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            14      0.06%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           25134                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    10819472737                       # Total ticks spent queuing
+system.physmem.totMemAccLat               20508910237                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2583850000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20936.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39516.86                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.63                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.55                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.63                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.55                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39686.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           0.64                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.56                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        0.64                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.56                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        12.69                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     386701                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    307219                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.16                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  69.40                       # Row buffer hit rate for writes
-system.physmem.avgGap                     53928457.08                       # Average gap between requests
-system.physmem.pageHitRate                      73.01                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  977757480                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  531832125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1985068800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               1442681280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3310425549600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1177046851320                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           30704731659000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             35197141399605                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              665.410484                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   48872276305390                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1692446600000                       # Time in different power states
+system.physmem.avgWrQLen                        13.27                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     394016                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    312132                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   76.25                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  69.33                       # Row buffer hit rate for writes
+system.physmem.avgGap                     53050304.55                       # Average gap between requests
+system.physmem.pageHitRate                      73.02                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1012329360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  550658625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                2055807000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               1483375680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3312957669840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1179842633775                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29693796398250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34191698872530                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.616546                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   48906772559460                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1693741140000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    119675759110                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    122637370540                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  961435440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  522856125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1975334400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               1425859200                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3310425549600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1177208679735                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29690763244500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34183282959000                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.568308                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   48872046794911                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1692446600000                       # Time in different power states
+system.physmem_1.actEnergy                  959439600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  521932125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1974960000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               1433894400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3312957669840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1178190529245                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           30742990092750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             35239028517960                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              665.379239                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   48909312036157                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1693741140000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    119910447839                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    120107401343                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -444,47 +438,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                    90321                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong                90321                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples        90321                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          90321    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        90321                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 389002628992                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.524259                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -203938078758    -52.43%    -52.43% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1   592940707750    152.43%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 389002628992                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        65935     84.97%     84.97% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        11661     15.03%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        77596                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90321                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                    90147                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong                90147                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples        90147                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0          90147    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total        90147                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 390083894328                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.522589                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0   -203853691422    -52.26%    -52.26% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1   593937585750    152.26%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 390083894328                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        65853     84.82%     84.82% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        11789     15.18%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total        77642                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90147                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90321                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        77596                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90147                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        77642                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        77596                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       167917                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        77642                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       167789                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    64849168                       # DTB read hits
-system.cpu0.dtb.read_misses                     68465                       # DTB read misses
-system.cpu0.dtb.write_hits                   59113138                       # DTB write hits
-system.cpu0.dtb.write_misses                    21856                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1195                       # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits                    64842340                       # DTB read hits
+system.cpu0.dtb.read_misses                     68503                       # DTB read misses
+system.cpu0.dtb.write_hits                   59153195                       # DTB write hits
+system.cpu0.dtb.write_misses                    21644                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        1197                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              16233                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    380                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   40748                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              16138                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    390                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   41112                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2820                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  2836                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     7506                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                64917633                       # DTB read accesses
-system.cpu0.dtb.write_accesses               59134994                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     7541                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                64910843                       # DTB read accesses
+system.cpu0.dtb.write_accesses               59174839                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        123962306                       # DTB hits
-system.cpu0.dtb.misses                          90321                       # DTB misses
-system.cpu0.dtb.accesses                    124052627                       # DTB accesses
+system.cpu0.dtb.hits                        123995535                       # DTB hits
+system.cpu0.dtb.misses                          90147                       # DTB misses
+system.cpu0.dtb.accesses                    124085682                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -514,699 +508,699 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    53302                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                53302                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples        53302                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          53302    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        53302                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 389002628992                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.524352                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -203974223258    -52.44%    -52.44% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   592976852250    152.44%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 389002628992                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        46280     94.90%     94.90% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2485      5.10%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        48765                       # Table walker page sizes translated
+system.cpu0.itb.walker.walks                    53264                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                53264                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples        53264                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          53264    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        53264                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 390083894328                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.522690                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -203892956422    -52.27%    -52.27% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   593976850750    152.27%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 390083894328                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        46252     94.85%     94.85% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2512      5.15%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        48764                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53302                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53302                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53264                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53264                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        48765                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        48765                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       102067                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   346354960                       # ITB inst hits
-system.cpu0.itb.inst_misses                     53302                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        48764                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        48764                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       102028                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   346149733                       # ITB inst hits
+system.cpu0.itb.inst_misses                     53264                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1195                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb                        1197                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              16233                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    380                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   28697                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              16138                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    390                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   28909                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               346408262                       # ITB inst accesses
-system.cpu0.itb.hits                        346354960                       # DTB hits
-system.cpu0.itb.misses                          53302                       # DTB misses
-system.cpu0.itb.accesses                    346408262                       # DTB accesses
-system.cpu0.numCycles                       417857825                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               346202997                       # ITB inst accesses
+system.cpu0.itb.hits                        346149733                       # DTB hits
+system.cpu0.itb.misses                          53264                       # DTB misses
+system.cpu0.itb.accesses                    346202997                       # DTB accesses
+system.cpu0.numCycles                       417561800                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16514                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  346212347                       # Number of instructions committed
-system.cpu0.committedOps                    407289562                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            374196807                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                371114                       # Number of float alu accesses
-system.cpu0.num_func_calls                   20959157                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     52529410                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   374196807                       # number of integer instructions
-system.cpu0.num_fp_insts                       371114                       # number of float instructions
-system.cpu0.num_int_register_reads          546236459                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         297045333                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              596552                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             319604                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            90150585                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           89913729                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    124035099                       # number of memory refs
-system.cpu0.num_load_insts                   64906131                       # Number of load instructions
-system.cpu0.num_store_insts                  59128968                       # Number of store instructions
-system.cpu0.num_idle_cycles              408498118.041102                       # Number of idle cycles
-system.cpu0.num_busy_cycles              9359706.958898                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.022399                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.977601                       # Percentage of idle cycles
-system.cpu0.Branches                         77291806                       # Number of branches fetched
+system.cpu0.kern.inst.quiesce                   16515                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  346008550                       # Number of instructions committed
+system.cpu0.committedOps                    406987651                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            373920117                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                356678                       # Number of float alu accesses
+system.cpu0.num_func_calls                   20899397                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     52499689                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   373920117                       # number of integer instructions
+system.cpu0.num_fp_insts                       356678                       # number of float instructions
+system.cpu0.num_int_register_reads          546105589                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         296761298                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              572858                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             307664                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads            90112158                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           89900490                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    124068171                       # number of memory refs
+system.cpu0.num_load_insts                   64899300                       # Number of load instructions
+system.cpu0.num_store_insts                  59168871                       # Number of store instructions
+system.cpu0.num_idle_cycles              407652478.881758                       # Number of idle cycles
+system.cpu0.num_busy_cycles              9909321.118242                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.023731                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.976269                       # Percentage of idle cycles
+system.cpu0.Branches                         77190718                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                282487625     69.32%     69.32% # Class of executed instruction
-system.cpu0.op_class::IntMult                  909497      0.22%     69.54% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    41524      0.01%     69.55% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             50320      0.01%     69.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.56% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.56% # Class of executed instruction
-system.cpu0.op_class::MemRead                64906131     15.93%     85.49% # Class of executed instruction
-system.cpu0.op_class::MemWrite               59128968     14.51%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                282157616     69.29%     69.29% # Class of executed instruction
+system.cpu0.op_class::IntMult                  905041      0.22%     69.51% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    41769      0.01%     69.52% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.52% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             48126      0.01%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.53% # Class of executed instruction
+system.cpu0.op_class::MemRead                64899300     15.94%     85.47% # Class of executed instruction
+system.cpu0.op_class::MemWrite               59168871     14.53%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 407524065                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          9647883                       # number of replacements
+system.cpu0.op_class::total                 407220723                       # Class of executed instruction
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 system.cpu0.dcache.tags.tagsinuse          511.999717                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          292725890                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          9648395                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            30.339335                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs          292908190                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          9652852                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            30.344212                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.728369                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     5.127427                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     4.702216                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data     4.441704                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.972126                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.010015                       # Average percentage of cache occupancy
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 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
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 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1240366941                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1240366941                       # Number of data accesses
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-system.cpu0.dcache.WriteReq_hits::cpu0.data     55903260                       # number of WriteReq hits
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-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       159106                       # number of SoftPFReq hits
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-system.cpu0.dcache.SoftPFReq_hits::total       395957                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       126545                       # number of WriteLineReq hits
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-system.cpu0.dcache.LoadLockedReq_misses::total       356263                       # number of LoadLockedReq misses
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 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
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-system.cpu0.dcache.overall_misses::total     13415404                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  10730358500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  16517281500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  60662755500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  87910395500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9179104000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22761343000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 115052000035                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 146992447035                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   3717932000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   5375214500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data  11073619157                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  20166765657                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    535758000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    751006000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2342018000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3628782000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data        84500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total        84500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  19909462500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  39278624500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data 175714755535                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 234902842535                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  19909462500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  39278624500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data 175714755535                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 234902842535                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     62723063                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     19575168                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_accesses::cpu0.data     56748882                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     17612743                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data     23791257                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu3.data     41323259                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    139476141                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       622568                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       192054                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       286887                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       464260                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1565769                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       814123                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       157067                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       209808                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       374141                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1555139                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1550233                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       467855                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       622012                       # number of LoadLockedReq accesses(hits+misses)
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-system.cpu0.dcache.LoadLockedReq_accesses::total      3745975                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1549496                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       467643                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       621749                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1067527                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3706415                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    119471945                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     37187911                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data     50741020                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data     89705457                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    297106333                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    120094513                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     37379965                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data     51027907                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data     90169717                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    298672102                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032602                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033445                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.035752                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.071077                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.045055                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014901                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014262                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.025407                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.083303                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.036878                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.744436                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.755449                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.731734                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.756770                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747117                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.844563                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.704298                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.715335                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.741215                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788098                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059326                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.080760                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.080900                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.159321                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.095106                       # miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.761235                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.724494                       # miss rate for SoftPFReq accesses
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+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.077706                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.158370                       # miss rate for LoadLockedReq accesses
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 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000001                       # miss rate for StoreCondReq accesses
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 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024194                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024360                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.030901                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data     0.076709                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.041216                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027928                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028116                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.034842                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data     0.080210                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.044917                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16389.983809                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17142.751948                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17640.362754                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12378.320014                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36542.473825                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37655.726857                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 33422.458350                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 28577.586795                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 33609.336298                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 35814.945730                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 39930.978970                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16454.579592                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14179.493966                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14924.305956                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13292.645965                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10185.683049                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        84500                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        42250                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21978.035170                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25050.574532                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25535.418449                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 19182.644868                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18943.946385                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22092.732260                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24294.976745                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17509.934292                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     14425372                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        42395                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           882588                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            392                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.344401                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   108.150510                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024221                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023855                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.031072                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data     0.077174                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.041281                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027965                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027802                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.034810                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data     0.080686                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.044979                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16558.383994                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17221.784248                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17597.375388                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12389.939529                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38752.228326                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36802.187980                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 34278.467562                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29163.570105                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32809.746281                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 35773.601276                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 40588.964406                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16640.291904                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14175.371237                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15023.765457                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13407.463400                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10247.390965                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        31375                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        25100                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23020.846175                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24510.200664                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25943.139149                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19425.881509                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19646.982737                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21760.312263                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24685.512154                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 17735.575268                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     14877388                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        44459                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs           886775                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            413                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.776959                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   107.648910                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7475106                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7475106                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3650                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       124312                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1904102                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      2032064                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4908                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       268057                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2861568                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3134533                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           28                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2036                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         2064                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8313                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10472                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       108224                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       127009                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         8558                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       392369                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      4765670                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      5166597                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         8558                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       392369                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      4765670                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      5166597                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       651040                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       839202                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1534759                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3025001                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       246282                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       336402                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       580788                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1163472                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       144706                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       207290                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       344141                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       696137                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       110622                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       150055                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       275283                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       535960                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        29471                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        39849                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        67965                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       137285                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       897322                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data      1175604                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data      2115547                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4188473                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      1042028                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data      1382894                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data      2459688                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      4884610                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         6832                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6962                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         7151                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20945                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         6305                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         6510                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6865                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19680                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        13137                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        13472                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        14016                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40625                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9843427000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  13182169000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  26527501500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  49553097500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   8718556000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  12098346000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  21094064660                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  41910966660                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   3026616000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   4207308500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   6719819000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13953743500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   3607310000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   5223957500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data  10676266657                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  19507534157                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    382668000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    527867500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    968982000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1879517500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data        83500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        83500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  18561983000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  25280515000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  47621566160                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  91464064160                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  21588599000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  29487823500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  54341385160                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 105417807660                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1349798500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1371763500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1366987000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4088549000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1281894000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1318427500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1339823955                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3940145455                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2631692500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2690191000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2706810955                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   8028694455                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033258                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031139                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031722                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019190                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013983                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014140                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.014055                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008342                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.753465                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.722549                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.741268                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.444598                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.704298                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.715202                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.735773                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.344638                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062992                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.064065                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.061458                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036649                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024129                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023169                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023583                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.014098                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027877                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027101                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.027278                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.016354                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15119.542578                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15707.980915                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17284.473654                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16381.183841                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35400.703259                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35963.953841                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 36319.732260                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36022.325127                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20915.622020                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20296.726808                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19526.354023                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20044.536492                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 32609.336298                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 34813.618340                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 38782.876738                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36397.369500                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12984.561094                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13246.693769                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14257.073494                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13690.625341                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        83500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        83500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20685.977832                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21504.277801                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22510.285122                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21837.090548                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20717.868426                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21323.270981                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22092.795981                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21581.622209                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197570.038056                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197035.837403                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 191160.257307                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 195204.058248                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203313.877875                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 202523.425499                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 195167.364166                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200210.643039                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 200326.748877                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 199687.574228                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 193122.927725                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 197629.401969                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks      7483477                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7483477                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3222                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       130575                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1920030                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      2053827                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4922                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       261783                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2870322                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      3137027                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           26                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2099                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         2125                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8352                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10672                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       107753                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       126777                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         8144                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       392358                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data      4790352                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      5190854                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         8144                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       392358                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data      4790352                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      5190854                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       624647                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       868468                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1528213                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      3021328                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       253007                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       330590                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       582238                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1165835                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       151732                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       198469                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       344358                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       694559                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       112802                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       149235                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       277838                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total       539875                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        30976                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        38496                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        67864                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       137336                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            4                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       877654                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data      1199058                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data      2110451                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      4187163                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      1029386                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data      1397527                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data      2454809                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      4881722                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         6935                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6911                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         6765                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20611                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         6456                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         6468                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6500                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19424                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        13391                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        13379                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        13265                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40035                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9554770500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  13722884500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  26401240500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  49678895500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9526378000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  11636542500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  21578675477                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  42741595977                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   3041699000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   3963544500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   6809698000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13814941500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   3588203000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   5189095500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data  10959309429                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  19736607929                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    400391000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    515235000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    967704000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1883330000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       121500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       121500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  19081148500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  25359427000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  47979915977                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  92420491477                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  22122847500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  29322971500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  54789613977                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 106235432977                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1364610000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1364502500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1307720500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4036833000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1311207000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1311882500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1281361955                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3904451455                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2675817000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2676385000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2589082455                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7941284455                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032146                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031779                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031654                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019150                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014293                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.013838                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.014152                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008355                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.759328                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.714979                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.741745                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.443691                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.709737                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.716432                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.734971                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.347111                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.065334                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.060840                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.061199                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036668                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000004                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023636                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023411                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023602                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.014083                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027573                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027139                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.027311                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.016333                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15296.272135                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15801.255199                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17275.890534                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16442.734950                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37652.626212                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35199.317886                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 37061.606211                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36661.788312                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20046.522817                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 19970.597423                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19775.053868                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19890.234667                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31809.746281                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 34771.303649                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 39444.962277                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36557.736382                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12925.845816                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13384.117830                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14259.460097                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13713.301683                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        30375                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        30375                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21741.083046                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21149.458158                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22734.437320                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22072.341458                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21491.304039                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20982.042923                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22319.298152                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21761.876849                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196771.449171                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197439.227319                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 193306.799704                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 195858.182524                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203098.977695                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 202826.607916                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 197132.608462                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201011.709998                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 199822.044657                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 200043.725241                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 195181.489257                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 198358.547646                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         15696881                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.971340                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          558297724                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         15697393                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            35.566270                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements         15741403                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.971353                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          557979460                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         15741915                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            35.445463                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      11785355500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   478.712705                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     4.090332                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    22.639696                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst     6.528608                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.934986                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.007989                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.044218                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst     0.012751                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   478.989508                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst     3.251405                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    22.715639                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst     7.014801                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.935526                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.006350                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.044366                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst     0.013701                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999944                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        590046663                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       590046663                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    340808018                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    105888169                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     63991635                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst     47609902                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      558297724                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    340808018                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    105888169                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     63991635                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst     47609902                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       558297724                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    340808018                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    105888169                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     63991635                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst     47609902                       # number of overall hits
-system.cpu0.icache.overall_hits::total      558297724                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5595707                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1686311                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst      3834374                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst      4935088                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     16051480                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5595707                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1686311                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst      3834374                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst      4935088                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      16051480                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5595707                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1686311                       # number of overall misses
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-system.cpu0.icache.overall_misses::cpu3.inst      4935088                       # number of overall misses
-system.cpu0.icache.overall_misses::total     16051480                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22823417500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  52649440500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  66649232311                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 142122090311                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  22823417500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst  52649440500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst  66649232311                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 142122090311                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  22823417500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst  52649440500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst  66649232311                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 142122090311                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    346403725                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    107574480                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     67826009                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.demand_accesses::cpu3.inst     52544990                       # number of demand (read+write) accesses
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-system.cpu0.icache.overall_accesses::total    574349204                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016154                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015676                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.056533                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.093921                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.027947                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016154                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015676                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.056533                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst     0.093921                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.027947                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016154                       # miss rate for overall accesses
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-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.056533                       # miss rate for overall accesses
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-system.cpu0.icache.overall_miss_rate::total     0.027947                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13534.524474                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13730.909009                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13505.176060                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8854.142441                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13534.524474                       # average overall miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total  8854.142441                       # average overall miss latency
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-system.cpu0.icache.overall_avg_miss_latency::total  8854.142441                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        61485                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        589817883                       # Number of tag accesses
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+system.cpu0.icache.ReadReq_avg_miss_latency::total  8885.281230                       # average ReadReq miss latency
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+system.cpu0.icache.demand_avg_miss_latency::total  8885.281230                       # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13552.794209                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8885.281230                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        61852                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             3700                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             3678                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.617568                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.816748                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks     15696881                       # number of writebacks
-system.cpu0.icache.writebacks::total         15696881                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       354021                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       354021                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst       354021                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       354021                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst       354021                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       354021                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1686311                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3834374                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4581067                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     10101752                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      1686311                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst      3834374                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst      4581067                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     10101752                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      1686311                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst      3834374                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst      4581067                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     10101752                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21137106500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  48815066500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  58829212841                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 128781385841                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21137106500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  48815066500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  58829212841                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 128781385841                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21137106500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  48815066500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  58829212841                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 128781385841                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015676                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.056533                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.087184                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017588                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015676                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.056533                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.087184                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.017588                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015676                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.056533                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.087184                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.017588                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12534.524474                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12730.909009                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12841.814547                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12748.420852                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12534.524474                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12730.909009                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12841.814547                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12748.420852                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12534.524474                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12730.909009                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12841.814547                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12748.420852                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks     15741403                       # number of writebacks
+system.cpu0.icache.writebacks::total         15741403                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       354429                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total       354429                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst       354429                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total       354429                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst       354429                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total       354429                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1682310                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3897820                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4574015                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     10154145                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      1682310                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst      3897820                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst      4574015                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     10154145                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      1682310                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst      3897820                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst      4574015                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     10154145                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21043406500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  49603548000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  58927308844                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 129574263344                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21043406500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  49603548000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  58927308844                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 129574263344                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21043406500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  49603548000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  58927308844                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 129574263344                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015620                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.057531                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.087249                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017688                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015620                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.057531                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.087249                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.017688                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015620                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.057531                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.087249                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.017688                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12508.637825                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12725.971954                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12883.059816                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12760.726122                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12508.637825                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12725.971954                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12883.059816                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12760.726122                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12508.637825                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12725.971954                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12883.059816                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12760.726122                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1237,67 +1231,72 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                    31728                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong                31728                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4579                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        23199                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore            5                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        31723                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.882640                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev   157.206647                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047        31722    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks                    31832                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong                31832                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4623                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        23155                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            6                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples        31826                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean     1.131151                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev   163.231245                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-2047        31824     99.99%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::6144-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        31723                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        27783                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 25230.482669                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21865.634493                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 16058.224156                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        27633     99.46%     99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071            1      0.00%     99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          123      0.44%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143            5      0.02%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           12      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215            4      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        27783                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   2741941428                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.632141                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.482223                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1008648500     36.79%     36.79% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     1733292928     63.21%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   2741941428                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        23199     83.52%     83.52% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         4579     16.48%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkWaitTime::total        31826                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples        27784                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 25027.875756                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21593.645021                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 16285.465271                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767        18174     65.41%     65.41% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535         9447     34.00%     99.41% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071            1      0.00%     99.42% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839          131      0.47%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607            9      0.03%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375            1      0.00%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143            1      0.00%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911            8      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679            2      0.01%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215            5      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::491520-524287            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total        27784                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -2880889132                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     1.351726                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1013283500    -35.17%    -35.17% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    -3894172632    135.17%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -2880889132                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        23155     83.36%     83.36% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M         4623     16.64%    100.00% # Table walker page sizes translated
 system.cpu1.dtb.walker.walkPageSizes::total        27778                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31728                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31832                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31728                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31832                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27778                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27778                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        59506                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        59610                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    20241909                       # DTB read hits
-system.cpu1.dtb.read_misses                     24578                       # DTB read misses
-system.cpu1.dtb.write_hits                   18246308                       # DTB write hits
-system.cpu1.dtb.write_misses                     7150                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1186                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    20112265                       # DTB read hits
+system.cpu1.dtb.read_misses                     24546                       # DTB read misses
+system.cpu1.dtb.write_hits                   18343322                       # DTB write hits
+system.cpu1.dtb.write_misses                     7286                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        1188                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               5242                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   17924                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid               5429                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    141                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   18466                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   956                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   996                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     2537                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                20266487                       # DTB read accesses
-system.cpu1.dtb.write_accesses               18253458                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     2613                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                20136811                       # DTB read accesses
+system.cpu1.dtb.write_accesses               18350608                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         38488217                       # DTB hits
-system.cpu1.dtb.misses                          31728                       # DTB misses
-system.cpu1.dtb.accesses                     38519945                       # DTB accesses
+system.cpu1.dtb.hits                         38455587                       # DTB hits
+system.cpu1.dtb.misses                          31832                       # DTB misses
+system.cpu1.dtb.accesses                     38487419                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1327,131 +1326,130 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    20290                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                20290                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walks                    20094                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                20094                       # Table walker walks initiated with long descriptors
 system.cpu1.itb.walker.walksLongTerminationLevel::Level2          971                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17908                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        20290                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          20290    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        20290                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        18879                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 28298.930028                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 25145.287562                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 17574.390852                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        18719     99.15%     99.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          141      0.75%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143            3      0.02%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679            8      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215            3      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17728                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        20094                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          20094    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        20094                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        18699                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28327.343708                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25076.534832                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18332.547535                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        18529     99.09%     99.09% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          145      0.78%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143            7      0.04%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679            8      0.04%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215            6      0.03%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        18879                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        18699                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        17908     94.86%     94.86% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          971      5.14%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        18879                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        17728     94.81%     94.81% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          971      5.19%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        18699                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        20290                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        20290                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        20094                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        20094                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18879                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18879                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        39169                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   107574480                       # ITB inst hits
-system.cpu1.itb.inst_misses                     20290                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18699                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18699                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total        38793                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   107701123                       # ITB inst hits
+system.cpu1.itb.inst_misses                     20094                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1186                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                        1188                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               5242                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   13368                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid               5429                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    141                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   13720                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               107594770                       # ITB inst accesses
-system.cpu1.itb.hits                        107574480                       # DTB hits
-system.cpu1.itb.misses                          20290                       # DTB misses
-system.cpu1.itb.accesses                    107594770                       # DTB accesses
-system.cpu1.numCycles                      1186092617                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               107721217                       # ITB inst accesses
+system.cpu1.itb.hits                        107701123                       # DTB hits
+system.cpu1.itb.misses                          20094                       # DTB misses
+system.cpu1.itb.accesses                    107721217                       # DTB accesses
+system.cpu1.numCycles                      1188094365                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  107495721                       # Number of instructions committed
-system.cpu1.committedOps                    126075283                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            115907756                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                113126                       # Number of float alu accesses
-system.cpu1.num_func_calls                    6382091                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     16276077                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   115907756                       # number of integer instructions
-system.cpu1.num_fp_insts                       113126                       # number of float instructions
-system.cpu1.num_int_register_reads          166908100                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          91871167                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              184275                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              91240                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            27698310                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           27628060                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     38485648                       # number of memory refs
-system.cpu1.num_load_insts                   20241154                       # Number of load instructions
-system.cpu1.num_store_insts                  18244494                       # Number of store instructions
-system.cpu1.num_idle_cycles              1161627733.273481                       # Number of idle cycles
-system.cpu1.num_busy_cycles              24464883.726519                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.020626                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.979374                       # Percentage of idle cycles
-system.cpu1.Branches                         23916118                       # Number of branches fetched
+system.cpu1.committedInsts                  107621607                       # Number of instructions committed
+system.cpu1.committedOps                    126383134                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            116203246                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                115467                       # Number of float alu accesses
+system.cpu1.num_func_calls                    6450925                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     16259693                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   116203246                       # number of integer instructions
+system.cpu1.num_fp_insts                       115467                       # number of float instructions
+system.cpu1.num_int_register_reads          168004862                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          92163558                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              188871                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              91760                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads            27757608                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           27690244                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     38453101                       # number of memory refs
+system.cpu1.num_load_insts                   20111693                       # Number of load instructions
+system.cpu1.num_store_insts                  18341408                       # Number of store instructions
+system.cpu1.num_idle_cycles              1162766845.919452                       # Number of idle cycles
+system.cpu1.num_busy_cycles              25327519.080548                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.021318                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.978682                       # Percentage of idle cycles
+system.cpu1.Branches                         23943919                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 87373708     69.26%     69.26% # Class of executed instruction
-system.cpu1.op_class::IntMult                  271273      0.22%     69.47% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    11107      0.01%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             12264      0.01%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.49% # Class of executed instruction
-system.cpu1.op_class::MemRead                20241154     16.04%     85.54% # Class of executed instruction
-system.cpu1.op_class::MemWrite               18244494     14.46%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 87732322     69.37%     69.37% # Class of executed instruction
+system.cpu1.op_class::IntMult                  254511      0.20%     69.58% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    10291      0.01%     69.58% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             12383      0.01%     69.59% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.59% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.59% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.59% # Class of executed instruction
+system.cpu1.op_class::MemRead                20111693     15.90%     85.50% # Class of executed instruction
+system.cpu1.op_class::MemWrite               18341408     14.50%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 126154042                       # Class of executed instruction
-system.cpu2.branchPred.lookups               39396533                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         27362101                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect          1971184                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            28599658                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               20206635                       # Number of BTB hits
+system.cpu1.op_class::total                 126462650                       # Class of executed instruction
+system.cpu2.branchPred.lookups               39591395                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         27402166                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect          2021243                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            28606558                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               20093171                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            70.653415                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                4844874                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            318265                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            70.239737                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                4887391                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect            324081                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1481,59 +1479,61 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.walks                    92743                       # Table walker walks requested
-system.cpu2.dtb.walker.walksLong                92743                       # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         6709                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        28755                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples        92743                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0          92743    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total        92743                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples        35464                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 24952.261448                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 21836.970286                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 14872.403453                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-65535        35314     99.58%     99.58% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-196607          126      0.36%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-262143            2      0.01%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-327679           14      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::393216-458751            6      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total        35464                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks                    95006                       # Table walker walks requested
+system.cpu2.dtb.walker.walksLong                95006                       # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         6740                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        29708                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples        95006                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0          95006    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total        95006                       # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples        36448                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 25417.457748                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 22182.749988                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 16592.444485                       # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-65535        36232     99.41%     99.41% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::65536-131071            1      0.00%     99.41% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-196607          183      0.50%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-262143            9      0.02%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-327679            9      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::327680-393215            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::393216-458751            8      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::589824-655359            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total        36448                       # Table walker service (enqueue to completion) latency
 system.cpu2.dtb.walker.walksPending::samples   2000224000                       # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::0     2000224000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.dtb.walker.walksPending::total   2000224000                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K        28755     81.08%     81.08% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M         6709     18.92%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total        35464                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        92743                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K        29708     81.51%     81.51% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M         6740     18.49%    100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total        36448                       # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        95006                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        92743                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        35464                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        95006                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        36448                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        35464                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total       128207                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        36448                       # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total       131454                       # Table walker requests started/completed, data/inst
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    28135338                       # DTB read hits
-system.cpu2.dtb.read_misses                     77405                       # DTB read misses
-system.cpu2.dtb.write_hits                   24723604                       # DTB write hits
-system.cpu2.dtb.write_misses                    15338                       # DTB write misses
-system.cpu2.dtb.flush_tlb                        1186                       # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits                    28518980                       # DTB read hits
+system.cpu2.dtb.read_misses                     79318                       # DTB read misses
+system.cpu2.dtb.write_hits                   24832866                       # DTB write hits
+system.cpu2.dtb.write_misses                    15688                       # DTB write misses
+system.cpu2.dtb.flush_tlb                        1188                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid               6517                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid                    195                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                   22464                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                       74                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                  2032                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid               6544                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid                    184                       # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries                   22314                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                       75                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                  2052                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                     3778                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                28212743                       # DTB read accesses
-system.cpu2.dtb.write_accesses               24738942                       # DTB write accesses
+system.cpu2.dtb.perms_faults                     3674                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                28598298                       # DTB read accesses
+system.cpu2.dtb.write_accesses               24848554                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         52858942                       # DTB hits
-system.cpu2.dtb.misses                          92743                       # DTB misses
-system.cpu2.dtb.accesses                     52951685                       # DTB accesses
+system.cpu2.dtb.hits                         53351846                       # DTB hits
+system.cpu2.dtb.misses                          95006                       # DTB misses
+system.cpu2.dtb.accesses                     53446852                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1563,86 +1563,86 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.walks                    27058                       # Table walker walks requested
-system.cpu2.itb.walker.walksLong                27058                       # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1852                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22698                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples        27058                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0          27058    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total        27058                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples        24550                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 28387.494908                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 25558.389161                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 15951.956543                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767        12868     52.42%     52.42% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535        11496     46.83%     99.24% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839          141      0.57%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607           26      0.11%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375            3      0.01%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::229376-262143            3      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::262144-294911            4      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::294912-327679            5      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::393216-425983            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total        24550                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks                    27923                       # Table walker walks requested
+system.cpu2.itb.walker.walksLong                27923                       # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1838                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3        23508                       # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples        27923                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0          27923    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total        27923                       # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples        25346                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 28940.858518                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 25854.889269                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 17791.815030                       # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767        13319     52.55%     52.55% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535        11735     46.30%     98.85% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839          221      0.87%     99.72% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607           46      0.18%     99.90% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375            3      0.01%     99.91% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::229376-262143            3      0.01%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::262144-294911           12      0.05%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::294912-327679            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::327680-360447            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total        25346                       # Table walker service (enqueue to completion) latency
 system.cpu2.itb.walker.walksPending::samples   2000197500                       # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::0     2000197500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu2.itb.walker.walksPending::total   2000197500                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K        22698     92.46%     92.46% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M         1852      7.54%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total        24550                       # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K        23508     92.75%     92.75% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M         1838      7.25%    100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total        25346                       # Table walker page sizes translated
 system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27058                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27058                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27923                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27923                       # Table walker requests started/completed, data/inst
 system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24550                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24550                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total        51608                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    67882722                       # ITB inst hits
-system.cpu2.itb.inst_misses                     27058                       # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        25346                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total        25346                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total        53269                       # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits                    67809364                       # ITB inst hits
+system.cpu2.itb.inst_misses                     27923                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                        1186                       # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb                        1188                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid               6517                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid                    195                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                   16669                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid               6544                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid                    184                       # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries                   17096                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                    53735                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                    54805                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                67909780                       # ITB inst accesses
-system.cpu2.itb.hits                         67882722                       # DTB hits
-system.cpu2.itb.misses                          27058                       # DTB misses
-system.cpu2.itb.accesses                     67909780                       # DTB accesses
-system.cpu2.numCycles                      6659969764                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                67837287                       # ITB inst accesses
+system.cpu2.itb.hits                         67809364                       # DTB hits
+system.cpu2.itb.misses                          27923                       # DTB misses
+system.cpu2.itb.accesses                     67837287                       # DTB accesses
+system.cpu2.numCycles                      6729019952                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                  144540812                       # Number of instructions committed
-system.cpu2.committedOps                    169698177                       # Number of ops (including micro ops) committed
-system.cpu2.discardedOps                     13684727                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends                     1569                       # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles                 95895764240                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi                             46.076742                       # CPI: cycles per instruction
-system.cpu2.ipc                              0.021703                       # IPC: instructions per cycle
+system.cpu2.committedInsts                  145507421                       # Number of instructions committed
+system.cpu2.committedOps                    170762991                       # Number of ops (including micro ops) committed
+system.cpu2.discardedOps                     13321557                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends                     1585                       # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles                 95906188119                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi                             46.245201                       # CPI: cycles per instruction
+system.cpu2.ipc                              0.021624                       # IPC: instructions per cycle
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                      269319044                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                     6390650720                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               73106797                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted         49433479                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect          3258695                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups            49334876                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits               35656978                       # Number of BTB hits
+system.cpu2.tickCycles                      269790363                       # Number of cycles that the object actually ticked
+system.cpu2.idleCycles                     6459229589                       # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups               72990389                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted         49393926                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect          3261178                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups            49526964                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits               35642873                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            72.275398                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                9555620                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect            104634                       # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct            71.966602                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                9524201                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect            103362                       # Number of incorrect RAS predictions.
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1672,88 +1672,85 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.walks                   494873                       # Table walker walks requested
-system.cpu3.dtb.walker.walksLong               494873                       # Table walker walks initiated with long descriptors
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8038                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        49628                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore       307549                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples       187324                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean  2356.267750                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 14281.156299                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-65535       186079     99.34%     99.34% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-131071          697      0.37%     99.71% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::131072-196607          387      0.21%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::196608-262143           69      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::262144-327679           51      0.03%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::327680-393215           11      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::393216-458751           12      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::458752-524287           14      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total       187324                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples       229131                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 22686.146789                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 18317.810397                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 18596.429018                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-65535       224486     97.97%     97.97% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3513      1.53%     99.51% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-196607          846      0.37%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::196608-262143           43      0.02%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::262144-327679          153      0.07%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::327680-393215           48      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::393216-458751           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::458752-524287           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total       229131                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -24996742720                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean    -0.101724                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-3 -25553833720    102.23%    102.23% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-7    304691500     -1.22%    101.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-11    107266500     -0.43%    100.58% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-15     67844000     -0.27%    100.31% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-19     24788500     -0.10%    100.21% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-23     14749500     -0.06%    100.15% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-27     13689000     -0.05%    100.10% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-31     19439000     -0.08%    100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::32-35      4284000     -0.02%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::36-39       178500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::40-43        52500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::44-47       105500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::48-51         2500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -24996742720                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K        49628     86.06%     86.06% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::2M         8038     13.94%    100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total        57666                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       494873                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walks                   500429                       # Table walker walks requested
+system.cpu3.dtb.walker.walksLong               500429                       # Table walker walks initiated with long descriptors
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8187                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        49422                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore       313054                       # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples       187375                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean  2308.042695                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 13865.789258                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-65535       186198     99.37%     99.37% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-131071          657      0.35%     99.72% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::131072-196607          362      0.19%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::196608-262143           70      0.04%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::262144-327679           56      0.03%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::327680-393215           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::393216-458751            9      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::458752-524287           11      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total       187375                       # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples       233412                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 22762.724282                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 18452.196764                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 18647.508849                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-65535       228859     98.05%     98.05% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3345      1.43%     99.48% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-196607          881      0.38%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::196608-262143           33      0.01%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::262144-327679          195      0.08%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::327680-393215           58      0.02%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::393216-458751           30      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::458752-524287           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total       233412                       # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -23888540384                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean    -0.243050                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-3 -24451568384    102.36%    102.36% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-7    309528500     -1.30%    101.06% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-11    106605000     -0.45%    100.61% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-15     67439500     -0.28%    100.33% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-19     25633500     -0.11%    100.23% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-23     15083500     -0.06%    100.16% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-27     13632500     -0.06%    100.11% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-31     20996500     -0.09%    100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::32-35      3974500     -0.02%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::36-39       102000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::40-43        25000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::44-47         6000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::48-51         1500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -23888540384                       # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K        49422     85.79%     85.79% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::2M         8187     14.21%    100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total        57609                       # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       500429                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       494873                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        57666                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       500429                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        57609                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        57666                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total       552539                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        57609                       # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total       558038                       # Table walker requests started/completed, data/inst
 system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                    58275132                       # DTB read hits
-system.cpu3.dtb.read_misses                    338945                       # DTB read misses
-system.cpu3.dtb.write_hits                   45320334                       # DTB write hits
-system.cpu3.dtb.write_misses                   155928                       # DTB write misses
-system.cpu3.dtb.flush_tlb                        1185                       # Number of times complete TLB was flushed
+system.cpu3.dtb.read_hits                    58164219                       # DTB read hits
+system.cpu3.dtb.read_misses                    342154                       # DTB read misses
+system.cpu3.dtb.write_hits                   45137816                       # DTB write hits
+system.cpu3.dtb.write_misses                   158275                       # DTB write misses
+system.cpu3.dtb.flush_tlb                        1187                       # Number of times complete TLB was flushed
 system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.dtb.flush_tlb_mva_asid              11379                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.dtb.flush_tlb_asid                    309                       # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries                   30010                       # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults                       82                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults                  4724                       # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_tlb_mva_asid              11250                       # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dtb.flush_tlb_asid                    304                       # Number of times TLB was flushed by ASID
+system.cpu3.dtb.flush_entries                   29745                       # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults                       69                       # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults                  4820                       # Number of TLB faults due to prefetch
 system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults                    33145                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                58614077                       # DTB read accesses
-system.cpu3.dtb.write_accesses               45476262                       # DTB write accesses
+system.cpu3.dtb.perms_faults                    32652                       # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses                58506373                       # DTB read accesses
+system.cpu3.dtb.write_accesses               45296091                       # DTB write accesses
 system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                        103595466                       # DTB hits
-system.cpu3.dtb.misses                         494873                       # DTB misses
-system.cpu3.dtb.accesses                    104090339                       # DTB accesses
+system.cpu3.dtb.hits                        103302035                       # DTB hits
+system.cpu3.dtb.misses                         500429                       # DTB misses
+system.cpu3.dtb.accesses                    103802464                       # DTB accesses
 system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1783,386 +1780,388 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.itb.walker.walks                    60079                       # Table walker walks requested
-system.cpu3.itb.walker.walksLong                60079                       # Table walker walks initiated with long descriptors
-system.cpu3.itb.walker.walksLongTerminationLevel::Level2         1942                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksLongTerminationLevel::Level3        41391                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore         8262                       # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples        51817                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean  1695.563232                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev 10747.357060                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-65535        51612     99.60%     99.60% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-131071           80      0.15%     99.76% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::131072-196607          107      0.21%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::196608-262143           10      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::262144-327679            7      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total        51817                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples        51595                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 29163.077818                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 24579.723425                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 21924.280551                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-32767        28123     54.51%     54.51% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-65535        22407     43.43%     97.94% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::65536-98303          307      0.60%     98.53% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::98304-131071           32      0.06%     98.59% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::131072-163839          434      0.84%     99.43% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::163840-196607          175      0.34%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::196608-229375           23      0.04%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::229376-262143           26      0.05%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::262144-294911           39      0.08%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::294912-327679           12      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::327680-360447            1      0.00%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::393216-425983            9      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total        51595                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -33589148812                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean     1.086684                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0     2957203824     -8.80%     -8.80% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1   -36586535136    108.92%    100.12% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2       35384500     -0.11%    100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3        4248500     -0.01%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4         527000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5          22500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -33589148812                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K        41391     95.52%     95.52% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::2M         1942      4.48%    100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total        43333                       # Table walker page sizes translated
+system.cpu3.itb.walker.walks                    60030                       # Table walker walks requested
+system.cpu3.itb.walker.walksLong                60030                       # Table walker walks initiated with long descriptors
+system.cpu3.itb.walker.walksLongTerminationLevel::Level2         1961                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksLongTerminationLevel::Level3        41132                       # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore         8185                       # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples        51845                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean  1585.842415                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev  9699.543374                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-32767        51363     99.07%     99.07% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-65535          302      0.58%     99.65% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-98303           36      0.07%     99.72% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-131071           44      0.08%     99.81% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::131072-163839           73      0.14%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::163840-196607           15      0.03%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::196608-229375            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::229376-262143            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::262144-294911            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total        51845                       # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples        51278                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 29392.673271                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 24917.769531                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 21411.451197                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-65535        50198     97.89%     97.89% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::65536-131071          365      0.71%     98.61% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::131072-196607          621      1.21%     99.82% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::196608-262143           29      0.06%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::262144-327679           49      0.10%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::327680-393215            9      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::393216-458751            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total        51278                       # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -28186036180                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean     0.973417                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev     0.149857                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0     -706639900      2.51%      2.51% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1   -27517172780     97.63%    100.13% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2       33476500     -0.12%    100.02% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3        3852500     -0.01%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4         369000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5          47500     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::6          31000     -0.00%    100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -28186036180                       # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K        41132     95.45%     95.45% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::2M         1961      4.55%    100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total        43093                       # Table walker page sizes translated
 system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        60079                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total        60079                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        60030                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total        60030                       # Table walker requests started/completed, data/inst
 system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        43333                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total        43333                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total       103412                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                    52677682                       # ITB inst hits
-system.cpu3.itb.inst_misses                     60079                       # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        43093                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total        43093                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total       103123                       # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits                    52557456                       # ITB inst hits
+system.cpu3.itb.inst_misses                     60030                       # ITB inst misses
 system.cpu3.itb.read_hits                           0                       # DTB read hits
 system.cpu3.itb.read_misses                         0                       # DTB read misses
 system.cpu3.itb.write_hits                          0                       # DTB write hits
 system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.flush_tlb                        1185                       # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb                        1187                       # Number of times complete TLB was flushed
 system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.itb.flush_tlb_mva_asid              11379                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.itb.flush_tlb_asid                    309                       # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries                   23578                       # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_tlb_mva_asid              11250                       # Number of times TLB was flushed by MVA & ASID
+system.cpu3.itb.flush_tlb_asid                    304                       # Number of times TLB was flushed by ASID
+system.cpu3.itb.flush_entries                   23210                       # Number of entries that have been flushed from TLB
 system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults                   114813                       # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults                   115031                       # Number of TLB faults due to permissions restrictions
 system.cpu3.itb.read_accesses                       0                       # DTB read accesses
 system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                52737761                       # ITB inst accesses
-system.cpu3.itb.hits                         52677682                       # DTB hits
-system.cpu3.itb.misses                          60079                       # DTB misses
-system.cpu3.itb.accesses                     52737761                       # DTB accesses
-system.cpu3.numCycles                       367538464                       # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses                52617486                       # ITB inst accesses
+system.cpu3.itb.hits                         52557456                       # DTB hits
+system.cpu3.itb.misses                          60030                       # DTB misses
+system.cpu3.itb.accesses                     52617486                       # DTB accesses
+system.cpu3.numCycles                       367681719                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles         137661230                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                     325116146                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   73106797                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches          45212598                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                    207107906                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                7385298                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles                   1491112                       # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles                7917                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles             2707                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles      2935817                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles        92613                       # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles         5851                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                 52545073                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes              2005603                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes                  24026                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples         352997650                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.078283                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.326168                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles         137382452                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                     324487112                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                   72990389                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches          45167074                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                    207382227                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                7378767                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles                   1499130                       # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles                9416                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles             2414                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles      2929845                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles        92895                       # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles         5499                       # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines                 52424871                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes              2006412                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes                  23984                       # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples         352993106                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.076120                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.324101                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0               272813729     77.28%     77.28% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                10027908      2.84%     80.13% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                10164479      2.88%     83.01% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 7468497      2.12%     85.12% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                15406630      4.36%     89.49% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                 5031910      1.43%     90.91% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 5399943      1.53%     92.44% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                 4793152      1.36%     93.80% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                21891402      6.20%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0               272962947     77.33%     77.33% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                10013633      2.84%     80.16% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                10141075      2.87%     83.04% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                 7427569      2.10%     85.14% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                15412828      4.37%     89.51% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                 5010537      1.42%     90.93% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                 5410828      1.53%     92.46% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                 4793943      1.36%     93.82% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                21819746      6.18%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total           352997650                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.198909                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.884577                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles               112522162                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles            171201406                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                 59221662                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles              7151544                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles               2899090                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved            10994019                       # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred               804734                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts             355281721                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts              2474096                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles               2899090                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles               116622448                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles               14081573                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles     135939902                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                 62181324                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles             21271328                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts             346993975                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                66296                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents               1234254                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                930282                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents              10943562                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.FullRegisterEvents            2087                       # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands          331516858                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            531452942                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups       410096361                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups           485069                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps            278766720                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                52750133                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts           7968822                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts       6860328                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                 39681669                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads            56098818                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores           47638464                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          7335407                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         7944863                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                 329650835                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded            7964776                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                329496224                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued           469719                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined       44173010                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     28338373                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved        197137                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples    352997650                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        0.933423                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.659576                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total           352993106                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.198515                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       0.882522                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles               112311908                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles            171536917                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                 59078029                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles              7166258                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles               2898243                       # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved            10967565                       # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred               802193                       # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts             354637256                       # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts              2468190                       # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles               2898243                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles               116412746                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles               14091886                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles     135873689                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                 62053830                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles             21660921                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts             346387617                       # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents                69362                       # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents               1230764                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents                966889                       # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents              11283496                       # Number of times rename has blocked due to SQ full
+system.cpu3.rename.FullRegisterEvents            2101                       # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands          331152482                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups            530946274                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups       409391445                       # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups           488669                       # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps            278384590                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                52767887                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts           7985124                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts       6877230                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                 39792362                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads            55963963                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores           47449628                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads          7288791                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores         7899727                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                 329013774                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded            7979579                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                328894803                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued           473789                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined       44157935                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined     28349943                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved        195322                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples    352993106                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        0.931732                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.657853                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0          224922038     63.72%     63.72% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1           52868564     14.98%     78.69% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2           24171570      6.85%     85.54% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3           17197419      4.87%     90.41% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4           12806059      3.63%     94.04% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5            9032778      2.56%     96.60% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6            6064654      1.72%     98.32% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7            3560331      1.01%     99.33% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8            2374237      0.67%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0          225053646     63.76%     63.76% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1           52887195     14.98%     78.74% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2           24125112      6.83%     85.57% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3           17152120      4.86%     90.43% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4           12799961      3.63%     94.06% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5            9006883      2.55%     96.61% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6            6061659      1.72%     98.33% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7            3555429      1.01%     99.33% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8            2351101      0.67%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total      352997650                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total      352993106                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                1654999     25.37%     25.37% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                 15899      0.24%     25.61% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                   1445      0.02%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.63% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead               2663997     40.83%     66.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite              2188300     33.54%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                1666434     25.55%     25.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                 16334      0.25%     25.81% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                   1493      0.02%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.83% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead               2666569     40.89%     66.72% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite              2170161     33.28%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass               19      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu            223294743     67.77%     67.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult              773232      0.23%     68.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                39732      0.01%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.02% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc         41118      0.01%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead            59435929     18.04%     86.07% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite           45911451     13.93%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass               37      0.00%      0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu            222970071     67.79%     67.79% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult              784272      0.24%     68.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                39650      0.01%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                183      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   1      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               1      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.04% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc         42230      0.01%     68.06% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.06% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.06% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.06% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead            59327329     18.04%     86.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite           45731029     13.90%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total             329496224                       # Type of FU issued
-system.cpu3.iq.rate                          0.896495                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                    6524640                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.019802                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads        1018336747                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes        381842202                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses    317599035                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads             647710                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes            321899                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses       289386                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses             335674602                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                 346243                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads         2638413                       # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total             328894803                       # Type of FU issued
+system.cpu3.iq.rate                          0.894510                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                    6520991                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.019827                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads        1017124188                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes        381195731                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses    316969788                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads             653304                       # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes            324459                       # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses       290942                       # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses             335066450                       # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses                 349307                       # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads         2611645                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      8879523                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses        11866                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation       381459                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores      4873286                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads      8878101                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses        11627                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation       374989                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores      4859757                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads      2106312                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked      4209032                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads      2089653                       # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked      4248814                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles               2899090                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                8833562                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles              4011376                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts          337691030                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts           991613                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts             56098818                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts            47638464                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts           6709459                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                120203                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents              3844571                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents        381459                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect       1469292                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect      1295892                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts             2765184                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts            325759751                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts             58266124                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts          3247625                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles               2898243                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                8732301                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles              4121646                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts          337068759                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts           994758                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts             55963963                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts            47449628                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts           6728240                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                117681                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents              3958014                       # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents        374989                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect       1476989                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect      1294241                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts             2771230                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts            325158275                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts             58155452                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts          3242017                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        75419                       # number of nop insts executed
-system.cpu3.iew.exec_refs                   103584875                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                60432321                       # Number of branches executed
-system.cpu3.iew.exec_stores                  45318751                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.886328                       # Inst execution rate
-system.cpu3.iew.wb_sent                     318561323                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                    317888421                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                157110188                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                272714221                       # num instructions consuming a value
-system.cpu3.iew.wb_rate                      0.864912                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.576098                       # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts       44200110                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls        7767639                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts          2464984                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples    345475072                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.849389                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.847862                       # Number of insts commited each cycle
+system.cpu3.iew.exec_nop                        75406                       # number of nop insts executed
+system.cpu3.iew.exec_refs                   103291863                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                60348156                       # Number of branches executed
+system.cpu3.iew.exec_stores                  45136411                       # Number of stores executed
+system.cpu3.iew.exec_rate                    0.884347                       # Inst execution rate
+system.cpu3.iew.wb_sent                     317931631                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                    317260730                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                156804040                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                272237503                       # num instructions consuming a value
+system.cpu3.iew.wb_rate                      0.862868                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.575983                       # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts       44184156                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls        7784257                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts          2469882                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples    345475115                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     0.847631                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.845112                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0    238897207     69.15%     69.15% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1     51619563     14.94%     84.09% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2     18609130      5.39%     89.48% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      8398025      2.43%     91.91% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4      6043748      1.75%     93.66% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5      3655661      1.06%     94.72% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6      3455010      1.00%     95.72% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7      2146483      0.62%     96.34% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8     12650245      3.66%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0    238965063     69.17%     69.17% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1     51652898     14.95%     84.12% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2     18588674      5.38%     89.50% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3      8404155      2.43%     91.93% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4      6041826      1.75%     93.68% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5      3641114      1.05%     94.74% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6      3441360      1.00%     95.73% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7      2148532      0.62%     96.36% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8     12591493      3.64%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total    345475072                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts           249760952                       # Number of instructions committed
-system.cpu3.commit.committedOps             293442596                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total    345475115                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts           249281112                       # Number of instructions committed
+system.cpu3.commit.committedOps             292835413                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                      89984472                       # Number of memory references committed
-system.cpu3.commit.loads                     47219294                       # Number of loads committed
-system.cpu3.commit.membars                    1969895                       # Number of memory barriers committed
-system.cpu3.commit.branches                  55759591                       # Number of branches committed
-system.cpu3.commit.fp_insts                    278553                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                269644169                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             7403511                       # Number of function calls committed.
+system.cpu3.commit.refs                      89675732                       # Number of memory references committed
+system.cpu3.commit.loads                     47085861                       # Number of loads committed
+system.cpu3.commit.membars                    1972703                       # Number of memory barriers committed
+system.cpu3.commit.branches                  55678709                       # Number of branches committed
+system.cpu3.commit.fp_insts                    279951                       # Number of committed floating point instructions.
+system.cpu3.commit.int_insts                269023900                       # Number of committed integer instructions.
+system.cpu3.commit.function_calls             7382684                       # Number of function calls committed.
 system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu       202786729     69.11%     69.11% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult         605783      0.21%     69.31% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv           30019      0.01%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc        35593      0.01%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead       47219294     16.09%     85.43% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite      42765178     14.57%    100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu       202481834     69.15%     69.15% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult         611500      0.21%     69.35% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv           29936      0.01%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.36% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc        36411      0.01%     69.38% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.38% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.38% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.38% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead       47085861     16.08%     85.46% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite      42589871     14.54%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total        293442596                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events             12650245                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                   668392773                       # The number of ROB reads
-system.cpu3.rob.rob_writes                  682819370                       # The number of ROB writes
-system.cpu3.timesIdled                        2353613                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                       14540814                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                 98630935405                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                  249760952                       # Number of Instructions Simulated
-system.cpu3.committedOps                    293442596                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.471561                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.471561                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.679551                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.679551                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads               384013216                       # number of integer regfile reads
-system.cpu3.int_regfile_writes              227255326                       # number of integer regfile writes
-system.cpu3.fp_regfile_reads                   562445                       # number of floating regfile reads
-system.cpu3.fp_regfile_writes                  347476                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                 69354543                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                70004499                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads              654418825                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes               7814462                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq                40238                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40238                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136511                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136511                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47686                       # Packet count per connected master and slave (bytes)
+system.cpu3.commit.op_class_0::total        292835413                       # Class of committed instruction
+system.cpu3.commit.bw_lim_events             12591493                       # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads                   667852271                       # The number of ROB reads
+system.cpu3.rob.rob_writes                  681568770                       # The number of ROB writes
+system.cpu3.timesIdled                        2347442                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                       14688613                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                 98704312464                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                  249281112                       # Number of Instructions Simulated
+system.cpu3.committedOps                    292835413                       # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi                              1.474968                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        1.474968                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              0.677981                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        0.677981                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads               383320839                       # number of integer regfile reads
+system.cpu3.int_regfile_writes              226802116                       # number of integer regfile writes
+system.cpu3.fp_regfile_reads                   566354                       # number of floating regfile reads
+system.cpu3.fp_regfile_writes                  353692                       # number of floating regfile writes
+system.cpu3.cc_regfile_reads                 69391716                       # number of cc regfile reads
+system.cpu3.cc_regfile_writes                70028526                       # number of cc regfile writes
+system.cpu3.misc_regfile_reads              653217985                       # number of misc regfile reads
+system.cpu3.misc_regfile_writes               7838267                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq                40272                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40272                       # Transaction distribution
+system.iobus.trans_dist::WriteReq              136541                       # Transaction distribution
+system.iobus.trans_dist::WriteResp             136541                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47702                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -2171,19 +2170,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29444                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122464                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       122584                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230962                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       230962                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353498                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47706                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353626                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47722                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -2192,21 +2189,20 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155640                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total       155714                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334280                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334280                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7491974                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             34324500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492080                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             34502500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                 5500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer2.occupancy               217500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
@@ -2217,72 +2213,66 @@ system.iobus.reqLayer16.occupancy                5500                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            13360500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            12266000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              141000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            21519500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            21520500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           257935387                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy               46500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           257733143                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            59729000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            58894000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            75398000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            75406000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115459                       # number of replacements
-system.iocache.tags.tagsinuse               10.420601                       # Cycle average of tags in use
+system.iocache.tags.replacements               115463                       # number of replacements
+system.iocache.tags.tagsinuse               10.424920                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115479                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13089166487009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.547306                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.873295                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221707                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.429581                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651288                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13089166486009                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     3.544579                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.880341                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.221536                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.430021                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651557                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039650                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039686                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039686                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8817                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8854                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8817                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8857                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
-system.iocache.overall_misses::total             8853                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide   1078707234                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1078707234                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   6251807909                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   6251807909                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   1078707234                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1078707234                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   1078707234                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1078707234                       # number of overall miss cycles
+system.iocache.overall_misses::realview.ide         8817                       # number of overall misses
+system.iocache.overall_misses::total             8857                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide   1102393747                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1102393747                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   6261704640                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   6261704640                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide   1102393747                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1102393747                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide   1102393747                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1102393747                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8817                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8854                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8817                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8857                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8817                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8857                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -2296,506 +2286,507 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 122399.549983                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 121887.823051                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58612.164451                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 58612.164451                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 122399.549983                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 121846.519146                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 122399.549983                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 121846.519146                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         22659                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 125030.480549                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 124507.990400                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58704.948624                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 58704.948624                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 125030.480549                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 124465.817658                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 125030.480549                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 124465.817658                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         24279                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 2381                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 2397                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.516590                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.128911                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide         5719                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         5719                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        48024                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        48024                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         5719                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         5719                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         5719                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         5719                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide    792757234                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    792757234                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3850607909                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3850607909                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide    792757234                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    792757234                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide    792757234                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    792757234                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.648928                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.646215                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.450236                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.450236                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.648928                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.645996                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.648928                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.645996                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138618.155971                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 138618.155971                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80180.907650                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80180.907650                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 138618.155971                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 138618.155971                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 138618.155971                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 138618.155971                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::realview.ide         5695                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         5695                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide        48080                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        48080                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         5695                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         5695                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide         5695                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         5695                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide    817643747                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    817643747                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3857704640                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3857704640                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide    817643747                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    817643747                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide    817643747                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    817643747                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.645911                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.643212                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.450761                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.450761                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide     0.645911                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.642994                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide     0.645911                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.642994                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143572.211940                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 143572.211940                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.121464                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.121464                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 143572.211940                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 143572.211940                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 143572.211940                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 143572.211940                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1137204                       # number of replacements
-system.l2c.tags.tagsinuse                65362.357170                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   47194222                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1199974                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    39.329370                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1138666                       # number of replacements
+system.l2c.tags.tagsinuse                65322.262178                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   47289153                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1201213                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    39.367833                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36812.759669                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   141.825850                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   212.294111                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3568.454051                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     8068.997871                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    31.153423                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    51.715903                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      455.445147                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2127.472553                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    35.646762                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker    56.154607                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1628.641788                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     3512.634896                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker    79.313177                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.itb.walker   110.411472                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     2677.526600                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     5791.909290                       # Average occupied blocks per requestor
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-system.l2c.ReadReq_hits::total                 963487                       # number of ReadReq hits
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-system.l2c.UpgradeReq_hits::cpu3.data            2703                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                9268                       # number of UpgradeReq hits
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-system.l2c.InvalidateReq_hits::cpu3.data       226607                       # number of InvalidateReq hits
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-system.l2c.ReadReq_misses::cpu1.itb.walker          326                       # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu2.itb.walker          343                       # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::cpu2.data          5760                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data          9480                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             33702                       # number of UpgradeReq misses
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+system.l2c.tags.occ_blocks::cpu0.inst     3683.589947                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     7937.199418                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu1.itb.walker    49.489312                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      262.199860                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1950.255648                       # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu2.itb.walker    62.743334                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     1641.772402                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     3638.516325                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.dtb.walker    77.227279                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.itb.walker   111.401868                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst     2775.336167                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data     5846.563924                       # Average occupied blocks per requestor
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+system.l2c.overall_miss_latency::cpu2.data  13186251500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.dtb.walker    141420500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.itb.walker    125786000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst   3813703499                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data  26044712000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    57743248999                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker       158459                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker       109354                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        56333                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker        42146                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker       154003                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker        59515                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.dtb.walker       288282                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.itb.walker       110699                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             978791                       # number of ReadReq accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::writebacks      7483477                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackDirty_accesses::total      7483477                       # number of WritebackDirty accesses(hits+misses)
+system.l2c.WritebackClean_accesses::writebacks     15738935                       # number of WritebackClean accesses(hits+misses)
+system.l2c.WritebackClean_accesses::total     15738935                       # number of WritebackClean accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data        17639                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5890                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data         7319                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data        12060                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           42908                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu3.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       827795                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       240563                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data       329220                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data       571155                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          1968733                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst      5595707                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst      1686311                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst      3834374                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst      4581002                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total      15697394                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      2600331                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       825217                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data      1086282                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data      1944316                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      6456146                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       687578                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       110622                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu2.data       150055                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu3.data       275283                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total      1223538                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       158170                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       109277                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         5595707                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         3428126                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        57050                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker        42798                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         1686311                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1065780                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker       148942                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker        57299                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst         3834374                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data         1415502                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.dtb.walker       286474                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.itb.walker       109434                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst         4581002                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data         2515471                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            25091717                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       158170                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       109277                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        5595707                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        3428126                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        57050                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker        42798                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        1686311                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1065780                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker       148942                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker        57299                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst        3834374                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data        1415502                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.dtb.walker       286474                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.itb.walker       109434                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst        4581002                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data        2515471                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           25091717                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007953                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012208                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.006415                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.007617                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002571                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.005986                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003543                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.008517                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.006145                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784316                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783354                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.795470                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data     0.778133                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.784315                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_accesses::cpu3.data            4                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             5                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       827854                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       247117                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data       323309                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data       572672                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total          1970952                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst      5587852                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst      1682310                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst      3897820                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst      4573932                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total      15741914                       # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data      2607237                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data       807355                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data      1105395                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data      1937941                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total      6457928                       # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data       684118                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data       112802                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu2.data       149235                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu3.data       277838                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total      1223993                       # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker       158459                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker       109354                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst         5587852                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         3435091                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        56333                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker        42146                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst         1682310                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data         1054472                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker       154003                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker        59515                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst         3897820                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data         1428704                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.dtb.walker       288282                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.itb.walker       110699                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst         4573932                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data         2510613                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total            25149585                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker       158459                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker       109354                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst        5587852                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        3435091                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        56333                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker        42146                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst        1682310                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data        1054472                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker       154003                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker        59515                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst        3897820                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data        1428704                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.dtb.walker       288282                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.itb.walker       110699                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst        4573932                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data        2510613                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total           25149585                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007560                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011394                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.007083                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.007782                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002929                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.007729                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003549                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.008374                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.006163                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.780203                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.770968                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.796147                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data     0.780846                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.781836                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu3.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.220745                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.187913                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.190587                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data     0.171036                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.197269                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006447                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004247                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.005859                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005808                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.005880                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041967                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.033051                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.035730                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.040646                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.039380                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.575191                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.171783                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu2.data     0.176055                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu3.data     0.176822                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.400140                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007953                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.012208                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006447                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.085137                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.006415                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.007617                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.004247                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.068006                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002571                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.005986                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.005859                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.071747                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003543                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.itb.walker     0.008517                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.005808                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.070252                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.029527                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007953                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.012208                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006447                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.085137                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.006415                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.007617                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004247                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.068006                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.002571                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.005986                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.005859                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.071747                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003543                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.itb.walker     0.008517                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.005808                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.070252                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.029527                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 136609.289617                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138636.503067                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 136240.208877                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 138790.087464                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 138687.192118                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 137583.690987                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 77887.359409                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41235.825893                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 42800.781250                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 43269.989451                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 24967.909916                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130893.938724                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 132452.633676                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 146905.863566                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 73586.376394                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131591.873778                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133654.513889                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 135819.070132                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 81884.712040                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 132981.007553                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 135099.425450                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 141054.417422                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 78735.167675                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130472.951639                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 138899.178590                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 155632.611554                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total 28032.641865                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136609.289617                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138636.503067                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 131591.873778                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 131679.307110                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 136240.208877                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker 138790.087464                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 133654.513889                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 133464.173182                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 138687.192118                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.itb.walker 137583.690987                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 135819.070132                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 144289.076824                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 76421.749493                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136609.289617                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138636.503067                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 131591.873778                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 131679.307110                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 136240.208877                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker 138790.087464                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 133654.513889                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 133464.173182                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 138687.192118                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.itb.walker 137583.690987                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 135819.070132                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 144289.076824                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 76421.749493                       # average overall miss latency
+system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.250000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.215728                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.206825                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.184965                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data     0.176179                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.198074                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006405                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004024                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.005814                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.006128                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005924                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.040642                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.033278                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.035623                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.040807                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.038912                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.580204                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.164962                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu2.data     0.175328                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu3.data     0.181383                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.402042                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007560                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.011394                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.006405                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.082837                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.007083                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.007782                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004024                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.073949                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002929                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker     0.007729                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.005814                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.069418                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003549                       # miss rate for demand accesses
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+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007560                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003549                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.029462                       # miss rate for overall accesses
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+system.l2c.ReadReq_avg_miss_latency::total 81476.375995                       # average ReadReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 41412.047366                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 42612.456196                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 24857.632575                       # average UpgradeReq miss latency
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+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133749.867620                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 136053.066212                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 82975.254946                       # average ReadCleanReq miss latency
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+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130586.978719                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 139175.386967                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 155662.198631                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total 28279.203651                       # average InvalidateReq miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.inst 131892.820210                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.inst 131892.820210                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 131875.995486                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 135605.321508                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker 136805.434783                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 133749.867620                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 132955.408458                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu3.itb.walker 135691.477886                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 136053.066212                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 144712.943464                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 77929.582558                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2804,11 +2795,11 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              947584                       # number of writebacks
-system.l2c.writebacks::total                   947584                       # number of writebacks
+system.l2c.writebacks::writebacks              950197                       # number of writebacks
+system.l2c.writebacks::total                   950197                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            2                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           11                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                13                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           14                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                16                       # number of ReadReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadSharedReq_mshr_hits::cpu2.data            4                       # number of ReadSharedReq MSHR hits
@@ -2816,326 +2807,326 @@ system.l2c.ReadSharedReq_mshr_hits::cpu3.data            1
 system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
 system.l2c.demand_mshr_hits::cpu2.data              4                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.dtb.walker            2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.itb.walker           11                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.itb.walker           14                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 22                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu2.data             4                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.dtb.walker            2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.itb.walker           11                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.itb.walker           14                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          366                       # number of ReadReq MSHR misses
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-system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1013                       # number of ReadReq MSHR misses
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-system.l2c.ReadReq_mshr_misses::total            3352                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4480                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data         5760                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data         9480                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        19720                       # number of UpgradeReq MSHR misses
+system.l2c.overall_mshr_hits::total                22                       # number of overall MSHR hits
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+system.l2c.UpgradeReq_mshr_misses::cpu2.data         5827                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data         9417                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        19785                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        45205                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        62745                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data        97688                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        205638                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         7162                       # number of ReadCleanReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_miss_latency::total        72000                       # number of SCUpgradeReq MSHR miss cycles
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-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.171783                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.176055                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.176822                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.076906                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.006415                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.007617                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004247                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.068006                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002571                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.005986                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005859                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.071744                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003536                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.008416                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005808                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.070251                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.016353                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.006415                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.007617                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004247                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.068006                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002571                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.005986                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005859                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.071744                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003536                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.008416                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005808                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.070251                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.016353                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 127917.362768                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70682.366071                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70768.055556                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70756.856540                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70743.204868                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   6190886500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   7284997500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data  13845865500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  27321749500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    825092500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   2804419500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   3533391999                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   7162903999                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   3312638000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   4909113000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data  10398990500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  18620741500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2243882500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   3379874000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   7340646500                       # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total  12964403000                       # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     50859000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     42041500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    825092500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   9503524500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     56648000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     58330500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst   2804419500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data  12194110500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker    130896000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.itb.walker    115049500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst   3533391999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data  24244856000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  53559219499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     50859000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     42041500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    825092500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   9503524500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     56648000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     58330500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst   2804419500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data  12194110500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker    130896000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.itb.walker    115049500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst   3533391999                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data  24244856000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  53559219499                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1277858000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1278109500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1223125500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3779093000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1236963000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1237416500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1206551998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   3680931498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2514821000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2515526000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2429677498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   7460024498                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.007083                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.007782                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002929                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.007729                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003542                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.008248                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.003649                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.770968                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.796147                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.780846                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.461103                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.206825                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.184965                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.176179                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.107463                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.004024                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.005814                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.006128                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003650                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.033278                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.035619                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.040807                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.022503                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.164962                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.175328                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.181383                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.077752                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.007083                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.007782                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004024                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.073949                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002929                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.007729                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005814                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.069415                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003542                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.008248                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.006128                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.071685                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.016627                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.007083                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.007782                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004024                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.073949                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002929                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.007729                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005814                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.069415                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003542                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.008248                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.006128                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.071685                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.016627                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127466.165414                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128175.304878                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 125605.321508                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 126805.434783                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128203.721841                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 126012.595838                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 127050.531915                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70671.327901                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70766.689549                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70758.097059                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70740.712661                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        72000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        72000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120893.938724                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122452.633676                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 136905.863566                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 128975.972340                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121591.873778                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123654.513889                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 125823.742727                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124418.169352                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122981.007553                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 125103.017341                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131054.734458                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127945.486183                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120472.951639                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 128899.178590                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 145632.611554                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 135853.629765                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121591.873778                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121679.307110                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123654.513889                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123465.481419                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 125823.742727                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134289.236907                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 127978.300496                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121591.873778                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121679.307110                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123654.513889                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123465.481419                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 125823.742727                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134289.236907                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 127978.300496                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185061.255855                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 184535.262856                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 178655.153125                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 182699.259967                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191813.877875                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191010.983103                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 183657.028114                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 188702.921646                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 188302.123773                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 187664.489311                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 181105.058362                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 185607.618412                       # average overall mshr uncacheable latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121128.673449                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 121820.663534                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137233.162856                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 128995.436819                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121892.820210                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123749.867620                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126057.509775                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124656.793286                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123297.651394                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124682.218779                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131497.964113                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 128135.241982                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120586.978719                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 129175.386967                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 145662.198631                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 136226.494200                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127466.165414                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128175.304878                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121892.820210                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121875.995486                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 125605.321508                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 126805.434783                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123749.867620                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 122956.727570                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128203.721841                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 126012.595838                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126057.509775                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134713.103004                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 128083.689656                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127466.165414                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128175.304878                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121892.820210                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121875.995486                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 125605.321508                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 126805.434783                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123749.867620                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 122956.727570                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128203.721841                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 126012.595838                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126057.509775                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134713.103004                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 128083.689656                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184262.148522                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 184938.431486                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 180801.995565                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 183353.209451                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191598.977695                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191313.620903                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 185623.384308                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189504.298703                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 187799.342842                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 188020.479856                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 183164.530569                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 186337.567079                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               76702                       # Transaction distribution
-system.membus.trans_dist::ReadResp             438040                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33616                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33616                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1054215                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           195061                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            34374                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76742                       # Transaction distribution
+system.membus.trans_dist::ReadResp             436146                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33651                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33651                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1056828                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           193864                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            34231                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           34376                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            877287                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           877287                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        361338                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           34233                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            881810                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           881810                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        359404                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122464                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122584                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           61                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6736                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3755613                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3884874                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342734                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       342734                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4227608                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155640                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6766                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3762035                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3891446                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342687                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342687                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4234133                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155714                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13472                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    139526112                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    139695420                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7304128                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7304128                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               146999548                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1634                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2741682                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13532                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    139863648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    140033090                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7303808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7303808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               147336898                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1567                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2745655                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2741682    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2745655    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2741682                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            69473500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2745655                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            68555500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1838002                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1764002                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          2993221129                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          3043978655                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2766254947                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2811928746                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          111131085                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          111188737                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3189,61 +3180,61 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     51354926                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     26009056                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         2855                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2048                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2048                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     51453109                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     26058247                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         3008                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2315                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2315                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            1478127                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          23632068                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33616                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33616                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      7917832                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     15694537                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2278182                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           42970                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          42972                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1968733                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1968733                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      15697459                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      6461865                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1271562                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1223538                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47175640                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29164933                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       814493                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1705007                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              78860073                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2009256084                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1017810408                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2934600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6010000                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3036011092                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1652274                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         37979201                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.016509                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.127422                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            1484473                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          23684852                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33651                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33651                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      7933708                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     15738935                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2275989                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           42908                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             5                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          42913                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1970952                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1970952                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      15741997                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      6463623                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1272073                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1223993                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47309096                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29178438                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       818931                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1715075                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              79021540                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2014946836                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1018609902                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2956128                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6054072                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             3042566938                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1651979                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         38031624                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.016505                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.127406                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               37352210     98.35%     98.35% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 626991      1.65%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               37403925     98.35%     98.35% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 627699      1.65%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           37979201                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        30549015491                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           38031624                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        30654168986                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           656694                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           845171                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       15157992691                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       15236717928                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        7808308250                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        7805405781                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         290510210                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         292394209                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         695723441                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         700943896                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal
index 0be82d384..b17305731 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal
@@ -103,33 +103,33 @@
 [    3.136511] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]

 [    3.136524] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]

 [    3.136537] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]

-[    3.136598] pci_bus 0000:00: fixups for bus

+[    3.136597] pci_bus 0000:00: fixups for bus

 [    3.136607] pci_bus 0000:00: bus scan returning with max=00

 [    3.136622] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc

 [    3.136649] pci 0000:00:00.0: fixup irq: got 33

 [    3.136659] pci 0000:00:00.0: assigning IRQ 33

-[    3.136673] pci 0000:00:01.0: fixup irq: got 34

-[    3.136683] pci 0000:00:01.0: assigning IRQ 34

+[    3.136672] pci 0000:00:01.0: fixup irq: got 34

+[    3.136682] pci 0000:00:01.0: assigning IRQ 34

 [    3.136697] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

 [    3.136712] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]

 [    3.136726] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

 [    3.136739] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

 [    3.136751] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]

-[    3.136764] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]

-[    3.136776] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

-[    3.136788] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

+[    3.136763] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]

+[    3.136775] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

+[    3.136787] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

 [    3.137187] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

 [    3.137353] ata_piix 0000:00:01.0: version 2.13

 [    3.137355] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

 [    3.137360] ata_piix 0000:00:01.0: enabling bus mastering

 [    3.137757] scsi0 : ata_piix

 [    3.137894] scsi1 : ata_piix

-[    3.137933] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

+[    3.137932] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

 [    3.137945] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

 [    3.138020] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

-[    3.138032] e1000: Copyright (c) 1999-2006 Intel Corporation.

+[    3.138031] e1000: Copyright (c) 1999-2006 Intel Corporation.

 [    3.138045] e1000 0000:00:00.0: enabling device (0000 -> 0002)

-[    3.138056] e1000 0000:00:00.0: enabling bus mastering

+[    3.138055] e1000 0000:00:00.0: enabling bus mastering

 [    3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66

 [    3.290901] ata1.00: 2096640 sectors, multi 0: LBA 

 [    3.290907] ata1.00: configured for UDMA/33

@@ -158,9 +158,9 @@
 [    3.411950] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)

 
 
-[    3.450205] udevd[607]: starting version 182

+[    3.450204] udevd[607]: starting version 182

 Starting Bootlog daemon: bootlogd.


-[    3.533179] random: dd urandom read with 19 bits of entropy available

+[    3.543300] random: dd urandom read with 19 bits of entropy available

 Populating dev cache


 net.ipv4.conf.default.rp_filter = 1


 net.ipv4.conf.all.rp_filter = 1


@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory


 
INIT: Entering runlevel: 5



 Configuring network interfaces... udhcpc (v1.21.1) started


-[    3.671115] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

+[    3.681115] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

 Sending discover...


 Sending discover...


 Sending discover...


diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
index c81d738a9..d0e4571d0 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -1261,10 +1261,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -1291,7 +1290,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -1455,12 +1454,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -1553,16 +1549,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1578,7 +1573,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1741,13 +1736,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1757,9 +1752,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1801,7 +1795,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1882,14 +1876,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1906,7 +1899,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1921,7 +1914,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -2044,17 +2037,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -2106,7 +2101,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -2121,7 +2116,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr
index bc7e2966b..e3ddf9c3f 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr
@@ -461,3 +461,83 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout
index 925f82879..f47c1d8a7 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 20:08:05
-gem5 executing on e104799-lin, pid 28085
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 14:20:09
+gem5 executing on e104799-lin, pid 15456
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
index cb7276071..a910c6b4e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
@@ -1,162 +1,162 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.329060                       # Number of seconds simulated
-sim_ticks                                51329059921000                       # Number of ticks simulated
-final_tick                               51329059921000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.289328                       # Number of seconds simulated
+sim_ticks                                51289327844000                       # Number of ticks simulated
+final_tick                               51289327844000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 136441                       # Simulator instruction rate (inst/s)
-host_op_rate                                   160331                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7875321628                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 694032                       # Number of bytes of host memory used
-host_seconds                                  6517.71                       # Real time elapsed on the host
-sim_insts                                   889279572                       # Number of instructions simulated
-sim_ops                                    1044993075                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 135228                       # Simulator instruction rate (inst/s)
+host_op_rate                                   158909                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7809061274                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 694320                       # Number of bytes of host memory used
+host_seconds                                  6567.93                       # Real time elapsed on the host
+sim_insts                                   888164103                       # Number of instructions simulated
+sim_ops                                    1043699308                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker       138560                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       132032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3631936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         41395808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       145856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       130368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3527872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         42283560                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        424576                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             91810568                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3631936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3527872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7159808                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     78035520                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker       136512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker       126720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          3641344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         41468960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       150528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker       137472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          3597568                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         42676392                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        428864                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             92364360                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      3641344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      3597568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         7238912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     78441216                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          78056100                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2165                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2063                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             56749                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            646818                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2279                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2037                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             55123                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            660685                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6634                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1434553                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1219305                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          78461796                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         2133                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1980                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             56896                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            647961                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker         2352                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         2148                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             56212                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            666823                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6701                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1443206                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1225644                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1221878                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2699                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2572                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               70758                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              806479                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2842                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2540                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               68731                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              823774                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8272                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1788666                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          70758                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          68731                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             139488                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1520299                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total              1228217                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          2662                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          2471                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               70996                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              808530                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          2935                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          2680                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               70143                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              832072                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             8362                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1800849                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          70996                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          70143                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             141139                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1529387                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1520700                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1520299                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2699                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2572                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              70758                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             806479                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2842                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2540                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              68731                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             824175                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8272                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3309366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1434553                       # Number of read requests accepted
-system.physmem.writeReqs                      1221878                       # Number of write requests accepted
-system.physmem.readBursts                     1434553                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1221878                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 91768384                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     43008                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  78056128                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  91810568                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               78056100                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      672                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1529788                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1529387                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         2662                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         2471                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              70996                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             808530                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         2935                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         2680                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              70143                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             832473                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            8362                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3330637                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1443206                       # Number of read requests accepted
+system.physmem.writeReqs                      1228217                       # Number of write requests accepted
+system.physmem.readBursts                     1443206                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1228217                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 92312576                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     52608                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  78461696                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  92364360                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               78461796                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      822                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         354445                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               86303                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               88556                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               87585                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               86132                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               85519                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               93403                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               87506                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               86099                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               84644                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              113970                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              93714                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              93674                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              83678                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              89960                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              85105                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              88033                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               73419                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               74799                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               75041                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               76138                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               74959                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               79592                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               75110                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               75651                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               74129                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               81022                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              78327                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              79368                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              72597                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              77989                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              74762                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              76724                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         356478                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               87850                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               89651                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               87083                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               86997                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               87338                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               97616                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               89147                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               87735                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               84823                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              114942                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              92351                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              95964                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              83458                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              87171                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              84360                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              85898                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               74977                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               75819                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               74752                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               76261                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               75660                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               82258                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               76272                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               77177                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               74263                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               81618                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              78101                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              81113                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              72977                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              75983                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              73541                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              75192                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51329058678000                       # Total gap between requests
+system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51289326709500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1434538                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1443191                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
 system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1219305                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    657679                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    396498                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    215329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    158489                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       891                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       626                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       551                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1107                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       765                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       399                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      390                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1225644                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    662564                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    398514                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    216343                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    159104                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       873                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       598                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       577                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       787                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       375                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      385                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                      191                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      190                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      136                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      134                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      133                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      125                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                      121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      104                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       93                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      103                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                       81                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       63                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -165,185 +165,180 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean      302.697381                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.440606                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     331.820574                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         224613     40.04%     40.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       128067     22.83%     62.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        54948      9.79%     72.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        26347      4.70%     77.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        23416      4.17%     81.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12898      2.30%     83.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        13342      2.38%     86.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         8863      1.58%     87.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        68542     12.22%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         561036                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         69852                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        20.526986                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      231.209031                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          69847     99.99%     99.99% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::total         565463                       # Bytes accessed per row activation
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 system.physmem.rdPerTurnAround::2048-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-6143            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::59392-61439            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           69852                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         69852                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.460159                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.920258                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.852761                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                44      0.06%      0.06% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::8-11               11      0.02%      0.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              61      0.09%      0.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           65855     94.28%     94.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            1487      2.13%     96.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             231      0.33%     96.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             500      0.72%     97.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              71      0.10%     97.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             334      0.48%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             206      0.29%     98.53% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::48-51              69      0.10%     98.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             137      0.20%     98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              25      0.04%     98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              32      0.05%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             488      0.70%     99.66% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::samples         70251                       # Writes before turning the bus around for reads
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 system.physmem.wrPerTurnAround::68-71              32      0.05%     99.70% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::76-79             111      0.16%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
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 system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::128-131            24      0.03%     99.98% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::164-167             3      0.00%    100.00% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total           69852                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    41803653811                       # Total ticks spent queuing
-system.physmem.totMemAccLat               68688922561                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   7169405000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       29154.20                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::total           70251                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    41993928125                       # Total ticks spent queuing
+system.physmem.totMemAccLat               69038628125                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   7211920000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       29114.25                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  47904.20                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.79                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.79                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47864.25                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.80                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.53                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.80                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.53                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.29                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.57                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1177173                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    915297                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.05                       # Row buffer hit rate for writes
-system.physmem.avgGap                     19322564.25                       # Average gap between requests
-system.physmem.pageHitRate                      78.86                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2106662040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1149468375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                5468603400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3918514320                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3352564322640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1237967178795                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29711496726750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34314671476320                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.523347                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49427496871292                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713989940000                       # Time in different power states
+system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        10.56                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1183273                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    919611                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.04                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.01                       # Row buffer hit rate for writes
+system.physmem.avgGap                     19199253.25                       # Average gap between requests
+system.physmem.pageHitRate                      78.81                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 2152490760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 1174474125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                5564652600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3973380480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3349969140960                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1239658923690                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29686172799750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34288665862365                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.534207                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49385348498815                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1712663160000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    187567949958                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    191309868685                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2134770120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1164805125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                5715621600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3984668640                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3352564322640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1240798843035                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29709012810750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34315375841910                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.537070                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49423322508450                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713989940000                       # Time in different power states
+system.physmem_1.actEnergy                 2122409520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 1158060750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                5685895800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3970866240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3349969140960                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1241047287225                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29684954937000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34288908597495                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.538939                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49383290725827                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1712663160000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    191746853550                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    193373338673                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst         1088                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -373,15 +368,15 @@ system.cf0.dma_read_txs                           122                       # Nu
 system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              128171553                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         86901839                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5585684                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            86828453                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               62767092                       # Number of BTB hits
+system.cpu0.branchPred.lookups              128583219                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         87130706                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect          5608498                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups            87627947                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits               62974583                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            72.288622                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               16853141                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            186956                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            71.865866                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS               16935709                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect            187300                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -412,89 +407,87 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   885239                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               885239                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16068                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        88252                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       546727                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       338512                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2698.944203                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 16449.109677                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       335800     99.20%     99.20% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1393      0.41%     99.61% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          884      0.26%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          153      0.05%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679          156      0.05%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           36      0.01%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751           43      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287           32      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823           10      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::589824-655359            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       338512                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       409508                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23024.226633                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18496.792158                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 19848.076678                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       400961     97.91%     97.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         6256      1.53%     99.44% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1568      0.38%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          126      0.03%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679          350      0.09%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215          156      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           68      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       409508                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 369272261460                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.199871                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.721140                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3 368268104460     99.73%     99.73% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7    539578000      0.15%     99.87% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11    201182000      0.05%     99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15    121167500      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19     48555500      0.01%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23     26406000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27     26984000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31     34302000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35      5588500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::36-39       301000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::40-43        52000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::44-47        18000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::48-51        22500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 369272261460                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        88253     84.60%     84.60% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        16068     15.40%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       104321                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       885239                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks                   888652                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               888652                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16421                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        87809                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore       549489                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       339163                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean  2672.191542                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 16085.449478                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535       336454     99.20%     99.20% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071         1394      0.41%     99.61% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607          896      0.26%     99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143          159      0.05%     99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679          148      0.04%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215           38      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751           39      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287           31      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       339163                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       409656                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22857.613461                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18421.045367                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 19320.142266                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       401054     97.90%     97.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071         6459      1.58%     99.48% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1486      0.36%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143           99      0.02%     99.86% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679          354      0.09%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215          127      0.03%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           51      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287           19      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total       409656                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 372489857920                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.125711                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.685370                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-3 371484178920     99.73%     99.73% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-7    543967500      0.15%     99.88% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-11    197972000      0.05%     99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-15    122397500      0.03%     99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-19     45621000      0.01%     99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-23     26772000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-27     27386500      0.01%     99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-31     35231000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::32-35      5712500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::36-39       472000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::40-43        66500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::44-47        35000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::48-51        45500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 372489857920                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        87810     84.25%     84.25% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        16421     15.75%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       104231                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       888652                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       885239                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       104321                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       888652                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       104231                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       104321                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       989560                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       104231                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       992883                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   102290715                       # DTB read hits
-system.cpu0.dtb.read_misses                    610545                       # DTB read misses
-system.cpu0.dtb.write_hits                   79331513                       # DTB write hits
-system.cpu0.dtb.write_misses                   274694                       # DTB write misses
+system.cpu0.dtb.read_hits                   102519767                       # DTB read hits
+system.cpu0.dtb.read_misses                    608916                       # DTB read misses
+system.cpu0.dtb.write_hits                   79730858                       # DTB write hits
+system.cpu0.dtb.write_misses                   279736                       # DTB write misses
 system.cpu0.dtb.flush_tlb                        1105                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              21571                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    526                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   54684                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      193                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9578                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid              21393                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    535                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   55242                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                      209                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                  9412                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    56017                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               102901260                       # DTB read accesses
-system.cpu0.dtb.write_accesses               79606207                       # DTB write accesses
+system.cpu0.dtb.perms_faults                    56039                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses               103128683                       # DTB read accesses
+system.cpu0.dtb.write_accesses               80010594                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        181622228                       # DTB hits
-system.cpu0.dtb.misses                         885239                       # DTB misses
-system.cpu0.dtb.accesses                    182507467                       # DTB accesses
+system.cpu0.dtb.hits                        182250625                       # DTB hits
+system.cpu0.dtb.misses                         888652                       # DTB misses
+system.cpu0.dtb.accesses                    183139277                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -524,830 +517,824 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                   102914                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong               102914                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2949                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69039                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        14347                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        88567                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1898.844942                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 12048.773919                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        87489     98.78%     98.78% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          597      0.67%     99.46% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303           92      0.10%     99.56% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071          110      0.12%     99.68% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839          199      0.22%     99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           35      0.04%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375           18      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        88567                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        86335                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 29628.748480                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24429.301414                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 24451.958978                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        84088     97.40%     97.40% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071          706      0.82%     98.22% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607         1293      1.50%     99.71% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           86      0.10%     99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679          119      0.14%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           18      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                   102152                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong               102152                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3042                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        68901                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore        14128                       # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples        88024                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean  1905.912024                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 12139.697138                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-65535        87548     99.46%     99.46% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-131071          189      0.21%     99.67% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-196607          243      0.28%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-262143           22      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-327679           18      0.02%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        88024                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        86071                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 29335.746070                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24303.412638                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 23702.116672                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        84000     97.59%     97.59% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071          669      0.78%     98.37% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607         1177      1.37%     99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           63      0.07%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679          107      0.12%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           38      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        86335                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 279075367244                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.887042                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -247471426488    -88.68%    -88.68% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   526476465732    188.65%     99.97% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       62141000      0.02%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        6800000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4        1085000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5         302000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 279075367244                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        69039     95.90%     95.90% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2949      4.10%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        71988                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total        86071                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 290883014796                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean     1.826730                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0   -240403892944    -82.65%    -82.65% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1   531218150240    182.62%     99.98% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2       61167000      0.02%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3        6375000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4        1069000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5         146500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 290883014796                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        68901     95.77%     95.77% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         3042      4.23%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        71943                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102914                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102914                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102152                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102152                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        71988                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        71988                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       174902                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    91881601                       # ITB inst hits
-system.cpu0.itb.inst_misses                    102914                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        71943                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        71943                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       174095                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    92233828                       # ITB inst hits
+system.cpu0.itb.inst_misses                    102152                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                        1105                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              21571                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    526                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   40429                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              21393                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    535                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   40730                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   204535                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                   204444                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                91984515                       # ITB inst accesses
-system.cpu0.itb.hits                         91881601                       # DTB hits
-system.cpu0.itb.misses                         102914                       # DTB misses
-system.cpu0.itb.accesses                     91984515                       # DTB accesses
-system.cpu0.numCycles                       691170563                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                92335980                       # ITB inst accesses
+system.cpu0.itb.hits                         92233828                       # DTB hits
+system.cpu0.itb.misses                         102152                       # DTB misses
+system.cpu0.itb.accesses                     92335980                       # DTB accesses
+system.cpu0.numCycles                       692838439                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles         239962884                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     570438077                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  128171553                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          79620233                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    407738854                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               12781952                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2594971                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               25425                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             5359                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles      5458708                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       162648                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles         3329                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 91660544                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              3463851                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  41672                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         662342878                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.009072                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.262587                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles         240908960                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                     572231445                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                  128583219                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches          79910292                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                    408388774                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles               12834591                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                   2570044                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles               24306                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             5220                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles      5457264                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       161454                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles         3138                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                 92012846                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes              3478486                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                  41135                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples         663936181                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             1.010011                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.263466                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               521294405     78.70%     78.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                17644727      2.66%     81.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                17609553      2.66%     84.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                13023217      1.97%     85.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                28132742      4.25%     90.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 8705409      1.31%     91.56% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 9465006      1.43%     92.98% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 8172202      1.23%     94.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                38295617      5.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0               522394328     78.68%     78.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                17725810      2.67%     81.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                17688411      2.66%     84.02% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                13071873      1.97%     85.98% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                28203827      4.25%     90.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                 8736087      1.32%     91.55% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 9493633      1.43%     92.98% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                 8170343      1.23%     94.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                38451869      5.79%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           662342878                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.185441                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.825322                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               194658503                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            347202119                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                101960102                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             13505854                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5013938                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19069784                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              1396202                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             622839427                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4306034                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5013938                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               202133183                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               32047845                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     264605257                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                107868981                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             50671063                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             608332366                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                94298                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               2196276                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1835605                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              31002598                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents            3774                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          582920651                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            941800609                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       719611293                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           780673                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            492512857                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                90407789                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          15406324                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      13476597                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 76098764                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            97666868                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           83390194                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         13497619                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores        14417995                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 576927509                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           15532510                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                579347297                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           823601                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       76188435                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     48806754                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        359672                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    662342878                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.874694                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.613558                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total           663936181                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.185589                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.825923                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles               195480668                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles            347525883                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                102363007                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles             13531611                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               5032846                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved            19144374                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred              1404061                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts             624972262                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts              4324699                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               5032846                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles               202972273                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               31908208                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles     264942356                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                108280793                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles             50797146                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts             610471334                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                95561                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents               2181622                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents               1833281                       # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents              31100121                       # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents            3748                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands          584763041                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            944825531                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       722111361                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           774403                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps            494202829                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                90560207                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts          15441984                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts      13500490                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 76181815                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            97914623                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores           83796282                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads         13494788                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores        14509188                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                 578969956                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded           15549087                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                581387385                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           830768                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined       76282364                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     48796155                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        362907                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples    663936181                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.875668                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.614381                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          433272632     65.42%     65.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           98115954     14.81%     80.23% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           42214584      6.37%     86.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           29957655      4.52%     91.13% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4           22351656      3.37%     94.50% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5           15512359      2.34%     96.84% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6           10588779      1.60%     98.44% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7            6205955      0.94%     99.38% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8            4123304      0.62%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0          434128190     65.39%     65.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           98370789     14.82%     80.20% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2           42377650      6.38%     86.59% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3           30067622      4.53%     91.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4           22403128      3.37%     94.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5           15594972      2.35%     96.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6           10621983      1.60%     98.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7            6235616      0.94%     99.38% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8            4136231      0.62%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      662342878                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total      663936181                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                2935970     25.32%     25.32% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 23101      0.20%     25.52% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                   2125      0.02%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.54% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4825862     41.62%     67.16% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              3807172     32.84%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                2959786     25.50%     25.50% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                 23278      0.20%     25.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                   2380      0.02%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.73% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4810604     41.45%     67.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite              3809012     32.82%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass               11      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            393154923     67.86%     67.86% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1386126      0.24%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                65806      0.01%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                 67      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               1      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         58960      0.01%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           104322059     18.01%     86.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           80359344     13.87%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu            394568235     67.87%     67.87% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult             1380833      0.24%     68.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                65255      0.01%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                 66      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   2      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               1      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc         59226      0.01%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead           104545250     17.98%     86.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite           80768506     13.89%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             579347297                       # Type of FU issued
-system.cpu0.iq.rate                          0.838212                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   11594230                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.020013                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        1832414752                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        668808824                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    557946251                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1040551                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            514226                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       463065                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             590385045                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 556471                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         4593967                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total             581387385                       # Type of FU issued
+system.cpu0.iq.rate                          0.839138                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                   11605060                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.019961                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads        1838113951                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes        670976650                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses    559986003                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads            1032828                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            510697                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       459801                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses             592439966                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 552468                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads         4598569                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     15457682                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        19886                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       685587                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      8559329                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads     15443537                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses        19687                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation       696908                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores      8570730                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      3807037                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      8317580                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      3841968                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked      8263079                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5013938                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               16283569                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles             13949536                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          592593872                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts          1684559                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             97666868                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            83390194                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13181889                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                225552                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents             13639351                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        685587                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2515735                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2200394                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             4716129                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            572987032                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            102282970                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          5487366                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               5032846                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               16244018                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles             13852341                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts          594652790                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts          1703484                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             97914623                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts            83796282                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts          13208370                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                224559                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents             13543277                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents        696908                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect       2523457                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect      2209016                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts             4732473                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts            575002762                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts            102511874                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          5508716                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       133853                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   181615455                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               106143494                       # Number of branches executed
-system.cpu0.iew.exec_stores                  79332485                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.829010                       # Inst execution rate
-system.cpu0.iew.wb_sent                     559590255                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    558409316                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                275573262                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                478603193                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.807918                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.575787                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       76231429                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       15172838                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4208370                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    649315784                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.795101                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.790427                       # Number of insts commited each cycle
+system.cpu0.iew.exec_nop                       133747                       # number of nop insts executed
+system.cpu0.iew.exec_refs                   182243986                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches               106498541                       # Number of branches executed
+system.cpu0.iew.exec_stores                  79732112                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.829923                       # Inst execution rate
+system.cpu0.iew.wb_sent                     561628821                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                    560445804                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                276455484                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                480133798                       # num instructions consuming a value
+system.cpu0.iew.wb_rate                      0.808913                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.575788                       # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts       76323092                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls       15186180                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts          4223774                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples    650882635                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.796206                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.791535                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    458104846     70.55%     70.55% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     95694647     14.74%     85.29% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     32190614      4.96%     90.25% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     14675845      2.26%     92.51% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     10626542      1.64%     94.14% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      6339406      0.98%     95.12% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      5863967      0.90%     96.02% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3778167      0.58%     96.61% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     22041750      3.39%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0    459027992     70.52%     70.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1     95977430     14.75%     85.27% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2     32265262      4.96%     90.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3     14738583      2.26%     92.49% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4     10675615      1.64%     94.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5      6384145      0.98%     95.11% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6      5905756      0.91%     96.02% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7      3807566      0.58%     96.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8     22100286      3.40%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    649315784                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           439229242                       # Number of instructions committed
-system.cpu0.commit.committedOps             516271579                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total    650882635                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts           440797694                       # Number of instructions committed
+system.cpu0.commit.committedOps             518236674                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     157040050                       # Number of memory references committed
-system.cpu0.commit.loads                     82209185                       # Number of loads committed
-system.cpu0.commit.membars                    3679399                       # Number of memory barriers committed
-system.cpu0.commit.branches                  98142600                       # Number of branches committed
-system.cpu0.commit.fp_insts                    444854                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                473776942                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13048594                       # Number of function calls committed.
+system.cpu0.commit.refs                     157696637                       # Number of memory references committed
+system.cpu0.commit.loads                     82471085                       # Number of loads committed
+system.cpu0.commit.membars                    3674667                       # Number of memory barriers committed
+system.cpu0.commit.branches                  98481561                       # Number of branches committed
+system.cpu0.commit.fp_insts                    441323                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                475654398                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls            13113007                       # Number of function calls committed.
 system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       358050943     69.35%     69.35% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1081428      0.21%     69.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           48877      0.01%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        50281      0.01%     69.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.58% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       82209185     15.92%     85.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      74830865     14.49%    100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu       359364507     69.34%     69.34% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult        1076711      0.21%     69.55% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv           48368      0.01%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.56% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc        50451      0.01%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.57% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead       82471085     15.91%     85.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite      75225552     14.52%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        516271579                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             22041750                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1215785177                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1198053925                       # The number of ROB writes
-system.cpu0.timesIdled                        4064231                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       28827685                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 52470002692                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  439229242                       # Number of Instructions Simulated
-system.cpu0.committedOps                    516271579                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.573599                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.573599                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.635486                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.635486                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               676011417                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              398349827                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   844800                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  475036                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                123341922                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               124453917                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1200774516                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              15268687                       # number of misc regfile writes
-system.cpu0.dcache.tags.replacements         10441215                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.972989                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          300350847                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10441727                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.764480                       # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total        518236674                       # Class of committed instruction
+system.cpu0.commit.bw_lim_events             22100286                       # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads                  1219379931                       # The number of ROB reads
+system.cpu0.rob.rob_writes                 1202193257                       # The number of ROB writes
+system.cpu0.timesIdled                        4085117                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       28902258                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                 52406782764                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                  440797694                       # Number of Instructions Simulated
+system.cpu0.committedOps                    518236674                       # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi                              1.571783                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        1.571783                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.636220                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.636220                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               678374188                       # number of integer regfile reads
+system.cpu0.int_regfile_writes              399817042                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   838109                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  474946                       # number of floating regfile writes
+system.cpu0.cc_regfile_reads                123617139                       # number of cc regfile reads
+system.cpu0.cc_regfile_writes               124729221                       # number of cc regfile writes
+system.cpu0.misc_regfile_reads             1203854145                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes              15290594                       # number of misc regfile writes
+system.cpu0.dcache.tags.replacements         10436084                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.972968                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs          299959666                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs         10436596                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            28.741140                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       2716190500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   278.618843                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   233.354146                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.544177                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.455770                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   279.244386                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   232.728582                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.545399                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.454548                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          171                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          323                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1324703631                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1324703631                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     77691173                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     80692342                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      158383515                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     65479208                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     68217846                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     133697054                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       204861                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       196710                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       401571                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       173286                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       151828                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       325114                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1754825                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1726209                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3481034                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2015188                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1998716                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4013904                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    143170381                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    148910188                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       292080569                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    143375242                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    149106898                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      292482140                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6274582                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      6195801                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total     12470383                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      6551010                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      6079210                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total     12630220                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       672252                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       604348                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1276600                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       607594                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       629524                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1237118                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       316888                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       332062                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       648950                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            6                       # number of StoreCondReq misses
+system.cpu0.dcache.tags.tag_accesses       1323106613                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1323106613                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     77963580                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     80269235                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total      158232815                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     65859782                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data     67602913                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total     133462695                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       205959                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       194953                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       400912                       # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       173450                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data       151834                       # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total       325284                       # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1750606                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1727963                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total      3478569                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2015132                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1995479                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total      4010611                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data    143823362                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data    147872148                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total       291695510                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data    144029321                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data    148067101                       # number of overall hits
+system.cpu0.dcache.overall_hits::total      292096422                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      6244351                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data      6201364                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total     12445715                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      6561247                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      6087286                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total     12648533                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       674350                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data       604184                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total      1278534                       # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       611409                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data       625543                       # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total      1236952                       # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       321165                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       325705                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total       646870                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data            7                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            5                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     12825592                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data     12275011                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      25100603                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     13497844                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data     12879359                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     26377203                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110046320000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111087741500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 221134061500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 282950530887                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 268653294230                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 551603825117                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  43457890636                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  47921476510                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  91379367146                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4290157000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4634510500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   8924667500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       150500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       207500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       358000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 392996850887                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 379741035730                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 772737886617                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 392996850887                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 379741035730                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 772737886617                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     83965755                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     86888143                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    170853898                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     72030218                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     74297056                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    146327274                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       877113                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       801058                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1678171                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       780880                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       781352                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1562232                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2071713                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2058271                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4129984                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2015194                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1998721                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4013915                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    155995973                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    161185199                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    317181172                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    156873086                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    161986257                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    318859343                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074728                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.071308                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.072989                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.090948                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.081823                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.086315                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766437                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.754437                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760709                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.778089                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.805686                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.791891                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.152959                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.161331                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.157131                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data     12805598                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data     12288650                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total      25094248                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data     13479948                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data     12892834                       # number of overall misses
+system.cpu0.dcache.overall_misses::total     26372782                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 109268778000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 112129743000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 221398521000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 284664585056                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 269956494563                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 554621079619                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  43595846266                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  47989893688                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total  91585739954                       # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4328541000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4603645500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total   8932186500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       235000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       208500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       443500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 393933363056                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 382086237563                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 776019600619                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 393933363056                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 382086237563                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 776019600619                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     84207931                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     86470599                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total    170678530                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     72421029                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data     73690199                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total    146111228                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       880309                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       799137                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total      1679446                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       784859                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       777377                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total      1562236                       # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2071771                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2053668                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total      4125439                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2015139                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1995484                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total      4010623                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data    156628960                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data    160160798                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total    316789758                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data    157509269                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data    160959935                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total    318469204                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074154                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.071716                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.072919                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.090599                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.082606                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.086568                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766038                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.756046                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.761283                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.779005                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.804684                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.791783                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.155020                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.158597                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.156800                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.082217                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.076155                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.079136                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086043                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.079509                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.082724                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17538.430448                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17929.520574                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17732.740165                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.894210                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44192.139148                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43673.334678                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 71524.555272                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 76123.351151                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 73864.713912                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13538.401580                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13956.762593                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13752.473226                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25083.333333                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        41500                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32545.454545                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30641.614897                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30936.105534                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 30785.630394                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29115.527701                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29484.467024                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 29295.671972                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     87920844                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       114851                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          3496537                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           1061                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    25.145120                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   108.247879                       # average number of cycles each access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081758                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.076727                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.079214                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085582                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.080100                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.082811                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17498.820614                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18081.464497                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17789.136341                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43385.744365                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44347.595063                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 43848.648663                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 71303.900116                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 76717.178017                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 74041.466406                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13477.623651                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14134.402297                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13808.317745                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 33571.428571                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        41700                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 36958.333333                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30762.590162                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31092.612904                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 30924.202256                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29223.655986                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29635.550847                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 29425.018590                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs     88195384                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       113546                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs          3493866                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets           1091                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    25.242921                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   104.075160                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      8016148                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8016148                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3459904                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3385993                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      6845897                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5454136                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5045051                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total     10499187                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3486                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3453                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         6939                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       195002                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       204372                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       399374                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      8914040                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      8431044                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     17345084                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      8914040                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      8431044                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     17345084                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2814678                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2809808                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5624486                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1096874                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1034159                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2131033                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       658655                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       593550                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1252205                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       604108                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       626071                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1230179                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       121886                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       127690                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       249576                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            6                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      8003169                       # number of writebacks
+system.cpu0.dcache.writebacks::total          8003169                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3436866                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3393684                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total      6830550                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5461090                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5053042                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total     10514132                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3543                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3329                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total         6872                       # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       197755                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       200626                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total       398381                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      8897956                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      8446726                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total     17344682                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      8897956                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      8446726                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total     17344682                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2807485                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2807680                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      5615165                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1100157                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1034244                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      2134401                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       660963                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       593397                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1254360                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       607866                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       622214                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1230080                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       123410                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       125079                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       248489                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            7                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            5                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3911552                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3843967                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      7755519                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      4570207                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4437517                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      9007724                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15990                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17689                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33679                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        14658                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        19039                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30648                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        36728                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67376                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48435084000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  49650597000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  98085681000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  50577189739                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  47912432297                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  98489622036                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13555749500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11111774000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  24667523500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  42652248636                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  47094090510                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  89746339146                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1696955500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1893897000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3590852500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       144500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       202500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       347000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99012273739                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  97563029297                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 196575303036                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112568023239                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 108674803297                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 221242826536                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2881077500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3350690000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6231767500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2752373000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3455424991                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6207797991                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5633450500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6806114991                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12439565491                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033522                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032338                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032920                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015228                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013919                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014563                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750935                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.740958                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746172                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.773625                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.801266                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787450                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058833                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062038                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060430                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3907642                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3841924                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      7749566                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      4568605                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      4435321                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      9003926                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16017                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17661                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        14689                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        19007                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30706                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        36668                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48229998000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  49964907000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  98194905000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  50851143254                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  48166542964                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  99017686218                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13581281500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11177477000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  24758758500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  42782526766                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  47168374188                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  89950900954                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1714638000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1879552500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3594190500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       228000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       203500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       431500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99081141254                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  98131449964                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 197212591218                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112662422754                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 109308926964                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 221971349718                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2884316000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3346437000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6230753000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2757806500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3449966491                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6207772991                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5642122500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6796403491                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12438525991                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033340                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032470                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032899                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015191                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014035                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014608                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750831                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.742547                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746889                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.774491                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.800402                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787384                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059567                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060905                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060233                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025075                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023848                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.024451                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029133                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027394                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028250                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17208.037296                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17670.458978                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17439.047941                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46110.300489                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46329.850919                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46216.845087                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20580.955887                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18720.872715                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19699.269289                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 70603.681189                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 75221.645005                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 72953.886504                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13922.480843                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14831.991542                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14387.811729                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24083.333333                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        40500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 31545.454545                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25312.784731                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25380.818643                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25346.505248                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24630.836905                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24490.002697                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24561.457093                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180179.956223                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189422.239810                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185034.220137                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187772.752081                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181491.937129                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184224.055287                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183811.358001                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185311.342600                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184629.029491                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024948                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023988                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.024463                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029005                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027555                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028273                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17179.075935                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17795.798310                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17487.447831                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46221.714950                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46571.740290                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46391.323007                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20547.718254                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18836.423170                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19738.160098                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 70381.509685                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 75807.317399                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73126.057617                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13893.833563                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15026.922985                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14464.183525                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 32571.428571                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        40700                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35958.333333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25355.736594                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25542.267355                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25448.211063                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24660.136465                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24645.099411                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24652.729234                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180078.416682                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189481.739426                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185009.590831                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187746.374838                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181510.311517                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184228.780597                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183746.580473                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185349.718856                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184619.081411                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         16004570                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.921303                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          169009090                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         16005082                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.559714                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements         15974128                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.921242                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          168806839                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         15974640                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.567176                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      23708267500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   282.699542                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   229.221761                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.552148                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.447699                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   281.088545                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   230.832697                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.549001                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.450845                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999846                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          323                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
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+system.cpu0.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        202254376                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       202254376                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     83086352                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     85922738                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      169009090                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     83086352                       # number of demand (read+write) hits
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-system.cpu0.icache.demand_hits::total       169009090                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     83086352                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     85922738                       # number of overall hits
-system.cpu0.icache.overall_hits::total      169009090                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      8561048                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      8679036                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     17240084                       # number of ReadReq misses
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-system.cpu0.icache.demand_misses::total      17240084                       # number of demand (read+write) misses
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-system.cpu0.icache.overall_misses::total     17240084                       # number of overall misses
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-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 117350183832                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 232568712196                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 115218528364                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 117350183832                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 232568712196                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 115218528364                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 117350183832                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 232568712196                       # number of overall miss cycles
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-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.093413                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.091743                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.092565                       # miss rate for ReadReq accesses
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-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.091743                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.092565                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13458.460736                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13521.108085                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.998784                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13458.460736                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13521.108085                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13489.998784                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13458.460736                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13521.108085                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13489.998784                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs       127898                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        201986364                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       201986364                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     83405429                       # number of ReadReq hits
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+system.cpu0.icache.ReadReq_avg_miss_latency::total 13502.043573                       # average ReadReq miss latency
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+system.cpu0.icache.overall_avg_miss_latency::total 13502.043573                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs       130388                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             8453                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs             8896                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.130486                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.656924                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks     16004570                       # number of writebacks
-system.cpu0.icache.writebacks::total         16004570                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       610799                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       624083                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total      1234882                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       610799                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst       624083                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total      1234882                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       610799                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst       624083                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total      1234882                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      7950249                       # number of ReadReq MSHR misses
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-system.cpu0.icache.ReadReq_mshr_misses::total     16005202                       # number of ReadReq MSHR misses
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-system.cpu0.icache.demand_mshr_misses::cpu1.inst      8054953                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     16005202                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      7950249                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      8054953                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     16005202                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks     15974128                       # number of writebacks
+system.cpu0.icache.writebacks::total         15974128                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       611973                       # number of ReadReq MSHR hits
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 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        20646                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        20646                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 101752782407                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103549068385                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 205301850792                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 101752782407                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103549068385                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 205301850792                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 101752782407                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103549068385                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 205301850792                       # number of overall MSHR miss cycles
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+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 102903128872                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 205072103279                       # number of ReadReq MSHR miss cycles
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 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2636383000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636383000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086748                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.085146                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085934                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086748                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.085146                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.085934                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086748                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.085146                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.085934                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12798.691262                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12855.328688                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12827.195233                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12798.691262                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12855.328688                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12827.195233                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12798.691262                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12855.328688                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12827.195233                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086764                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.085016                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085880                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086764                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.085016                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.085880                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086764                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.085016                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.085880                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12799.442167                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12875.011323                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12837.250799                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12799.442167                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12875.011323                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12837.250799                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12799.442167                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12875.011323                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12837.250799                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969                       # average ReadReq mshr uncacheable latency
@@ -1355,15 +1342,15 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups              131672686                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         89355343                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5781214                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            89724326                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               64173033                       # Number of BTB hits
+system.cpu1.branchPred.lookups              130968102                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted         88970124                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect          5750252                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups            89023495                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits               63858591                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            71.522446                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17121716                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            186515                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            71.732289                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS               16978119                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect            186369                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1393,94 +1380,94 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   890074                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               890074                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        16464                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        90676                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       549449                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       340625                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2662.717064                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 16656.719504                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       337983     99.22%     99.22% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1343      0.39%     99.62% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          873      0.26%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143          159      0.05%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679          157      0.05%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215           32      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751           28      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287           31      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::720896-786431            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::786432-851967            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::851968-917503            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::917504-983039            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::983040-1.04858e+06            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       340625                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       415755                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23534.974925                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 18938.344998                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 20176.522890                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       406038     97.66%     97.66% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         7288      1.75%     99.42% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1678      0.40%     99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          118      0.03%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          407      0.10%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215          121      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           66      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       415755                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 351694007776                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.068501                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.668276                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3 350661865276     99.71%     99.71% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7    565026500      0.16%     99.87% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11    204421500      0.06%     99.93% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15    121176000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19     47649500      0.01%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23     25922000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27     25482500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31     35190500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35      6889500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::36-39       280500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::40-43        36000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::44-47        45500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::48-51        22500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 351694007776                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        90676     84.63%     84.63% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        16464     15.37%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       107140                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       890074                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks                   886500                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               886500                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        16614                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        90854                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore       546971                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       339529                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean  2635.682077                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 15582.194898                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-32767       331369     97.60%     97.60% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-65535         5485      1.62%     99.21% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-98303          837      0.25%     99.46% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::98304-131071          574      0.17%     99.63% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-163839          696      0.20%     99.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::163840-196607          183      0.05%     99.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-229375           92      0.03%     99.91% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::229376-262143           51      0.02%     99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-294911          111      0.03%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::294912-327679           44      0.01%     99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-360447           21      0.01%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::360448-393215            9      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-425983            6      0.00%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::425984-458751           19      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-491519           24      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::491520-524287            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       339529                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       415382                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23662.319263                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 19025.805885                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 20147.084285                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       405553     97.63%     97.63% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071         7307      1.76%     99.39% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1720      0.41%     99.81% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143          155      0.04%     99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679          425      0.10%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215          150      0.04%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           57      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287           14      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       415382                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 346321236644                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     0.073903                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev     0.674380                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3 345291497644     99.70%     99.70% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7    564895000      0.16%     99.87% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11    201129000      0.06%     99.92% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15    122101500      0.04%     99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19     48136500      0.01%     99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23     26097000      0.01%     99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27     27118000      0.01%     99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31     32649000      0.01%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35      7117000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::36-39       414500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::40-43        28000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::44-47        21500      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::48-51        30000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::52-55         2000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 346321236644                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        90854     84.54%     84.54% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        16614     15.46%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       107468                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       886500                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       890074                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       107140                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       886500                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       107468                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       107140                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       997214                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       107468                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       993968                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   104588302                       # DTB read hits
-system.cpu1.dtb.read_misses                    610979                       # DTB read misses
-system.cpu1.dtb.write_hits                   81672452                       # DTB write hits
-system.cpu1.dtb.write_misses                   279095                       # DTB write misses
+system.cpu1.dtb.read_hits                   104053210                       # DTB read hits
+system.cpu1.dtb.read_misses                    608792                       # DTB read misses
+system.cpu1.dtb.write_hits                   81022913                       # DTB write hits
+system.cpu1.dtb.write_misses                   277708                       # DTB write misses
 system.cpu1.dtb.flush_tlb                        1101                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              20830                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    531                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   55425                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      192                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  9142                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid              21005                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    522                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   55258                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                      175                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                  8900                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    57336                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               105199281                       # DTB read accesses
-system.cpu1.dtb.write_accesses               81951547                       # DTB write accesses
+system.cpu1.dtb.perms_faults                    55921                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses               104662002                       # DTB read accesses
+system.cpu1.dtb.write_accesses               81300621                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        186260754                       # DTB hits
-system.cpu1.dtb.misses                         890074                       # DTB misses
-system.cpu1.dtb.accesses                    187150828                       # DTB accesses
+system.cpu1.dtb.hits                        185076123                       # DTB hits
+system.cpu1.dtb.misses                         886500                       # DTB misses
+system.cpu1.dtb.accesses                    185962623                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1510,390 +1497,398 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                   107237                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong               107237                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3106                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        74018                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        14783                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        92454                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1914.233024                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 12442.896364                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        91334     98.79%     98.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          604      0.65%     99.44% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303           90      0.10%     99.54% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071          135      0.15%     99.69% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839          192      0.21%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607           45      0.05%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375           20      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911           11      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::360448-393215            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-425983            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        92454                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        91907                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 29826.585570                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 25014.091101                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 23207.372292                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        89740     97.64%     97.64% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071          728      0.79%     98.43% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607         1203      1.31%     99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           89      0.10%     99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679          102      0.11%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           19      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           20      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        91907                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 308743335316                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     1.811344                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0   -250411422516    -81.11%    -81.11% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   559080989832    181.08%     99.98% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       64275500      0.02%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        7864000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4        1253500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5         141000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::6         234000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 308743335316                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        74018     95.97%     95.97% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         3106      4.03%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        77124                       # Table walker page sizes translated
+system.cpu1.itb.walker.walks                   108383                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong               108383                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3055                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        74203                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore        15086                       # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples        93297                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean  1942.152481                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 12371.477981                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767        92174     98.80%     98.80% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535          584      0.63%     99.42% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303          102      0.11%     99.53% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071          130      0.14%     99.67% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839          211      0.23%     99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607           45      0.05%     99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375           16      0.02%     99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::229376-262143           14      0.02%     99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447            6      0.01%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        93297                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        92344                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 29998.852118                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25024.825336                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 23447.205445                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767        47315     51.24%     51.24% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535        42742     46.29%     97.52% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303          660      0.71%     98.24% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071           85      0.09%     98.33% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839          956      1.04%     99.37% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607          338      0.37%     99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375           49      0.05%     99.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143           41      0.04%     99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911           83      0.09%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679           32      0.03%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447           14      0.02%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215           20      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        92344                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 303371540184                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean     1.809423                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0   -245466797852    -80.91%    -80.91% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1   548762837036    180.89%     99.98% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2       65136000      0.02%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3        8157000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4        1504000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5         507000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::6         155000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::7          42000      0.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 303371540184                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        74203     96.05%     96.05% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         3055      3.95%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        77258                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       107237                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total       107237                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       108383                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total       108383                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        77124                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        77124                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       184361                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    94835234                       # ITB inst hits
-system.cpu1.itb.inst_misses                    107237                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        77258                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        77258                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       185641                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    94245746                       # ITB inst hits
+system.cpu1.itb.inst_misses                    108383                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                        1101                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              20830                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    531                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   41604                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              21005                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    522                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   41537                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   202082                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                   202136                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                94942471                       # ITB inst accesses
-system.cpu1.itb.hits                         94835234                       # DTB hits
-system.cpu1.itb.misses                         107237                       # DTB misses
-system.cpu1.itb.accesses                     94942471                       # DTB accesses
-system.cpu1.numCycles                       690312922                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                94354129                       # ITB inst accesses
+system.cpu1.itb.hits                         94245746                       # DTB hits
+system.cpu1.itb.misses                         108383                       # DTB misses
+system.cpu1.itb.accesses                     94354129                       # DTB accesses
+system.cpu1.numCycles                       688244310                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles         244529898                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     585856252                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  131672686                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          81294749                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    402345645                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13192141                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2778573                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               21795                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             5943                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles      5312997                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       174263                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         3566                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 94609332                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              3554739                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  42315                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         661768476                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.036278                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.289766                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles         242823548                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                     582789507                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                  130968102                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches          80836710                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                    401946219                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles               13110617                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                   2820679                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles               23345                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             5607                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles      5329468                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       177594                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles         4339                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                 94019463                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes              3524085                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                  43192                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         659685833                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.033819                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.287421                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               517207044     78.16%     78.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                18129888      2.74%     80.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                18375332      2.78%     83.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                13432056      2.03%     85.70% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                27838578      4.21%     89.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 9027951      1.36%     91.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 9770345      1.48%     92.75% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 8415200      1.27%     94.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                39572082      5.98%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               515917584     78.21%     78.21% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                18016869      2.73%     80.94% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                18269669      2.77%     83.71% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                13353344      2.02%     85.73% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                27714525      4.20%     89.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                 8994456      1.36%     91.30% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 9703502      1.47%     92.77% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                 8398741      1.27%     94.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                39317143      5.96%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           661768476                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.190743                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.848682                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               199426637                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            337927065                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                106132516                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             13075533                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5204264                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            19655517                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1411698                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             639761275                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              4339654                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5204264                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               206862514                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               30693400                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     255298873                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                111614723                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             52092053                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             624767105                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents               119693                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               2051470                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               1928200                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              33207471                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            3875                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          596912920                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            957883599                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       738584518                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           769692                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            502441681                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                94471239                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          14502575                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      12526593                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 72768072                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads           100816739                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           85870948                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads         13475308                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores        14310498                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 593385744                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           14541945                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                593302844                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           834025                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       79206193                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     50535241                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        362086                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    661768476                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.896541                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.637280                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           659685833                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.190293                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.846777                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles               197914756                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles            338110902                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                105437320                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles             13046087                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               5174542                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved            19519920                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred              1400536                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts             636170059                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts              4304353                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               5174542                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles               205322358                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               31076264                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles     254971917                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                110916625                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles             52221607                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts             621253009                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents               123804                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents               2084188                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents               1933644                       # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents              33372173                       # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents            3863                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands          594055023                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            953160447                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       734477449                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           779699                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps            499665654                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                94389369                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts          14450095                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts      12489155                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                 72603024                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads           100339444                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores           85180632                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads         13386925                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores        14275413                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                 590006738                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded           14504084                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                589818158                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           830847                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       79048188                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     50610611                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        352346                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    659685833                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.894089                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.635498                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          430990787     65.13%     65.13% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1           95612119     14.45%     79.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           43322710      6.55%     86.12% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           31009109      4.69%     90.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           22951412      3.47%     94.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5           16184580      2.45%     96.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6           10912216      1.65%     98.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7            6468210      0.98%     99.35% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8            4317333      0.65%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0          430142670     65.20%     65.20% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1           95209085     14.43%     79.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2           43103455      6.53%     86.17% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3           30774369      4.67%     90.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           22787863      3.45%     94.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5           16081687      2.44%     96.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6           10870686      1.65%     98.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7            6433091      0.98%     99.35% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8            4282927      0.65%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      661768476                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      659685833                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                3013963     25.80%     25.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 25479      0.22%     26.01% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   3319      0.03%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               1      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     26.04% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4708735     40.30%     66.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              3932373     33.66%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                2991282     25.77%     25.77% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                 24682      0.21%     25.98% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                   3126      0.03%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     26.01% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4685148     40.36%     66.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite              3902762     33.62%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass                2      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            402293875     67.81%     67.81% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1465613      0.25%     68.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                66790      0.01%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                152      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         70080      0.01%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           106673645     17.98%     86.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           82732640     13.94%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu            399989408     67.82%     67.82% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult             1473233      0.25%     68.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                67059      0.01%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                153      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   4      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc         70210      0.01%     68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead           106137364     17.99%     86.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite           82080680     13.92%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             593302844                       # Type of FU issued
-system.cpu1.iq.rate                          0.859469                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                   11683870                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.019693                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1859837992                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        687326005                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    572108496                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1054067                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            524138                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       469445                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             604424270                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 562442                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         4728038                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total             589818158                       # Type of FU issued
+system.cpu1.iq.rate                          0.856990                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                   11607000                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.019679                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads        1850695958                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes        683728270                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses    568714201                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads            1064038                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            529691                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       473676                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses             600857355                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 567803                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads         4685307                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     15991835                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        20369                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       727913                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      8786210                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads     15994035                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses        20483                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation       710355                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      8709901                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      3909440                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      7480668                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads      3868542                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      7450104                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5204264                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               16486033                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles             12035619                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          608060202                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts          1765454                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts            100816739                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            85870948                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          12241352                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                233009                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents             11715765                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        727913                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2628157                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2293591                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             4921748                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            586639297                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            104576028                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          5786024                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               5174542                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               16661499                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles             12204142                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts          604643269                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts          1738208                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts            100339444                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts            85180632                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts          12202242                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                236266                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents             11879435                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents        710355                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect       2616920                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect      2284300                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts             4901220                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts            583187166                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts            104040866                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          5756605                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       132513                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   186249978                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               108834662                       # Number of branches executed
-system.cpu1.iew.exec_stores                  81673950                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.849816                       # Inst execution rate
-system.cpu1.iew.wb_sent                     573803675                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    572577941                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                282811002                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                490863765                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.829447                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.576150                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       79254249                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       14179859                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4389133                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    648242205                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.815623                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.819454                       # Number of insts commited each cycle
+system.cpu1.iew.exec_nop                       132447                       # number of nop insts executed
+system.cpu1.iew.exec_refs                   185065127                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches               108200674                       # Number of branches executed
+system.cpu1.iew.exec_stores                  81024261                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.847355                       # Inst execution rate
+system.cpu1.iew.wb_sent                     570418733                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                    569187877                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                281309683                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                488305636                       # num instructions consuming a value
+system.cpu1.iew.wb_rate                      0.827014                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.576093                       # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts       79095788                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls       14151738                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts          4369211                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    646199938                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.813158                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.817106                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    456295445     70.39%     70.39% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     93190134     14.38%     84.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     33049230      5.10%     89.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     15421896      2.38%     92.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     10834364      1.67%     93.91% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      6534810      1.01%     94.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      6130401      0.95%     95.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3914098      0.60%     96.47% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     22871827      3.53%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    455330275     70.46%     70.46% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1     92773758     14.36%     84.82% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2     32833911      5.08%     89.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3     15287498      2.37%     92.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4     10781023      1.67%     93.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5      6487132      1.00%     94.94% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      6078607      0.94%     95.88% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7      3894706      0.60%     96.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8     22733028      3.52%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    648242205                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           450050330                       # Number of instructions committed
-system.cpu1.commit.committedOps             528721496                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    646199938                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts           447366409                       # Number of instructions committed
+system.cpu1.commit.committedOps             525462634                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     161909642                       # Number of memory references committed
-system.cpu1.commit.loads                     84824904                       # Number of loads committed
-system.cpu1.commit.membars                    3632926                       # Number of memory barriers committed
-system.cpu1.commit.branches                 100459992                       # Number of branches committed
-system.cpu1.commit.fp_insts                    451058                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                485698001                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13255700                       # Number of function calls committed.
+system.cpu1.commit.refs                     160816140                       # Number of memory references committed
+system.cpu1.commit.loads                     84345409                       # Number of loads committed
+system.cpu1.commit.membars                    3627931                       # Number of memory barriers committed
+system.cpu1.commit.branches                  99847042                       # Number of branches committed
+system.cpu1.commit.fp_insts                    454333                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                482598910                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls            13134163                       # Number of function calls committed.
 system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       365572080     69.14%     69.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1129275      0.21%     69.36% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           50278      0.01%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.37% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        60179      0.01%     69.38% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.38% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.38% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.38% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       84824904     16.04%     85.42% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      77084738     14.58%    100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu       363400914     69.16%     69.16% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult        1135062      0.22%     69.37% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv           50467      0.01%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.38% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc        60009      0.01%     69.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.40% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead       84345409     16.05%     85.45% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite      76470731     14.55%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        528721496                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             22871827                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1229476063                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1229500763                       # The number of ROB writes
-system.cpu1.timesIdled                        4141402                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       28544446                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 48806249668                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  450050330                       # Number of Instructions Simulated
-system.cpu1.committedOps                    528721496                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.533857                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.533857                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.651951                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.651951                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               691759463                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              409243112                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   834045                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  529652                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                125054676                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               126221670                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1204731271                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              14298109                       # number of misc regfile writes
+system.cpu1.commit.op_class_0::total        525462634                       # Class of committed instruction
+system.cpu1.commit.bw_lim_events             22733028                       # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads                  1224126418                       # The number of ROB reads
+system.cpu1.rob.rob_writes                 1222625233                       # The number of ROB writes
+system.cpu1.timesIdled                        4106530                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                       28558477                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                 48790405544                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                  447366409                       # Number of Instructions Simulated
+system.cpu1.committedOps                    525462634                       # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi                              1.538435                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.538435                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.650011                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.650011                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               687757037                       # number of integer regfile reads
+system.cpu1.int_regfile_writes              406838676                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                   842941                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                  528902                       # number of floating regfile writes
+system.cpu1.cc_regfile_reads                124631004                       # number of cc regfile reads
+system.cpu1.cc_regfile_writes               125817612                       # number of cc regfile writes
+system.cpu1.misc_regfile_reads             1199807572                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes              14264439                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                40298                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               40298                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1903,10 +1898,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
@@ -1915,6 +1907,7 @@ system.iobus.pkt_count_system.realview.ethernet.dma::total           80
 system.iobus.pkt_count::total                  353738                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1924,24 +1917,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  7492168                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             47821000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             47828500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               344500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
@@ -1954,18 +1946,12 @@ system.iobus.reqLayer16.occupancy               14500                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25458500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25445500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              172500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            40141500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            40147500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           565650665                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              127000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565671459                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               45000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy           147714000                       # Layer occupancy (ticks)
@@ -1973,16 +1959,16 @@ system.iobus.respLayer3.utilization               0.0                       # La
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements               115458                       # number of replacements
-system.iocache.tags.tagsinuse               10.422741                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse               10.418706                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13100980146000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     5.902457                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     4.520285                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.368904                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.282518                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651421                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         13100979262000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet     5.907316                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     4.511389                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet     0.369207                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.281962                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.651169                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -2001,19 +1987,19 @@ system.iocache.demand_misses::total              8853                       # nu
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
 system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
 system.iocache.overall_misses::total             8853                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1698093507                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1703163007                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1684461016                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1689547016                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13865016452                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13865016452                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1698093507                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1703514007                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1698093507                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1703514007                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13867464649                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13867464649                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1684461016                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1689898016                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1684461016                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1689898016                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
@@ -2040,24 +2026,24 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 192680.529559                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 192447.797401                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 191133.667990                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 190909.267345                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129987.778932                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129987.778932                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 192680.529559                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 192422.230543                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 192680.529559                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 192422.230543                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         37009                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130010.731353                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130010.731353                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 191133.667990                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 190884.221846                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 191133.667990                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 190884.221846                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         36071                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3636                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3608                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.178493                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.997506                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -2076,19 +2062,19 @@ system.iocache.demand_mshr_misses::total         8853                       # nu
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1257443507                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1260663007                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1243811016                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1247047016                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8531816452                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8531816452                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1257443507                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1260864007                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1257443507                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1260864007                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8534264649                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8534264649                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1243811016                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1247248016                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1243811016                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1247248016                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -2102,312 +2088,312 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142680.529559                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 142447.797401                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141133.667990                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 140909.267345                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79987.778932                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79987.778932                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 142680.529559                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 142422.230543                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 142680.529559                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 142422.230543                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80010.731353                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80010.731353                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 141133.667990                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 140884.221846                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 141133.667990                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 140884.221846                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                  1318326                       # number of replacements
-system.l2c.tags.tagsinuse                65288.938042                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   49534529                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1380698                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    35.876440                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                  1326476                       # number of replacements
+system.l2c.tags.tagsinuse                65296.669801                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   49454623                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1388892                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    35.607249                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle              22398666000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   35503.403742                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   177.290447                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   268.045616                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3654.613344                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    10777.196597                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   178.643969                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   246.380396                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3657.335195                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    10826.028735                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.541739                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002705                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.data       0.164447                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002726                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003759                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.055807                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_blocks::1024        62027                       # Occupied blocks per task id
+system.l2c.tags.occ_blocks::writebacks   35546.103483                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   178.339981                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   269.475913                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3715.302647                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data    10815.708045                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker   174.213795                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   257.428239                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3587.286900                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data    10752.810798                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.542390                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.itb.walker     0.003928                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.054738                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::total           0.996348                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023          319                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        62097                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          344                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          522                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2801                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5049                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53552                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005264                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.946457                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                439709140                       # Number of tag accesses
-system.l2c.tags.data_accesses               439709140                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       516692                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       183733                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       528381                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       196932                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1425738                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      8016148                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         8016148                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     16001128                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        16001128                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            4984                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            4868                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                9852                       # number of UpgradeReq hits
+system.l2c.tags.age_task_id_blocks_1023::4          318                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
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+system.l2c.tags.age_task_id_blocks_1024::2         2767                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5122                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53561                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.004868                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.947525                       # Percentage of cache occupancy per task id
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+system.l2c.tags.data_accesses               439122291                       # Number of data accesses
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+system.l2c.ReadReq_hits::cpu1.itb.walker       198547                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1421802                       # number of ReadReq hits
+system.l2c.WritebackDirty_hits::writebacks      8003169                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         8003169                       # number of WritebackDirty hits
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+system.l2c.WritebackClean_hits::total        15970717                       # number of WritebackClean hits
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+system.l2c.UpgradeReq_hits::cpu1.data            4885                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                9886                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu0.data             5                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu1.data             3                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           820290                       # number of ReadExReq hits
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-system.l2c.ReadExReq_hits::total              1592779                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       7906464                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       8007151                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          15913615                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      3440520                       # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::total          6817471                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       364532                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       357882                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           722414                       # number of InvalidateReq hits
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-system.l2c.overall_hits::total               25749603                       # number of overall hits
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-system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
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+system.l2c.InvalidateReq_hits::total           720523                       # number of InvalidateReq hits
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784554                       # miss rate for UpgradeReq accesses
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 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.400000                       # miss rate for SCUpgradeReq accesses
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-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.428367                       # miss rate for InvalidateReq accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 138012.849931                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 138101.772031                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 139030.594406                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138189.280541                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 138346.684442                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 40409.996697                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41670.925707                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 41032.750118                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_miss_rate::total     0.333333                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.240450                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.242800                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.241589                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005488                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.006094                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005791                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041398                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.042885                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.042135                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.395041                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.433008                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.414246                       # miss rate for InvalidateReq accesses
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+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004154                       # miss rate for overall accesses
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+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 137032.838983                       # average ReadReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 40723.491072                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41185.383445                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 40951.159561                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        81000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        39750                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149817.768615                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 149546.348741                       # average ReadExReq miss latency
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-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 136094.215945                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 135705.280723                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141143.790696                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140253.144155                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 140700.419514                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 155245.642301                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 155253.910518                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total 155250.009355                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138012.849931                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138101.772031                       # average overall miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140492.941605                       # average ReadSharedReq miss latency
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+system.l2c.InvalidateReq_avg_miss_latency::total 155144.961780                       # average InvalidateReq miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2416,298 +2402,298 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks             1112675                       # number of writebacks
-system.l2c.writebacks::total                  1112675                       # number of writebacks
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-system.l2c.ReadReq_mshr_hits::total                82                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks             1119014                       # number of writebacks
+system.l2c.writebacks::total                  1119014                       # number of writebacks
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 system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           11                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data           10                       # number of ReadSharedReq MSHR hits
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 system.l2c.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
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 system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
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-system.l2c.overall_mshr_hits::cpu0.dtb.walker           14                       # number of overall MSHR hits
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 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
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 system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
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 system.l2c.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
 system.l2c.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        18166                       # number of UpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
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 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1254191000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   2539590500                       # number of UpgradeReq MSHR miss cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of overall MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::total  13945458496                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004173                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004295                       # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::total     0.005957                       # mshr miss rate for ReadReq accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6355367998                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  13944445496                       # number of overall MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004442                       # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::total     0.006021                       # mshr miss rate for ReadReq accesses
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.784708                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784554                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.784632                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.166667                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.784986                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784155                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.784576                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.285714                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.272727                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.239872                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.240940                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.240390                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005492                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005911                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005703                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041580                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.041976                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.041776                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.396578                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.428367                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.412756                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004173                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011102                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005492                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.087412                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004295                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.010236                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005911                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.086550                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.033812                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004173                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011102                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005492                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.087412                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004295                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.010236                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005911                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.086550                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.033812                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 128493.328652                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70758.532423                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70750.324364                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70754.478589                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.240450                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.242800                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.241589                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005488                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.006094                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005791                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041395                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.042882                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.042132                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.395041                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.433008                       # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total     0.414246                       # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004131                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.010769                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005488                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.087546                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004442                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.010701                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006094                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.087721                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034117                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004131                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.010769                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005488                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.087546                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004442                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.010701                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006094                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.087721                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034117                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 127829.676071                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70763.281849                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70751.310081                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70757.380919                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        71000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70750                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139289.246572                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139817.768615                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 139546.348741                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125283.634906                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126096.832756                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125707.843481                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131146.367199                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130252.654380                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130701.468233                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145245.642301                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145253.910518                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145250.009355                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125283.634906                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136311.100602                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126096.832756                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136218.050946                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 135122.369891                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125283.634906                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136311.100602                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126096.832756                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136218.050946                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 135122.369891                       # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        71250                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        71125                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139392.773852                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139774.479890                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 139578.674506                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125469.445522                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125584.780871                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125530.164611                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131080.893745                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130493.219474                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130784.609938                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145245.877268                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145055.017575                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145144.961780                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125469.445522                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136373.840007                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125584.780871                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136254.946515                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 135135.772667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125469.445522                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136373.840007                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125584.780871                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136254.946515                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 135135.772667                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167674.077548                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167572.516701                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176916.614845                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149596.631348                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176268.761086                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169907.768160                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172674.763273                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176976.360342                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149581.013880                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176241.949758                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169926.263903                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172679.442604                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 171784.651527                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 171719.761610                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173283.380473                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 158431.511395                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173321.915512                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 158423.602545                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               54325                       # Transaction distribution
-system.membus.trans_dist::ReadResp             460220                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33697                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33697                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1219305                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           210974                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            36812                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           36815                       # Transaction distribution
-system.membus.trans_dist::ReadExReq           1010906                       # Transaction distribution
-system.membus.trans_dist::ReadExResp          1010906                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        405895                       # Transaction distribution
+system.membus.trans_dist::ReadReq               54324                       # Transaction distribution
+system.membus.trans_dist::ReadResp             463697                       # Transaction distribution
+system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
+system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1225644                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           212879                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            36939                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           36943                       # Transaction distribution
+system.membus.trans_dist::ReadExReq           1016012                       # Transaction distribution
+system.membus.trans_dist::ReadExResp          1016012                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        409373                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6862                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4252499                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4382141                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       341858                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4723999                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4278076                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4407714                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342018                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       342018                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4749732                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13724                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    162617772                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    162789478                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7248896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7248896                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               170038374                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             2884                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3081006                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    163572972                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    163744670                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7253184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7253184                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               170997854                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             2815                       # Total snoops (count)
+system.membus.snoop_fanout::samples           3097878                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 3081006    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 3097878    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3081006                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           113865000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3097878                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           113853500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               50156                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5486002                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5460502                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8251811507                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          8296545910                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         7689965068                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         7735775396                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          227507173                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227455723                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2761,61 +2747,61 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     53750764                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     27303829                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         4497                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2153                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2153                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     53686542                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     27275171                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         4479                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2151                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2151                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            2028554                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          25149235                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33697                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33697                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      9235460                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     16001128                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2638618                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           45748                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            11                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          45759                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2096838                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2096838                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      16005202                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      7123570                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1336841                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1230177                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48052512                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31550783                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       914007                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2494586                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              83011888                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2049706496                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1102812070                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3078592                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8396320                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3163993478                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2090247                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         30104268                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.027207                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.162685                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            2028951                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          25110801                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             33696                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            33696                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      9228831                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     15970717                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2648270                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           45894                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            12                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          45906                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          2100210                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         2100210                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      15974768                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      7115167                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1336742                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1230078                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47961225                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31535681                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       914731                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2490388                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              82902025                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2045811904                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1101659806                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3076664                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8367272                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             3158915646                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         2102692                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         30077408                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.027456                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.163407                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               29285228     97.28%     97.28% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 819040      2.72%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               29251611     97.25%     97.25% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 825797      2.75%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           30104268                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        51537960463                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           30077408                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        51459246454                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1443392                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1450396                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       24054534227                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       24008829328                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       14512097283                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       14504682071                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         529644514                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         530598551                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1447978944                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy        1447405469                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   16329                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal
index 92e057a43..df2c0b95c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal
@@ -106,15 +106,15 @@
 [    3.135048] pci_bus 0000:00: fixups for bus

 [    3.135056] pci_bus 0000:00: bus scan returning with max=00

 [    3.135067] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc

-[    3.135084] pci 0000:00:00.0: fixup irq: got 33

-[    3.135092] pci 0000:00:00.0: assigning IRQ 33

+[    3.135083] pci 0000:00:00.0: fixup irq: got 33

+[    3.135091] pci 0000:00:00.0: assigning IRQ 33

 [    3.135101] pci 0000:00:01.0: fixup irq: got 34

-[    3.135109] pci 0000:00:01.0: assigning IRQ 34

+[    3.135108] pci 0000:00:01.0: assigning IRQ 34

 [    3.135119] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

 [    3.135131] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]

-[    3.135144] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

+[    3.135143] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

 [    3.135156] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

-[    3.135167] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]

+[    3.135166] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]

 [    3.135177] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]

 [    3.135188] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

 [    3.135199] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

@@ -123,7 +123,7 @@
 [    3.135708] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

 [    3.135730] ata_piix 0000:00:01.0: enabling bus mastering

 [    3.135914] scsi0 : ata_piix

-[    3.135984] scsi1 : ata_piix

+[    3.135983] scsi1 : ata_piix

 [    3.136005] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

 [    3.136017] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

 [    3.136090] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

@@ -133,9 +133,9 @@
 [    3.290704] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66

 [    3.290713] ata1.00: 2096640 sectors, multi 0: LBA 

 [    3.290737] ata1.00: configured for UDMA/33

-[    3.290779] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5

-[    3.290857] sd 0:0:0:0: Attached scsi generic sg0 type 0

-[    3.290877] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)

+[    3.290778] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5

+[    3.290856] sd 0:0:0:0: Attached scsi generic sg0 type 0

+[    3.290876] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)

 [    3.290908] sd 0:0:0:0: [sda] Write Protect is off

 [    3.290916] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00

 [    3.290933] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA

@@ -143,24 +143,24 @@
 [    3.291104] sd 0:0:0:0: [sda] Attached SCSI disk

 [    3.410957] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01

 [    3.410969] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection

-[    3.410986] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k

-[    3.410996] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.

-[    3.411012] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k

+[    3.410987] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k

+[    3.410997] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.

+[    3.411013] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k

 [    3.411024] igb: Copyright (c) 2007-2014 Intel Corporation.

 [    3.411070] usbcore: registered new interface driver usb-storage

-[    3.411110] mousedev: PS/2 mouse device common for all mice

+[    3.411111] mousedev: PS/2 mouse device common for all mice

 [    3.411211] usbcore: registered new interface driver usbhid

 [    3.411220] usbhid: USB HID core driver

 [    3.411245] TCP: cubic registered

-[    3.411252] NET: Registered protocol family 17

+[    3.411253] NET: Registered protocol family 17

 
 [    3.411533] devtmpfs: mounted

 [    3.411579] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)

 
 
-[    3.448025] udevd[607]: starting version 182

+[    3.448034] udevd[607]: starting version 182

 Starting Bootlog daemon: bootlogd.


-[    3.532647] random: dd urandom read with 19 bits of entropy available

+[    3.532645] random: dd urandom read with 19 bits of entropy available

 Populating dev cache


 net.ipv4.conf.default.rp_filter = 1


 net.ipv4.conf.all.rp_filter = 1


@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
 hwclock: can't open '/dev/misc/rtc': No such file or directory


 
INIT: Entering runlevel: 5



 Configuring network interfaces... udhcpc (v1.21.1) started


-[    3.650912] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

+[    3.650911] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None

 Sending discover...


 Sending discover...


 Sending discover...


diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
index c9adce55a..8093ae03e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -503,10 +503,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -533,7 +532,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -697,12 +696,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=true
-pci_io_base=788529152
 system=system
 
 [system.realview.aaci_fake]
@@ -795,16 +791,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -820,7 +815,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -983,13 +978,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -999,9 +994,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1043,7 +1037,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1124,14 +1118,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1148,7 +1141,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1163,7 +1156,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1286,17 +1279,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=12
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=788529152
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1348,7 +1343,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1363,7 +1358,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
index 80e6922d7..faa00bf6c 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
@@ -1505,51 +1505,3 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout
index fb14ae164..ffdfb4a34 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 20:16:56
-gem5 executing on e104799-lin, pid 28142
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 11:31:31
+gem5 executing on e104799-lin, pid 30776
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing
 
 Selected 64-bit ARM architecture, updating default disk image...
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
index c78f46d36..61bf9a286 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
@@ -1,159 +1,159 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                 51.771790                       # Number of seconds simulated
-sim_ticks                                51771790334500                       # Number of ticks simulated
-final_tick                               51771790334500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                 51.771755                       # Number of seconds simulated
+sim_ticks                                51771755296500                       # Number of ticks simulated
+final_tick                               51771755296500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 629815                       # Simulator instruction rate (inst/s)
-host_op_rate                                   740156                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            39468336741                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 677148                       # Number of bytes of host memory used
-host_seconds                                  1311.73                       # Real time elapsed on the host
-sim_insts                                   826146401                       # Number of instructions simulated
-sim_ops                                     970885096                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 629134                       # Simulator instruction rate (inst/s)
+host_op_rate                                   739361                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            39432920775                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 676920                       # Number of bytes of host memory used
+host_seconds                                  1312.91                       # Real time elapsed on the host
+sim_insts                                   825994487                       # Number of instructions simulated
+sim_ops                                     970712321                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker        64192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        68416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2225432                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         31926704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        62336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        66048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2388572                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         32205016                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        391616                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             69398332                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2225432                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2388572                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         4614004                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     60462464                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker        69120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        72384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          2314776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         32049840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        60480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        66688                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst          2364572                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         32106392                       # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide        391424                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             69495676                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      2314776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst      2364572                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         4679348                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     60509440                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         15860                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data          4720                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          60483044                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1003                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1069                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             55433                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            498858                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          974                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         1032                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             57068                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            503213                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6119                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1124769                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          944726                       # Number of write requests responded to by this memory
+system.physmem.bytes_written::total          60530020                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker         1080                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         1131                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             56829                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            500782                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker          945                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         1042                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             56693                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data            501672                       # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide           6116                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1126290                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          945460                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             1983                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data              590                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               947299                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1240                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1321                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               42985                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              616681                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          1204                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          1276                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               46137                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              622057                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7564                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1340466                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          42985                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          46137                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              89122                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1167865                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               948033                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker          1335                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          1398                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               44711                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              619060                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1168                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          1288                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               45673                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              620153                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide             7561                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1342347                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          44711                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          45673                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              90384                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1168773                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data                306                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 91                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1168263                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1167865                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1240                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1321                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              42985                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             616988                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         1204                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         1276                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              46137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             622148                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7564                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2508729                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1124769                       # Number of read requests accepted
-system.physmem.writeReqs                       947299                       # Number of write requests accepted
-system.physmem.readBursts                     1124769                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     947299                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 71946624                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     38592                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  60482240                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  69398332                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               60483044                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      603                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total                1169171                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1168773                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker         1335                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         1398                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              44711                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             619367                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1168                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         1288                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              45673                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             620244                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide            7561                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2511518                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1126290                       # Number of read requests accepted
+system.physmem.writeReqs                       948033                       # Number of write requests accepted
+system.physmem.readBursts                     1126290                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     948033                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 72036608                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     45952                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  60529408                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  69495676                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               60530020                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      718                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    2260                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         292556                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               71523                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               69926                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               70289                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               64893                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               64804                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               73543                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               62283                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               61053                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               62184                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              109202                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              70171                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              67486                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              64856                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              71148                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              68907                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              71898                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               59424                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               59953                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60707                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               57771                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               56630                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               62461                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               55190                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               55103                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               55968                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               60498                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              60512                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              59733                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              57588                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              61842                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              59660                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              61995                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         294002                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               72701                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               69688                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               71671                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               65333                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               67150                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               75432                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               63718                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               62281                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               61723                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              108434                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              66581                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              66036                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              64933                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              72823                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              65732                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              71336                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               59678                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               59397                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               61038                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               58102                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               58442                       # Per bank write bursts
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 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51771787505500                       # Total gap between requests
+system.physmem.numWrRetry                          14                       # Number of times write queue was full causing retry
+system.physmem.totGap                    51771752359500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
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 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1081653                       # Read request sizes (log2)
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-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -165,137 +165,137 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::stdev     331.159215                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         176110     39.90%     39.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       107371     24.33%     64.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        38199      8.65%     72.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        22075      5.00%     77.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        15487      3.51%     81.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11537      2.61%     84.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10154      2.30%     86.30% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151        51867     11.75%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         441395                       # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::stdev      295.103325                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047          52849     99.99%     99.99% # Reads before turning the bus around for writes
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 system.physmem.rdPerTurnAround::2048-4095            3      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6144-8191            2      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::12288-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::samples         52856                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.879427                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.143276                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        7.780491                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3               105      0.20%      0.20% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::8-11               62      0.12%      0.46% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::16-19           49304     93.28%     93.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             574      1.09%     95.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27             365      0.69%     95.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             594      1.12%     96.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             149      0.28%     97.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             324      0.61%     97.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             209      0.40%     98.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              26      0.05%     98.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              84      0.16%     98.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55             140      0.26%     98.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              28      0.05%     98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              39      0.07%     98.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             454      0.86%     99.58% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::samples         52882                       # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::gmean       17.137705                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.800600                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3               115      0.22%      0.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                64      0.12%      0.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11               68      0.13%      0.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15             119      0.23%      0.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           49331     93.29%     93.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             541      1.02%     95.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27             348      0.66%     95.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             615      1.16%     96.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35             130      0.25%     97.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             329      0.62%     97.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             199      0.38%     98.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              29      0.05%     98.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              82      0.16%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55             151      0.29%     98.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59              24      0.05%     98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63              42      0.08%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             468      0.88%     99.57% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::68-71              24      0.05%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              18      0.03%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79             112      0.21%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              11      0.02%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               3      0.01%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.00%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               2      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             5      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            24      0.05%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             3      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             7      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             4      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           52856                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    13880638873                       # Total ticks spent queuing
-system.physmem.totMemAccLat               34958751373                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5620830000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12347.50                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::72-75              19      0.04%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79             123      0.23%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               6      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               3      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               3      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.00%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            28      0.05%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             5      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             3      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             3      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           52882                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    13860867186                       # Total ticks spent queuing
+system.physmem.totMemAccLat               34965342186                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   5627860000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12314.51                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31097.50                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  31064.51                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.39                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.17                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.34                       # Average system read bandwidth in MiByte/s
@@ -305,40 +305,40 @@ system.physmem.busUtil                           0.02                       # Da
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.36                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     908414                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    719391                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.81                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  76.12                       # Row buffer hit rate for writes
-system.physmem.avgGap                     24985563.94                       # Average gap between requests
-system.physmem.pageHitRate                      78.67                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1674025920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  913407000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                4198810200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3027708720                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3381481552800                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1295576085285                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29926602975000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34613474564925                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.577915                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49785017997770                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1728773800000                       # Time in different power states
+system.physmem.avgWrQLen                         9.22                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     909331                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    719783                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   80.79                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  76.11                       # Row buffer hit rate for writes
+system.physmem.avgGap                     24958385.15                       # Average gap between requests
+system.physmem.pageHitRate                      78.65                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1706473440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  931111500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                4274158200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3064100400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           3381479010000                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           1298516894550                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           29923999959000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             34613971707090                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.588021                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   49780674651877                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    1728772500000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    257997880230                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    262307488123                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1662920280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  907347375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4569645600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3096118080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3381481552800                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1293349218120                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29928556367250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34613623169505                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.580786                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49788229996275                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1728773800000                       # Time in different power states
+system.physmem_1.actEnergy                 1636777800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  893083125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                4505264400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3064502160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           3381479010000                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           1291239562905                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           29930383583250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             34613201783640                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.573149                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   49791285234291                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    1728772500000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    254784926225                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    251692056959                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
@@ -392,68 +392,69 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                   115431                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               115431                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17925                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        83577                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore            9                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       115422                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean     0.155949                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev    52.981983                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047       115421    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks                   115460                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               115460                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17717                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        83741                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore           10                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples       115450                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean     0.259853                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev    63.668442                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047       115448    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       115422                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       101511                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 24872.984209                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21671.671712                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 15716.369374                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       100971     99.47%     99.47% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071            1      0.00%     99.47% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          465      0.46%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           13      0.01%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           29      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215            9      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkWaitTime::total       115450                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples       101468                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 25057.924666                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 21784.198284                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 16152.265883                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535       100874     99.41%     99.41% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071            1      0.00%     99.42% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607          517      0.51%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143            5      0.00%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679           33      0.03%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215           13      0.01%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751           19      0.02%     99.99% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       101511                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples    118356120                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean   -14.037796                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     1779815204   1503.78%   1503.78% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1    -1661459084  -1403.78%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total    118356120                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        83577     82.34%     82.34% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        17925     17.66%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       101502                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       115431                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total       101468                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples  -3983763676                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     1.449006                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     1788733704    -44.90%    -44.90% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1    -5772497380    144.90%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total  -3983763676                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        83741     82.54%     82.54% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        17717     17.46%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       101458                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       115460                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       115431                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       101502                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       115460                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       101458                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       101502                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       216933                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       101458                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       216918                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    77847569                       # DTB read hits
-system.cpu0.dtb.read_misses                     88672                       # DTB read misses
-system.cpu0.dtb.write_hits                   70757652                       # DTB write hits
-system.cpu0.dtb.write_misses                    26759                       # DTB write misses
+system.cpu0.dtb.read_hits                    77974126                       # DTB read hits
+system.cpu0.dtb.read_misses                     88549                       # DTB read misses
+system.cpu0.dtb.write_hits                   70569009                       # DTB write hits
+system.cpu0.dtb.write_misses                    26911                       # DTB write misses
 system.cpu0.dtb.flush_tlb                       51778                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              18503                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    514                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   67979                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid              18628                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                    500                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                   67577                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  3908                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  3961                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9235                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                77936241                       # DTB read accesses
-system.cpu0.dtb.write_accesses               70784411                       # DTB write accesses
+system.cpu0.dtb.perms_faults                     9183                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                78062675                       # DTB read accesses
+system.cpu0.dtb.write_accesses               70595920                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        148605221                       # DTB hits
-system.cpu0.dtb.misses                         115431                       # DTB misses
-system.cpu0.dtb.accesses                    148720652                       # DTB accesses
+system.cpu0.dtb.hits                        148543135                       # DTB hits
+system.cpu0.dtb.misses                         115460                       # DTB misses
+system.cpu0.dtb.accesses                    148658595                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -483,277 +484,278 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                    74042                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                74042                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4197                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        64819                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        74042                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          74042    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        74042                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        69016                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 28471.542831                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 25336.788819                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 18532.815053                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        68368     99.06%     99.06% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071            2      0.00%     99.06% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          559      0.81%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           14      0.02%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           33      0.05%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        69016                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                    74491                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                74491                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4184                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3        65168                       # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples        74491                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          74491    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        74491                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples        69352                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 28600.025955                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 25396.938168                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 18997.799631                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535        68658     99.00%     99.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071            2      0.00%     99.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607          606      0.87%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143           12      0.02%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679           31      0.04%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751           21      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total        69352                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   1705681704                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     1705681704    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total   1705681704                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        64819     93.92%     93.92% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         4197      6.08%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        69016                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K        65168     93.97%     93.97% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         4184      6.03%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        69352                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        74042                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        74042                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        74491                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        74491                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        69016                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        69016                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       143058                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   414105554                       # ITB inst hits
-system.cpu0.itb.inst_misses                     74042                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        69352                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        69352                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       143843                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                   413472692                       # ITB inst hits
+system.cpu0.itb.inst_misses                     74491                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                       51778                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              18503                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    514                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   50190                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid              18628                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                    500                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                   50115                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               414179596                       # ITB inst accesses
-system.cpu0.itb.hits                        414105554                       # DTB hits
-system.cpu0.itb.misses                          74042                       # DTB misses
-system.cpu0.itb.accesses                    414179596                       # DTB accesses
-system.cpu0.numCycles                     51772404432                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses               413547183                       # ITB inst accesses
+system.cpu0.itb.hits                        413472692                       # DTB hits
+system.cpu0.itb.misses                          74491                       # DTB misses
+system.cpu0.itb.accesses                    413547183                       # DTB accesses
+system.cpu0.numCycles                     51772397578                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   15961                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  413854142                       # Number of instructions committed
-system.cpu0.committedOps                    486394511                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            447175967                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                436796                       # Number of float alu accesses
-system.cpu0.num_func_calls                   24852805                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     62753360                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   447175967                       # number of integer instructions
-system.cpu0.num_fp_insts                       436796                       # number of float instructions
-system.cpu0.num_int_register_reads          647088270                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         354432965                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              705701                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             368548                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           107266365                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          106966753                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    148595341                       # number of memory refs
-system.cpu0.num_load_insts                   77843031                       # Number of load instructions
-system.cpu0.num_store_insts                  70752310                       # Number of store instructions
-system.cpu0.num_idle_cycles              50229100240.489449                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1543304191.510550                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.029809                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.970191                       # Percentage of idle cycles
-system.cpu0.Branches                         92298416                       # Number of branches fetched
+system.cpu0.committedInsts                  413219664                       # Number of instructions committed
+system.cpu0.committedOps                    485565994                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            446433803                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                442229                       # Number of float alu accesses
+system.cpu0.num_func_calls                   24786010                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     62671041                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   446433803                       # number of integer instructions
+system.cpu0.num_fp_insts                       442229                       # number of float instructions
+system.cpu0.num_int_register_reads          644929511                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         353812607                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              719009                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             362960                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           107066643                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes          106758859                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                    148533323                       # number of memory refs
+system.cpu0.num_load_insts                   77969520                       # Number of load instructions
+system.cpu0.num_store_insts                  70563803                       # Number of store instructions
+system.cpu0.num_idle_cycles              50229359275.953438                       # Number of idle cycles
+system.cpu0.num_busy_cycles              1543038302.046558                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.029804                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.970196                       # Percentage of idle cycles
+system.cpu0.Branches                         92169862                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                336911536     69.23%     69.23% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1057551      0.22%     69.45% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    48617      0.01%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                 20      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             54899      0.01%     69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
-system.cpu0.op_class::MemRead                77843031     16.00%     85.46% # Class of executed instruction
-system.cpu0.op_class::MemWrite               70752310     14.54%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                336128174     69.18%     69.18% # Class of executed instruction
+system.cpu0.op_class::IntMult                 1076007      0.22%     69.41% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    49967      0.01%     69.42% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                 20      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.42% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc             53572      0.01%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.43% # Class of executed instruction
+system.cpu0.op_class::MemRead                77969520     16.05%     85.48% # Class of executed instruction
+system.cpu0.op_class::MemWrite               70563803     14.52%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 486667985                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          9213148                       # number of replacements
+system.cpu0.op_class::total                 485841084                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          9212621                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.942746                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          287360735                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          9213660                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            31.188554                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs          287301900                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          9213133                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            31.183952                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       5830459500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   293.957596                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   217.985149                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.574136                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.425752                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   301.496360                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   210.446385                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.588860                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.411028                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999888                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          402                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          414                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1195960121                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1195960121                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     72895855                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     72819187                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      145715042                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     67181478                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     66888003                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     134069481                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       186279                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       186038                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       372317                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       164783                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       168129                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       332912                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1645519                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1628369                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3273888                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1788293                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1767339                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3555632                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    140077333                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    139707190                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       279784523                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    140263612                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    139893228                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      280156840                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2397654                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      2407349                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      4805003                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       991343                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       966962                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1958305                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       562095                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       539989                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1102084                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       607610                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       610974                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1218584                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       143596                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       139766                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       283362                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses       1195722346                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses      1195722346                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     73035245                       # number of ReadReq hits
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+system.cpu0.dcache.WriteLineReq_hits::cpu0.data       165113                       # number of WriteLineReq hits
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+system.cpu0.dcache.WriteLineReq_misses::cpu0.data       610138                       # number of WriteLineReq misses
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 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3388997                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      3374311                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       6763308                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3951092                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      3914300                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      7865392                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  40954472000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  41182021500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  82136493500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33182162500                       # number of WriteReq miss cycles
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-system.cpu0.dcache.WriteReq_miss_latency::total  65690096500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  36148226000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  36927465500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  73075691500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2158365000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2163537000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4321902000                       # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.overall_misses::total      7865591                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41217416000                       # number of ReadReq miss cycles
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+system.cpu0.dcache.ReadReq_miss_latency::total  82241453000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33031636500                       # number of WriteReq miss cycles
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+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2143987500                       # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.LoadLockedReq_miss_latency::total   4322058500                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        82000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  74136634500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  73689955500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 147826590000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  74136634500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  73689955500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 147826590000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     75293509                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     75226536                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    150520045                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     68172821                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     67854965                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    136027786                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       748374                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       726027                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1474401                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       772393                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       779103                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1551496                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1789115                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1768135                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3557250                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1788293                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1767340                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3555633                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    143466330                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    143081501                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    286547831                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    144214704                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    143807528                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    288022232                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031844                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032001                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.031923                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014542                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014250                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.014396                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.751088                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.743759                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747479                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.786659                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.784202                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.785425                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.080261                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.079047                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079658                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_latency::cpu0.data  74249052500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  73736674000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 147985726500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  74249052500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  73736674000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 147985726500                       # number of overall miss cycles
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+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       775251                       # number of WriteLineReq accesses(hits+misses)
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+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031860                       # miss rate for ReadReq accesses
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+system.cpu0.dcache.ReadReq_miss_rate::total     0.031925                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014428                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014376                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.014402                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.749010                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.746429                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747719                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.787020                       # miss rate for WriteLineReq accesses
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+system.cpu0.dcache.WriteLineReq_miss_rate::total     0.785467                       # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.078520                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.080385                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079450                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.023622                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023583                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.023603                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027397                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027219                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.027308                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17081.060070                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17106.793199                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17093.952595                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 33471.928989                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 33618.626171                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 33544.364387                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59492.480374                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 60440.322338                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59967.709653                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15030.815622                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15479.708942                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15252.228598                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.023597                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023617                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.023607                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027305                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027325                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.027315                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17149.035795                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17086.471445                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 17117.770009                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 33672.697311                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 33459.931101                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 33566.493229                       # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59224.653275                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 60594.020233                       # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59908.483397                       # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15322.076354                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15265.961100                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15293.745997                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21875.686081                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21838.519182                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 21857.142984                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18763.580929                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18825.832333                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18794.561034                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21938.324452                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21824.417101                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 21881.419730                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18862.531041                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18766.017368                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18814.317513                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -762,216 +764,216 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      7212950                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7212950                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        11283                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        11037                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        22320                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        11488                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         9712                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21200                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        33167                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        33718                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        66885                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        22771                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data        20749                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        43520                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        22771                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data        20749                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        43520                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2386371                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2396312                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      4782683                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       979855                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       957250                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1937105                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       561145                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       539145                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1100290                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       607610                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       610974                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1218584                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       110429                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       106048                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       216477                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks      7219847                       # number of writebacks
+system.cpu0.dcache.writebacks::total          7219847                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        11900                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        10524                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        22424                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        11494                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         9715                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        21209                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        33194                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        33628                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        66822                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        23394                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data        20239                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        43633                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        23394                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data        20239                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        43633                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2391583                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2390442                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      4782025                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       969468                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       967951                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total      1937419                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       550930                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       549790                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total      1100720                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       610138                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       608619                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total      1218757                       # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       106734                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       109047                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total       215781                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      3366226                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      3353562                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      6719788                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      3927371                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      3892707                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      7820078                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16580                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17120                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33700                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16850                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        16857                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      3361051                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data      3358393                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      6719444                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      3911981                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data      3908183                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      7820164                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16515                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17184                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33699                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16888                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        16819                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        33430                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        33977                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67407                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  37889939000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  38156301500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  76046240500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  31683288500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31094174500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  62777463000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10445512500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10132014500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  20577527000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  35540616000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  36316491500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  71857107500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1500809000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1468573500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2969382500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        33403                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        34003                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67406                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38123459500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  38015008500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  76138468000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  31542881000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31287443500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  62830324500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10406081000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10129235000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  20535316000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  35525073500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  36270053000                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  71795126500                       # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1470813500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1497747500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2968561000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        81000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  69573227500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  69250476000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 138823703500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  80018740000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  79382490500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 159401230500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3026868000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3173397500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6200265500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3017135500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3200441000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6217576500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6044003500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6373838500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12417842000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031694                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031855                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.031774                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014373                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014107                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014241                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.749819                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.742596                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746262                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.786659                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.784202                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.785425                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.061723                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059977                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060855                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  69666340500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  69302452000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 138968792500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  80072421500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  79431687000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 159504108500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3017045500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3182297000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6199342500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3020495500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3197083500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6217579000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6037541000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6379380500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12416921500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031702                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031850                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.031776                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014259                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014233                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014246                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.747720                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.745285                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746502                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.787020                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.783916                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.785467                       # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059893                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.061439                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060664                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023464                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023438                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.023451                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027233                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027069                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.027151                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15877.639730                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15922.927190                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15900.330526                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32334.670436                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32482.814834                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32407.878251                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18614.640601                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18792.744994                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18701.912223                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58492.480374                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59440.322338                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58967.709653                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13590.714396                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13848.196100                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13716.849827                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023434                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023475                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.023454                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027136                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027178                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.027157                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15940.680085                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15902.920255                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15921.804675                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32536.278660                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32323.375357                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32429.910360                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18888.209028                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18423.825461                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18656.257722                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58224.653275                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59594.020233                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58908.483397                       # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13780.177825                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13734.880373                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13757.286323                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20668.020359                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20649.827258                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20658.940952                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20374.632292                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20392.618941                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20383.585752                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182561.399276                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185362.003505                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183984.139466                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179058.486647                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189858.278460                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.503961                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180795.797188                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187592.739206                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184221.846396                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20727.546384                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20635.599229                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20681.590992                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20468.509816                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20324.454356                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20396.517068                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182685.165002                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185189.536778                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183962.209561                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178854.541686                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190087.609251                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.578129                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180748.465707                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187612.284210                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184210.923360                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements         13381945                       # number of replacements
+system.cpu0.icache.tags.replacements         13370435                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          511.782255                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          813274304                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         13382457                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            60.771673                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.total_refs          813133937                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs         13370947                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            60.813489                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      61705740500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   277.029971                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   234.752284                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.541074                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.458501                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   285.320721                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   226.461534                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.557267                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.442308                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999575                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          202                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        840039228                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       840039228                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    407397826                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    405876478                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      813274304                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    407397826                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    405876478                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       813274304                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    407397826                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    405876478                       # number of overall hits
-system.cpu0.icache.overall_hits::total      813274304                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6707728                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      6674734                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     13382462                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6707728                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      6674734                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      13382462                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6707728                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      6674734                       # number of overall misses
-system.cpu0.icache.overall_misses::total     13382462                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  91398041500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  91277594500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 182675636000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  91398041500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  91277594500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 182675636000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  91398041500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  91277594500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 182675636000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    414105554                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    412551212                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    826656766                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    414105554                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    412551212                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    826656766                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    414105554                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    412551212                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    826656766                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016198                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016179                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.016189                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016198                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016179                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.016189                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016198                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016179                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.016189                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13625.782307                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13675.090947                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13650.375843                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13625.782307                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13675.090947                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13650.375843                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13625.782307                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13675.090947                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13650.375843                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        839875841                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       839875841                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    406751315                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst    406382622                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      813133937                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    406751315                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst    406382622                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       813133937                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    406751315                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst    406382622                       # number of overall hits
+system.cpu0.icache.overall_hits::total      813133937                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      6721377                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst      6649575                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total     13370952                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      6721377                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst      6649575                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total      13370952                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      6721377                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst      6649575                       # number of overall misses
+system.cpu0.icache.overall_misses::total     13370952                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  91746511500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  90909260000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 182655771500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  91746511500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  90909260000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 182655771500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  91746511500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  90909260000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 182655771500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    413472692                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst    413032197                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    826504889                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    413472692                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst    413032197                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    826504889                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    413472692                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst    413032197                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    826504889                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016256                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016099                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.016178                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016256                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016099                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.016178                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016256                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016099                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.016178                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13649.957665                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.439152                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13660.640731                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13649.957665                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13671.439152                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13660.640731                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13649.957665                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13671.439152                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13660.640731                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -980,56 +982,56 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks     13381945                       # number of writebacks
-system.cpu0.icache.writebacks::total         13381945                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6707728                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6674734                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     13382462                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6707728                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      6674734                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     13382462                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6707728                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      6674734                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     13382462                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks     13370435                       # number of writebacks
+system.cpu0.icache.writebacks::total         13370435                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6721377                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6649575                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total     13370952                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      6721377                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst      6649575                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total     13370952                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      6721377                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst      6649575                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total     13370952                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        22062                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        21063                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        22062                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        21063                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  84690313500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  84602860500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 169293174000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  84690313500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  84602860500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 169293174000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  84690313500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  84602860500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 169293174000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  85025134500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  84259685000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 169284819500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  85025134500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  84259685000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 169284819500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  85025134500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  84259685000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 169284819500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780591500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   2656208000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5436799500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2780591500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   2656208000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   5436799500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016198                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016179                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016189                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016198                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016179                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.016189                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016198                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016179                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.016189                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12625.782307                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12675.090947                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12650.375843                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12625.782307                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12675.090947                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12650.375843                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12625.782307                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12675.090947                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12650.375843                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016256                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016099                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016178                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016256                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016099                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.016178                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016256                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016099                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.016178                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12649.957665                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12671.439152                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12660.640731                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12649.957665                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12671.439152                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12660.640731                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12649.957665                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12671.439152                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12660.640731                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043                       # average ReadReq mshr uncacheable latency
@@ -1066,69 +1068,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                   118026                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               118026                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17902                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        85905                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore            9                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       118017                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.101680                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    34.930834                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-1023       118016    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::11264-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       118017                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       103816                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 25027.404254                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21748.751472                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15644.616464                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       103269     99.47%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                   118174                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               118174                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17820                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        86207                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore            6                       # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples       118168                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         118168    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       118168                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples       104033                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 25040.588083                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21749.548904                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15700.304805                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535       103488     99.48%     99.48% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::65536-131071            2      0.00%     99.48% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          471      0.45%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143            7      0.01%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679           35      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           17      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       103816                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   2951550812                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.475602                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.499404                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1547787704     52.44%     52.44% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     1403763108     47.56%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   2951550812                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        85906     82.75%     82.75% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        17902     17.25%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       103808                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       118026                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607          470      0.45%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143            4      0.00%     99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679           36      0.03%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751           22      0.02%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total       104033                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples  -1363590484                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean     2.149961                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1568075704   -115.00%   -115.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1    -2931666188    215.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1363590484                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K        86208     82.87%     82.87% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        17820     17.13%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       104028                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       118174                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       118026                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       103808                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       118174                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       104028                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       103808                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       221834                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       104028                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       222202                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    77737807                       # DTB read hits
-system.cpu1.dtb.read_misses                     91072                       # DTB read misses
-system.cpu1.dtb.write_hits                   70427017                       # DTB write hits
-system.cpu1.dtb.write_misses                    26954                       # DTB write misses
+system.cpu1.dtb.read_hits                    77583369                       # DTB read hits
+system.cpu1.dtb.read_misses                     91391                       # DTB read misses
+system.cpu1.dtb.write_hits                   70584225                       # DTB write hits
+system.cpu1.dtb.write_misses                    26783                       # DTB write misses
 system.cpu1.dtb.flush_tlb                       51774                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              19160                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    483                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   67493                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid              19034                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                    497                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                   67777                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  3798                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                  3786                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     9286                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                77828879                       # DTB read accesses
-system.cpu1.dtb.write_accesses               70453971                       # DTB write accesses
+system.cpu1.dtb.perms_faults                     9337                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                77674760                       # DTB read accesses
+system.cpu1.dtb.write_accesses               70611008                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        148164824                       # DTB hits
-system.cpu1.dtb.misses                         118026                       # DTB misses
-system.cpu1.dtb.accesses                    148282850                       # DTB accesses
+system.cpu1.dtb.hits                        148167594                       # DTB hits
+system.cpu1.dtb.misses                         118174                       # DTB misses
+system.cpu1.dtb.accesses                    148285768                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1158,129 +1156,130 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                    75801                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                75801                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4159                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        66376                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        75801                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          75801    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        75801                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        70535                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 28466.739916                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 25302.677208                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18338.850484                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        69863     99.05%     99.05% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071            2      0.00%     99.05% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          592      0.84%     99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           11      0.02%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           25      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751           22      0.03%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        70535                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                    75448                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                75448                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4153                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3        66142                       # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples        75448                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          75448    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        75448                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples        70295                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 28625.784195                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25406.753839                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18792.899470                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535        69604     99.02%     99.02% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071            1      0.00%     99.02% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607          599      0.85%     99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143           17      0.02%     99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679           33      0.05%     99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751           19      0.03%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total        70295                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1449734704                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1449734704    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1449734704                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        66376     94.10%     94.10% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         4159      5.90%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        70535                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K        66142     94.09%     94.09% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         4153      5.91%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        70295                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        75801                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        75801                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        75448                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        75448                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        70535                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        70535                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       146336                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   412551212                       # ITB inst hits
-system.cpu1.itb.inst_misses                     75801                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        70295                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        70295                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       145743                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                   413032197                       # ITB inst hits
+system.cpu1.itb.inst_misses                     75448                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                       51774                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              19160                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    483                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   50654                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid              19034                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                    497                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                   50656                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               412627013                       # ITB inst accesses
-system.cpu1.itb.hits                        412551212                       # DTB hits
-system.cpu1.itb.misses                          75801                       # DTB misses
-system.cpu1.itb.accesses                    412627013                       # DTB accesses
-system.cpu1.numCycles                     51771176237                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses               413107645                       # ITB inst accesses
+system.cpu1.itb.hits                        413032197                       # DTB hits
+system.cpu1.itb.misses                          75448                       # DTB misses
+system.cpu1.itb.accesses                    413107645                       # DTB accesses
+system.cpu1.numCycles                     51771113015                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  412292259                       # Number of instructions committed
-system.cpu1.committedOps                    484490585                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            445445369                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                462328                       # Number of float alu accesses
-system.cpu1.num_func_calls                   24787523                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     62474042                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   445445369                       # number of integer instructions
-system.cpu1.num_fp_insts                       462328                       # number of float instructions
-system.cpu1.num_int_register_reads          644065931                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         352949314                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              746699                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             388588                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           106522074                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          106212078                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    148153513                       # number of memory refs
-system.cpu1.num_load_insts                   77732872                       # Number of load instructions
-system.cpu1.num_store_insts                  70420641                       # Number of store instructions
-system.cpu1.num_idle_cycles              50233711408.448738                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1537464828.551259                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.029697                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.970303                       # Percentage of idle cycles
-system.cpu1.Branches                         92021257                       # Number of branches fetched
+system.cpu1.committedInsts                  412774823                       # Number of instructions committed
+system.cpu1.committedOps                    485146327                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses            446024475                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                456863                       # Number of float alu accesses
+system.cpu1.num_func_calls                   24836924                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts     62537039                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                   446024475                       # number of integer instructions
+system.cpu1.num_fp_insts                       456863                       # number of float instructions
+system.cpu1.num_int_register_reads          646025772                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         353451520                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads              733263                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes             394304                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           106699743                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes          106398156                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                    148156265                       # number of memory refs
+system.cpu1.num_load_insts                   77578568                       # Number of load instructions
+system.cpu1.num_store_insts                  70577697                       # Number of store instructions
+system.cpu1.num_idle_cycles              50233500723.542557                       # Number of idle cycles
+system.cpu1.num_busy_cycles              1537612291.457444                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.029700                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.970300                       # Percentage of idle cycles
+system.cpu1.Branches                         92112103                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                335453186     69.20%     69.20% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1057928      0.22%     69.42% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    48471      0.01%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  1      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             57500      0.01%     69.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.44% # Class of executed instruction
-system.cpu1.op_class::MemRead                77732872     16.03%     85.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite               70420641     14.53%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                336122870     69.24%     69.24% # Class of executed instruction
+system.cpu1.op_class::IntMult                 1039751      0.21%     69.46% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    47048      0.01%     69.47% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  1      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc             58827      0.01%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.48% # Class of executed instruction
+system.cpu1.op_class::MemRead                77578568     15.98%     85.46% # Class of executed instruction
+system.cpu1.op_class::MemWrite               70577697     14.54%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 484770600                       # Class of executed instruction
-system.iobus.trans_dist::ReadReq                40328                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40328                       # Transaction distribution
+system.cpu1.op_class::total                 485424763                       # Class of executed instruction
+system.iobus.trans_dist::ReadReq                40321                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               40321                       # Transaction distribution
 system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
 system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1290,18 +1289,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231014                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       231014                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231000                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total       231000                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353798                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  353784                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1311,24 +1308,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334488                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334488                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334432                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      7334432                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492408                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             42148500                       # Layer occupancy (ticks)
+system.iobus.pkt_size::total                  7492352                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             42150500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               322500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer4.occupancy                11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
@@ -1341,79 +1337,73 @@ system.iobus.reqLayer16.occupancy               16500                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25714000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            25707000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              171000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            38602500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            38601000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           565399896                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              121500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           565515993                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147774000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy           147760000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements               115489                       # number of replacements
-system.iocache.tags.tagsinuse               10.442885                       # Cycle average of tags in use
+system.iocache.tags.replacements               115482                       # number of replacements
+system.iocache.tags.tagsinuse               10.442874                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115505                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs               115498                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         13183784929000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.514154                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.928730                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ethernet     3.514153                       # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide     6.928721                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ethernet     0.219635                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.433046                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide     0.433045                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.652680                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039920                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039920                       # Number of data accesses
+system.iocache.tags.tag_accesses              1039857                       # Number of tag accesses
+system.iocache.tags.data_accesses             1039857                       # Number of data accesses
 system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8843                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8880                       # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide         8836                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total             8873                       # number of ReadReq misses
 system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8843                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8883                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide         8836                       # number of demand (read+write) misses
+system.iocache.demand_misses::total              8876                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8843                       # number of overall misses
-system.iocache.overall_misses::total             8883                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5070500                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1656329126                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1661399626                       # number of ReadReq miss cycles
+system.iocache.overall_misses::realview.ide         8836                       # number of overall misses
+system.iocache.overall_misses::total             8876                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet      5087000                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide   1609197370                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total   1614284370                       # number of ReadReq miss cycles
 system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  13864058367                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  13864058367                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5421500                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1656329126                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1661750626                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5421500                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1656329126                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1661750626                       # number of overall miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide  13863548526                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total  13863548526                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet      5438000                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide   1609197370                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   1614635370                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet      5438000                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide   1609197370                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   1614635370                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8843                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8880                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide         8836                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total           8873                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8843                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8883                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide         8836                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total            8876                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8843                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8883                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide         8836                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total           8876                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1427,55 +1417,55 @@ system.iocache.demand_miss_rate::total              1                       # mi
 system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 187303.983490                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 187094.552477                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137486.486486                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 182118.308058                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 181932.195424                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
 system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129978.796661                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129978.796661                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 187303.983490                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 187070.879883                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 187303.983490                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 187070.879883                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         34559                       # number of cycles access was blocked
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129974.016782                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 129974.016782                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet       135950                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 182118.308058                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 181910.248986                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet       135950                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 182118.308058                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 181910.248986                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         32984                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3493                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 3440                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.893788                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.588372                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8843                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8880                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide         8836                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total         8873                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8843                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8883                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide         8836                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total         8876                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8843                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8883                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220500                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1214179126                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1217399626                       # number of ReadReq MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide         8836                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total         8876                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3237000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide   1167397370                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total   1170634370                       # number of ReadReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8530858367                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   8530858367                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3421500                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1214179126                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1217600626                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3421500                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1214179126                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1217600626                       # number of overall MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8530348526                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   8530348526                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet      3438000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   1167397370                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   1170835370                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet      3438000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   1167397370                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   1170835370                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1489,303 +1479,304 @@ system.iocache.demand_mshr_miss_rate::total            1                       #
 system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137303.983490                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 137094.552477                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87486.486486                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132118.308058                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 131932.195424                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79978.796661                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.796661                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 137303.983490                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 137070.879883                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 137303.983490                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 137070.879883                       # average overall mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79974.016782                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79974.016782                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85950                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 132118.308058                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131910.248986                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85950                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 132118.308058                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131910.248986                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   985866                       # number of replacements
-system.l2c.tags.tagsinuse                65209.136555                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   41640566                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1047670                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    39.745880                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   987985                       # number of replacements
+system.l2c.tags.tagsinuse                65209.498770                       # Cycle average of tags in use
+system.l2c.tags.total_refs                   41654495                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1049725                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    39.681340                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle              56075802500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37748.652544                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   103.945817                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   161.083000                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3928.961788                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     9675.154455                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    97.159223                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   145.757666                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4633.882908                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     8714.539154                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.575999                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001586                       # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu0.inst       0.059951                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.147631                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001483                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.002224                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.070707                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.132973                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995012                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          334                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        61470                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          334                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          429                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2433                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5559                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53016                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005096                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.937958                       # Percentage of cache occupancy per task id
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-system.l2c.tags.data_accesses               371905439                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker       203125                       # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu1.dtb.walker       208882                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       158880                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 726069                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      7212950                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         7212950                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     13380350                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        13380350                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data            4416                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            4453                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                8869                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           803064                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           783002                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1586066                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       6674320                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       6638729                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          13313049                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      2950718                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data      2933310                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          5884028                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       371511                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       368808                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           740319                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        203125                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        155182                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             6674320                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             3753782                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        208882                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        158880                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             6638729                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             3716312                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                21509212                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       203125                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       155182                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            6674320                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            3753782                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       208882                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       158880                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            6638729                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            3716312                       # number of overall hits
-system.l2c.overall_hits::total               21509212                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1003                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1069                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker          974                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         1032                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 4078                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data         16194                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data         16399                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             32593                       # number of UpgradeReq misses
+system.l2c.tags.occ_blocks::writebacks   37651.465010                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker   109.956357                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker   153.679221                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4175.861855                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     9735.363337                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    92.633503                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker   148.604603                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4437.462816                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     8704.472068                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.574516                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001678                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.002345                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.063719                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.148550                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001413                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker     0.002268                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.067710                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.132820                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995018                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_task_id_blocks::1024        61469                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4          270                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           34                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          404                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2443                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5529                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53059                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.004135                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.937943                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                371736931                       # Number of tag accesses
+system.l2c.tags.data_accesses               371736931                       # Number of data accesses
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+system.l2c.ReadReq_hits::cpu0.itb.walker       156439                       # number of ReadReq hits
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+system.l2c.ReadReq_hits::total                 728610                       # number of ReadReq hits
+system.l2c.WritebackDirty_hits::writebacks      7219847                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         7219847                       # number of WritebackDirty hits
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+system.l2c.WritebackClean_hits::total        13368850                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data            4381                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            4519                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                8900                       # number of UpgradeReq hits
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+system.l2c.ReadCleanReq_hits::total          13300518                       # number of ReadCleanReq hits
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+system.l2c.ReadSharedReq_hits::cpu1.data      2942858                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          5882589                       # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data       374559                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data       366598                       # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total           741157                       # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker        204252                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu0.inst             6686573                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data             3732452                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker        209151                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker        158768                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst             6613945                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data             3735894                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                21497474                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker       204252                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker       156439                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst            6686573                       # number of overall hits
+system.l2c.overall_hits::cpu0.data            3732452                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker       209151                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker       158768                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst            6613945                       # number of overall hits
+system.l2c.overall_hits::cpu1.data            3735894                       # number of overall hits
+system.l2c.overall_hits::total               21497474                       # number of overall hits
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+system.l2c.ReadReq_misses::cpu0.itb.walker         1131                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker          945                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker         1042                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                 4198                       # number of ReadReq misses
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+system.l2c.UpgradeReq_misses::total             32652                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         156181                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         153396                       # number of ReadExReq misses
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-system.l2c.ReadCleanReq_misses::total           69413                       # number of ReadCleanReq misses
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-system.l2c.ReadSharedReq_misses::total         215422                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       236099                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       242166                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         478265                       # number of InvalidateReq misses
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-system.l2c.demand_misses::cpu0.itb.walker         1069                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             33408                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            263408                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker          974                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         1032                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             36005                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            261591                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                598490                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1003                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1069                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            33408                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           263408                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker          974                       # number of overall misses
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-system.l2c.overall_misses::cpu1.inst            36005                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           261591                       # number of overall misses
-system.l2c.overall_misses::total               598490                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    136349000                       # number of ReadReq miss cycles
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 system.l2c.SCUpgradeReq_miss_latency::cpu1.data        79500                       # number of SCUpgradeReq miss cycles
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 system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
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-system.l2c.demand_miss_rate::cpu1.data       0.065761                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.027072                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004914                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.006842                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.004981                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.065570                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004641                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.006454                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005394                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.065761                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.027072                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 135941.176471                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 138141.253508                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 135810.061602                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 136656.976744                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 136667.729279                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 41530.783006                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41229.617660                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 41379.253214                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.164651                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.162490                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.163572                       # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005178                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005358                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total     0.005268                       # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.035916                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.034900                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.035408                       # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data     0.386108                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data     0.397656                       # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total     0.391875                       # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.005260                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.007178                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu0.data       0.066471                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004498                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.006520                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005358                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::total           0.027182                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.005260                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.007178                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu0.data      0.066471                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004498                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::total          0.027182                       # miss rate for overall accesses
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+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 137333.333333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 137378.306878                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 137853.646833                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 137259.766556                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 41262.766023                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41854.188086                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 41562.262649                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 130643.039166                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130656.223109                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 130649.571835                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 132185.509459                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132001.944174                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 132090.292885                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132703.908531                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 132702.842091                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 132703.372915                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 130150.186998                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130189.809882                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total 130170.249757                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135941.176471                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138141.253508                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 132185.509459                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 131481.969037                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 135810.061602                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 136656.976744                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 132001.944174                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 131502.712249                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 131596.923925                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135941.176471                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138141.253508                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 132185.509459                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 131481.969037                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 135810.061602                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 136656.976744                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 132001.944174                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 131502.712249                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 131596.923925                       # average overall miss latency
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+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130652.920493                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 130588.213860                       # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 132217.575566                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132121.681168                       # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 132169.066076                       # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132600.651960                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 132782.359685                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 132690.203624                       # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 130219.548432                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130186.409444                       # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total 130202.755444                       # average InvalidateReq miss latency
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+system.l2c.demand_avg_miss_latency::cpu0.inst 132217.575566                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 131380.034993                       # average overall miss latency
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+system.l2c.demand_avg_miss_latency::cpu1.data 131523.580194                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 131575.846667                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 137333.333333                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu0.data 131380.034993                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 137853.646833                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 132121.681168                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 131523.580194                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 131575.846667                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1794,261 +1785,261 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              838095                       # number of writebacks
-system.l2c.writebacks::total                   838095                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1003                       # number of ReadReq MSHR misses
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-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          974                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         1032                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            4078                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data        16194                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data        16399                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        32593                       # number of UpgradeReq MSHR misses
+system.l2c.writebacks::writebacks              838829                       # number of writebacks
+system.l2c.writebacks::total                   838829                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1080                       # number of ReadReq MSHR misses
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+system.l2c.UpgradeReq_mshr_misses::cpu0.data        16117                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data        16535                       # number of UpgradeReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
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-system.l2c.ReadExReq_mshr_misses::total        309577                       # number of ReadExReq MSHR misses
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-system.l2c.ReadCleanReq_mshr_misses::total        69413                       # number of ReadCleanReq MSHR misses
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-system.l2c.InvalidateReq_mshr_misses::cpu1.data       242166                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       478265                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1003                       # number of demand (read+write) MSHR misses
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 system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        22062                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16580                       # number of ReadReq MSHR uncacheable
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 system.l2c.ReadReq_mshr_uncacheable::cpu1.inst        21063                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17120                       # number of ReadReq MSHR uncacheable
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-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16850                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        16857                       # number of WriteReq MSHR uncacheable
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 system.l2c.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
 system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        22062                       # number of overall MSHR uncacheable misses
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 system.l2c.overall_mshr_uncacheable_misses::cpu1.inst        21063                       # number of overall MSHR uncacheable misses
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1159164500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total   2303762500                       # number of UpgradeReq MSHR miss cycles
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 system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        69500                       # number of SCUpgradeReq MSHR miss cycles
 system.l2c.SCUpgradeReq_mshr_miss_latency::total        69500                       # number of SCUpgradeReq MSHR miss cycles
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-system.l2c.ReadCleanReq_mshr_miss_latency::total   8474653500                       # number of ReadCleanReq MSHR miss cycles
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-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  29105885500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total  57473224500                       # number of InvalidateReq MSHR miss cycles
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 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2504816500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2819242000                       # number of ReadReq MSHR uncacheable cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::total   5829935500                       # number of WriteReq MSHR uncacheable cycles
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 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2504816500                       # number of overall MSHR uncacheable cycles
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.786447                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.786093                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::total     0.785811                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.163815                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.163310                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.004981                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005394                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005187                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.035065                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.035573                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.035318                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.388570                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.396361                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.392476                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004914                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.004981                       # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005394                       # mshr miss rate for demand accesses
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-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.004981                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005394                       # mshr miss rate for overall accesses
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-system.l2c.overall_mshr_miss_rate::total     0.027072                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 126667.729279                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70680.375448                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70685.072261                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70682.738625                       # average UpgradeReq mshr miss latency
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+system.l2c.InvalidateReq_mshr_miss_rate::total     0.391875                       # mshr miss rate for InvalidateReq accesses
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 127259.766556                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70685.332258                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70682.310251                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70683.801911                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120643.039166                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120656.223109                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 120649.571835                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122185.509459                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122001.944174                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122090.292885                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122703.908531                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122702.842091                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122703.372915                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120150.186998                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120189.809882                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120170.249757                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122185.509459                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121481.969037                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122001.944174                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121502.712249                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 121596.923925                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122185.509459                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121481.969037                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122001.944174                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121502.712249                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 121596.923925                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120524.496157                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120652.920493                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 120588.213860                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122217.575566                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122121.681168                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122169.066076                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122600.651960                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122782.359685                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122690.203624                       # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120219.548432                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120186.409444                       # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120202.755444                       # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122217.575566                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121380.034993                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122121.681168                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121523.580194                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 121575.846667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122217.575566                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121380.034993                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122121.681168                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121523.580194                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 121575.846667                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170038.721351                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170162.700575                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172838.872664                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138964.926782                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167558.189911                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178357.952186                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172959.192453                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172666.084730                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138954.857857                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167354.216011                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178587.311969                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172959.266621                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168788.438528                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168742.777595                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175577.052123                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 149331.560091                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175594.918095                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 149324.678145                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               76825                       # Transaction distribution
-system.membus.trans_dist::ReadResp             374618                       # Transaction distribution
+system.membus.trans_dist::ReadReq               76824                       # Transaction distribution
+system.membus.trans_dist::ReadResp             376266                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
 system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       944726                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           152734                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            33164                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       945460                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           154121                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            33223                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           33165                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            787274                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           787274                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        297793                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           33224                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            787142                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           787142                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        299442                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6924                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3294284                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3423970                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       340925                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       340925                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                3764895                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6922                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3299562                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      3429246                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       340924                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       340924                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                3770170                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    122665376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    122835190                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7216000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7216000                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               130051190                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3421                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2435800                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13844                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    122809888                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total    122979698                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7215808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      7215808                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               130195506                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             3417                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2439476                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 2435800    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 2439476    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2435800                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           106891000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             2439476                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           106887500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5617000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             5646000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          6213973567                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy          6220729239                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5964440131                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         5972547051                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy          227489060                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy          227475321                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -2102,61 +2093,61 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests     45763569                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     23167437                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1754                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2234                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2234                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests     45741552                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests     23157457                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests         1749                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           2207                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         2207                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            1181074                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          20663813                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq            1182207                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp          20652494                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             33707                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            33707                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      8157694                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     13380350                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2156668                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           41465                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      8165321                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean     13368850                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict         2150617                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           41555                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          41466                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          1895643                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         1895643                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      13382462                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      6108330                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1325248                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1218584                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     40231524                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27858913                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       757060                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1077336                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              69924833                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1712992468                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    973558114                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2529304                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3311872                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2692391758                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1591852                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples         25069303                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.021336                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.144501                       # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp          41556                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq          1895867                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp         1895867                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq      13370952                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      6107399                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq      1325421                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp      1218757                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     40197004                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27857487                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       758584                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1079607                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              69892682                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1711519828                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    973953566                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2539040                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3323424                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total             2691335858                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                         1592408                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples         25060590                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.021420                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.144781                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               24534434     97.87%     97.87% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 534869      2.13%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0               24523786     97.86%     97.86% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 536804      2.14%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           25069303                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        43835486500                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total           25060590                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy        43819448000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1550881                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy          1523382                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       20116818000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy       20099553000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       12673228476                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy       12672308976                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         440897000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         441204000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         663352000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         664179000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal
index 7229df406..b028e910d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal
@@ -104,7 +104,7 @@
 [    3.145027] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]

 [    3.145041] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]

 [    3.145103] pci_bus 0000:00: fixups for bus

-[    3.145113] pci_bus 0000:00: bus scan returning with max=00

+[    3.145112] pci_bus 0000:00: bus scan returning with max=00

 [    3.145127] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc

 [    3.145154] pci 0000:00:00.0: fixup irq: got 33

 [    3.145164] pci 0000:00:00.0: assigning IRQ 33

@@ -113,19 +113,19 @@
 [    3.145202] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]

 [    3.145217] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]

 [    3.145232] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]

-[    3.145247] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

+[    3.145246] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]

 [    3.145260] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]

 [    3.145273] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]

 [    3.145286] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]

 [    3.145300] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]

-[    3.146217] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

-[    3.146746] ata_piix 0000:00:01.0: version 2.13

-[    3.146758] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

-[    3.146802] ata_piix 0000:00:01.0: enabling bus mastering

-[    3.147407] scsi0 : ata_piix

+[    3.146216] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled

+[    3.146745] ata_piix 0000:00:01.0: version 2.13

+[    3.146757] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)

+[    3.146801] ata_piix 0000:00:01.0: enabling bus mastering

+[    3.147406] scsi0 : ata_piix

 [    3.147592] scsi1 : ata_piix

 [    3.147648] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34

-[    3.147662] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

+[    3.147661] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34

 [    3.147864] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI

 [    3.147877] e1000: Copyright (c) 1999-2006 Intel Corporation.

 [    3.147899] e1000 0000:00:00.0: enabling device (0000 -> 0002)

@@ -158,7 +158,7 @@
 [    3.423483] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)

 
 
-[    3.470486] udevd[607]: starting version 182

+[    3.470485] udevd[607]: starting version 182

 Starting Bootlog daemon: bootlogd.


 [    3.586582] random: dd urandom read with 21 bits of entropy available

 Populating dev cache


diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index 15805fa4d..6c3b8ef2c 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
@@ -28,8 +28,9 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -207,6 +208,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -223,6 +225,7 @@ system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
@@ -257,6 +260,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
@@ -273,6 +277,7 @@ system=system
 tags=system.cpu.dtb_walker_cache.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.dtb.walker.port
 mem_side=system.cpu.toL2Bus.slave[3]
 
@@ -599,6 +604,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -615,6 +621,7 @@ system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
@@ -665,6 +672,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
@@ -681,6 +689,7 @@ system=system
 tags=system.cpu.itb_walker_cache.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.itb.walker.port
 mem_side=system.cpu.toL2Bus.slave[2]
 
@@ -700,6 +709,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -716,6 +726,7 @@ system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
@@ -731,12 +742,13 @@ size=4194304
 
 [system.cpu.toL2Bus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_latency=0
 frontend_latency=1
 response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
 snoop_response_latency=1
 system=system
 use_default_range=false
@@ -744,6 +756,13 @@ width=32
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
 
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
 [system.cpu.tracer]
 type=ExeTracer
 eventq_index=0
@@ -1197,8 +1216,8 @@ frontend_latency=2
 response_latency=2
 use_default_range=false
 width=16
-default=system.pc.pciconfig.pio
-master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+default=system.pc.pci_host.pio
+master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
@@ -1207,6 +1226,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
@@ -1223,7 +1243,8 @@ system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
-cpu_side=system.iobus.master[19]
+writeback_clean=false
+cpu_side=system.iobus.master[18]
 mem_side=system.membus.slave[4]
 
 [system.iocache.tags]
@@ -1273,7 +1294,7 @@ pio=system.membus.default
 
 [system.pc]
 type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -1294,7 +1315,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[13]
+pio=system.iobus.master[12]
 
 [system.pc.com_1]
 type=Uart8250
@@ -1306,7 +1327,7 @@ pio_latency=100000
 platform=system.pc
 system=system
 terminal=system.pc.com_1.terminal
-pio=system.iobus.master[14]
+pio=system.iobus.master[13]
 
 [system.pc.com_1.terminal]
 type=Terminal
@@ -1332,7 +1353,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[15]
+pio=system.iobus.master[14]
 
 [system.pc.fake_com_3]
 type=IsaFake
@@ -1350,7 +1371,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[16]
+pio=system.iobus.master[15]
 
 [system.pc.fake_com_4]
 type=IsaFake
@@ -1368,7 +1389,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[17]
+pio=system.iobus.master[16]
 
 [system.pc.fake_floppy]
 type=IsaFake
@@ -1386,7 +1407,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[18]
+pio=system.iobus.master[17]
 
 [system.pc.i_dont_exist1]
 type=IsaFake
@@ -1404,7 +1425,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[11]
+pio=system.iobus.master[10]
 
 [system.pc.i_dont_exist2]
 type=IsaFake
@@ -1422,17 +1443,19 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[12]
+pio=system.iobus.master[11]
 
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
+[system.pc.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=13835058055282163712
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=9223372036854775808
 platform=system.pc
-size=16777216
 system=system
 pio=system.iobus.default
 
@@ -1555,14 +1578,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
 eventq_index=0
+host=system.pc.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=4
 pci_func=0
 pio_latency=30000
-platform=system.pc
 system=system
-config=system.iobus.master[4]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[3]
 
@@ -1586,7 +1608,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/work/gem5/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1609,7 +1631,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1714,7 +1736,7 @@ pio_addr=4273995776
 pio_latency=100000
 system=system
 int_master=system.iobus.slave[2]
-pio=system.iobus.master[10]
+pio=system.iobus.master[9]
 
 [system.pc.south_bridge.keyboard]
 type=I8042
@@ -1728,7 +1750,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
 pio_addr=0
 pio_latency=100000
 system=system
-pio=system.iobus.master[5]
+pio=system.iobus.master[4]
 
 [system.pc.south_bridge.keyboard.keyboard_int_pin]
 type=X86IntSourcePin
@@ -1749,7 +1771,7 @@ pio_addr=9223372036854775840
 pio_latency=100000
 slave=system.pc.south_bridge.pic2
 system=system
-pio=system.iobus.master[6]
+pio=system.iobus.master[5]
 
 [system.pc.south_bridge.pic1.output]
 type=X86IntSourcePin
@@ -1766,7 +1788,7 @@ pio_addr=9223372036854775968
 pio_latency=100000
 slave=Null
 system=system
-pio=system.iobus.master[7]
+pio=system.iobus.master[6]
 
 [system.pc.south_bridge.pic2.output]
 type=X86IntSourcePin
@@ -1781,7 +1803,7 @@ int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=100000
 system=system
-pio=system.iobus.master[8]
+pio=system.iobus.master[7]
 
 [system.pc.south_bridge.pit.int_pin]
 type=X86IntSourcePin
@@ -1795,7 +1817,7 @@ i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=100000
 system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[8]
 
 [system.physmem]
 type=DRAMCtrl
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index 9ee84cae3..17f645de1 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@@ -1,13 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  6 2015 14:29:04
-gem5 started Jul  6 2015 20:46:38
-gem5 executing on e104799-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5/outgoing/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
+gem5 compiled Dec  4 2015 15:10:31
+gem5 started Dec  4 2015 15:13:28
+gem5 executing on e104799-lin, pid 29885
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5130108675000 because m5_exit instruction encountered
+Exiting @ tick 5144274809000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index eac9fa93b..0e907e72d 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,132 +1,132 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.152314                       # Number of seconds simulated
-sim_ticks                                5152313559000                       # Number of ticks simulated
-final_tick                               5152313559000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.144275                       # Number of seconds simulated
+sim_ticks                                5144274809000                       # Number of ticks simulated
+final_tick                               5144274809000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 120887                       # Simulator instruction rate (inst/s)
-host_op_rate                                   238950                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1530523119                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 767492                       # Number of bytes of host memory used
-host_seconds                                  3366.37                       # Real time elapsed on the host
-sim_insts                                   406949634                       # Number of instructions simulated
-sim_ops                                     804396566                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 169693                       # Simulator instruction rate (inst/s)
+host_op_rate                                   335427                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2145113000                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 770200                       # Number of bytes of host memory used
+host_seconds                                  2398.14                       # Real time elapsed on the host
+sim_insts                                   406947274                       # Number of instructions simulated
+sim_ops                                     804399711                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker         4096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3840                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1035776                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10724352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1034048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10709312                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11792896                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1035776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1035776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9542784                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9542784                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker           64                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             11775872                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1034048                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1034048                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9547776                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9547776                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker           60                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16184                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             167568                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16157                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             167333                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                184264                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          149106                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               149106                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker            795                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total                183998                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          149184                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               149184                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker            746                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               201031                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2081463                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5503                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2288854                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          201031                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             201031                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1852136                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1852136                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1852136                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           795                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               201009                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2081792                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5511                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2289122                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          201009                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             201009                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1856000                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1856000                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1856000                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           746                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              201031                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2081463                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5503                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4140990                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        184264                       # Number of read requests accepted
-system.physmem.writeReqs                       149106                       # Number of write requests accepted
-system.physmem.readBursts                      184264                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     149106                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 11780160                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     12736                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9541632                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  11792896                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9542784                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      199                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst              201009                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2081792                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5511                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4145122                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        183998                       # Number of read requests accepted
+system.physmem.writeReqs                       149184                       # Number of write requests accepted
+system.physmem.readBursts                      183998                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     149184                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 11761088                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     14784                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9546240                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  11775872                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9547776                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      231                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          58128                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11264                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10595                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12318                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11595                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               11491                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10948                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               11084                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               11123                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10622                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11029                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11540                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11371                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              12384                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              12484                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              11992                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              12225                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                9588                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9011                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9691                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9485                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9599                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                9316                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                9059                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                9052                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8752                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9407                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9210                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8756                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9659                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9383                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9487                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9633                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          58239                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11315                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10581                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12129                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11752                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               11319                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10663                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10930                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               11239                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10920                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               11403                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11471                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11421                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              12415                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12512                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11823                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11874                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9756                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9158                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9767                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9469                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9300                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                9148                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8815                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8963                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8876                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9249                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9141                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9048                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9841                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9699                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9635                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9295                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           6                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5152313509500                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5144274759500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  184264                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  183998                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 149106                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    169844                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     11471                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 149184                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    169620                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     11412                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                      1942                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       461                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        40                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        36                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        37                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       450                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        36                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                        33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       23                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                       24                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -156,300 +156,300 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2273                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     7394                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     8312                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     8280                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     9465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     8746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     9965                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     9927                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9938                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    11756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     9034                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8390                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     8612                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7922                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      338                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       36                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        73162                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      291.431727                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.195666                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     313.031817                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          28160     38.49%     38.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17784     24.31%     62.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7754     10.60%     73.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         4294      5.87%     79.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2960      4.05%     83.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2393      3.27%     86.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1365      1.87%     88.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1117      1.53%     89.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7335     10.03%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          73162                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7284                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.269357                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      562.815412                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           7283     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2916                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     7399                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7449                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     8122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     8310                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     9443                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     8747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     9907                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    10037                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9884                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    11487                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     9002                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7610                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7540                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      380                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      268                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      126                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      149                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       40                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        72943                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      292.108413                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     174.353373                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     313.792232                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          28114     38.54%     38.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17711     24.28%     62.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         7670     10.52%     73.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4213      5.78%     79.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2951      4.05%     83.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2449      3.36%     86.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1349      1.85%     88.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1138      1.56%     89.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7348     10.07%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          72943                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7277                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.251615                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      563.083563                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           7276     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7284                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7284                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.467875                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.652190                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.050833                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            6239     85.65%     85.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             170      2.33%     87.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              40      0.55%     88.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             173      2.38%     90.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              22      0.30%     91.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             151      2.07%     93.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43             103      1.41%     94.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              10      0.14%     94.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              24      0.33%     95.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              33      0.45%     95.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               7      0.10%     95.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.11%     95.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             223      3.06%     98.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               4      0.05%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               9      0.12%     99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              29      0.40%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               2      0.03%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.03%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.01%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             6      0.08%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.03%     99.64% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            7277                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7277                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.497458                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.666266                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.148532                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            6223     85.52%     85.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             179      2.46%     87.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              37      0.51%     88.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             181      2.49%     90.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              17      0.23%     91.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             151      2.08%     93.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             102      1.40%     94.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               5      0.07%     94.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              29      0.40%     95.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              31      0.43%     95.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.07%     95.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               9      0.12%     95.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             222      3.05%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.08%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               6      0.08%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              40      0.55%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.01%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               1      0.01%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             5      0.07%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.01%     99.64% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::120-123             1      0.01%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.04%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            18      0.25%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7284                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2101117298                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5552336048                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    920325000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11415.08                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            17      0.23%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7277                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2097648589                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5543279839                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    918835000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11414.72                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30165.08                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30164.72                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.85                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.86                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        22.81                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     150235                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    109755                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.62                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.61                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15455240.45                       # Average gap between requests
-system.physmem.pageHitRate                      78.04                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  269725680                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  147171750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 705252600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                484710480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           336523814640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           132965791830                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2974749226500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             3445845693480                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.796291                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   4948684136224                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    172046940000                       # Time in different power states
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        21.26                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     150147                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    109836                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.71                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.62                       # Row buffer hit rate for writes
+system.physmem.avgGap                     15439833.96                       # Average gap between requests
+system.physmem.pageHitRate                      78.08                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  269030160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  146792250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 701430600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                481956480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           335998980720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           132992885070                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2969904214500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3440495289780                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.800889                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   4940616567724                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    171778620000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     31582322276                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     31879461276                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  283379040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  154621500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 730446600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                481379760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           336523814640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           133234904790                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2974513162500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             3445921708830                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.811045                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   4948281584736                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    172046940000                       # Time in different power states
+system.physmem_1.actEnergy                  282418920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  154097625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 731944200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                484600320                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           335998980720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           133085381535                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2969823077250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3440560500570                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.813565                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   4940481114488                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    171778620000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     31981299014                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     32014679262                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                86361942                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86361942                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            844867                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             79712463                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                77809670                       # Number of BTB hits
+system.cpu.branchPred.lookups                86341843                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          86341843                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            843606                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             79482226                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                77803537                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.612929                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1539914                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             177576                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.887969                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1532975                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             177711                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        465537238                       # number of cpu cycles simulated
+system.cpu.numCycles                        465489033                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27283425                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      426658175                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86361942                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79349584                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     433433945                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1774834                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     138611                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                62197                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        198243                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           56                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          777                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8943730                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                426192                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    4516                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          462004671                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.822565                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.015508                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27349012                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      426558725                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86341843                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79336512                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     433328456                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1773234                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     140367                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                61411                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        195746                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           62                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          949                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8924695                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                425342                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4681                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          461962620                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.822369                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.015343                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                297416009     64.38%     64.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2127138      0.46%     64.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72011199     15.59%     80.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1542030      0.33%     80.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2092912      0.45%     81.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2282044      0.49%     81.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1471797      0.32%     82.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1847192      0.40%     82.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81214350     17.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                297385469     64.37%     64.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2141918      0.46%     64.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72009169     15.59%     80.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1542851      0.33%     80.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2093373      0.45%     81.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2277762      0.49%     81.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1468275      0.32%     82.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1844826      0.40%     82.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81198977     17.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            462004671                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.185510                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.916486                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 22519882                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             281035605                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 150243041                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               7318726                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 887417                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              834212570                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 887417                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 25306548                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               229981312                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       14515163                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 154096108                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              37218123                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              830907338                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                454391                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               12058587                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 208124                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               22290402                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           992604792                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1804097397                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1109074070                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               286                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             961885827                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 30718963                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             460377                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         463475                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  38191150                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17040621                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10018939                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1267546                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1072117                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  825695768                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1151715                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 820812543                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            215202                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        22450912                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33825927                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         141995                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     462004671                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.776633                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.399879                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            461962620                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.185486                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.916367                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 23051751                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             281963390                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 147749616                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               8311246                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 886617                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              834090099                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                 886617                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 26334343                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               229948938                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       14545958                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 152100341                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              38146423                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              830806639                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                454355                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               12555277                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 214921                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               22219847                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           992487524                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1803840100                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1108929979                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               295                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             961885153                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 30602369                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             460175                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         463946                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  42648824                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17020536                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10013615                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1265948                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1065839                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  825617137                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1152647                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 820744592                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            214843                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        22370068                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33775079                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         142908                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     461962620                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.776647                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.400230                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           278825933     60.35%     60.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13663917      2.96%     63.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             9689323      2.10%     65.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6980180      1.51%     66.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            74150960     16.05%     82.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4285873      0.93%     83.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72643996     15.72%     99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1183653      0.26%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              580836      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           278779319     60.35%     60.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            13677385      2.96%     63.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             9694463      2.10%     65.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7479161      1.62%     67.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            73155086     15.84%     82.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4780135      1.03%     83.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72637826     15.72%     99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1181137      0.26%     99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              578108      0.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       462004671                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       461962620                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1923038     72.06%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     72.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 586062     21.96%     94.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                159510      5.98%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2412123     76.39%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 586072     18.56%     94.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                159607      5.05%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            284391      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             792925473     96.60%     96.64% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               149981      0.02%     96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                126333      0.02%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            284241      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             792878234     96.60%     96.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               149840      0.02%     96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                126459      0.02%     96.67% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.67% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                  89      0.00%     96.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                  91      0.00%     96.67% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.67% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.67% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.67% # Type of FU issued
@@ -473,96 +473,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.67% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.67% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.67% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.67% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             18051798      2.20%     98.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9274478      1.13%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             18033989      2.20%     98.87% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9271738      1.13%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              820812543                       # Type of FU issued
-system.cpu.iq.rate                           1.763151                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2668610                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.003251                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2106513130                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         849310448                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    816528938                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 438                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                438                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          154                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              823196553                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     209                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1863533                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              820744592                       # Type of FU issued
+system.cpu.iq.rate                           1.763188                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3157802                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.003847                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2106824012                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         849151947                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    816471101                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 436                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                450                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          156                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              823617942                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     211                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1861954                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3085538                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        14402                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13954                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1597584                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3065804                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        14153                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14111                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1593948                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2095829                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         68627                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      2095806                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         68873                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 887417                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               206161533                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              15636111                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           826847483                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            165160                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17040642                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10018939                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             682638                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 383814                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              14427518                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13954                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         477334                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       506558                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               983892                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             819301527                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              17680087                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1386795                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 886617                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               206103955                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              15659492                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           826769784                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            162986                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17020536                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10013615                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             683525                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 383471                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              14451239                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14111                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         476576                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       506351                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               982927                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             819239221                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              17663851                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1381012                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     26745143                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 82994335                       # Number of branches executed
-system.cpu.iew.exec_stores                    9065056                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.759905                       # Inst execution rate
-system.cpu.iew.wb_sent                      818828086                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     816529092                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 638693519                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1046716801                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.753950                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.610188                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        22326581                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1009720                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            855503                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    458638769                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.753878                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.647523                       # Number of insts commited each cycle
+system.cpu.iew.exec_refs                     26724913                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 82983667                       # Number of branches executed
+system.cpu.iew.exec_stores                    9061062                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.759954                       # Inst execution rate
+system.cpu.iew.wb_sent                      818769187                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     816471257                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 638649867                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1046653125                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.754008                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.610183                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        22245724                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1009739                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            854697                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    458607756                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.754004                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.647518                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    288181414     62.83%     62.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11088145      2.42%     65.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3640328      0.79%     66.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74471829     16.24%     82.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2429591      0.53%     82.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1624239      0.35%     83.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1000805      0.22%     83.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     70851455     15.45%     98.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5350963      1.17%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    288145143     62.83%     62.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11087272      2.42%     65.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3640468      0.79%     66.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74478879     16.24%     82.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2430107      0.53%     82.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1625402      0.35%     83.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1001040      0.22%     83.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     70854372     15.45%     98.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5345073      1.17%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    458638769                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            406949634                       # Number of instructions committed
-system.cpu.commit.committedOps              804396566                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    458607756                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            406947274                       # Number of instructions committed
+system.cpu.commit.committedOps              804399711                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22376458                       # Number of memory references committed
-system.cpu.commit.loads                      13955103                       # Number of loads committed
-system.cpu.commit.membars                      448031                       # Number of memory barriers committed
-system.cpu.commit.branches                   82000860                       # Number of branches committed
+system.cpu.commit.refs                       22374398                       # Number of memory references committed
+system.cpu.commit.loads                      13954731                       # Number of loads committed
+system.cpu.commit.membars                      448033                       # Number of memory barriers committed
+system.cpu.commit.branches                   81999646                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 733378889                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155590                       # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass       171811      0.02%      0.02% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        781584496     97.16%     97.19% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult          144575      0.02%     97.20% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv           121797      0.02%     97.22% # Class of committed instruction
+system.cpu.commit.int_insts                 733379682                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1155571                       # Number of function calls committed.
+system.cpu.commit.op_class_0::No_OpClass       171831      0.02%      0.02% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        781589650     97.16%     97.19% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult          144528      0.02%     97.20% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv           121874      0.02%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
@@ -589,231 +589,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        13952516      1.73%     98.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite        8421355      1.05%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        13952145      1.73%     98.95% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite        8419667      1.05%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         804396566                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5350963                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1279932650                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1656830555                       # The number of ROB writes
-system.cpu.timesIdled                          287928                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         3532567                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9839087291                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   406949634                       # Number of Instructions Simulated
-system.cpu.committedOps                     804396566                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.143968                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.143968                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.874151                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.874151                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1088094227                       # number of integer regfile reads
-system.cpu.int_regfile_writes               653527011                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       154                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 414885669                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                320973068                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               264298420                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 400155                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1656768                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.992170                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18961019                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1657280                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.441047                       # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total         804399711                       # Class of committed instruction
+system.cpu.commit.bw_lim_events               5345073                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1279829790                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1656663443                       # The number of ROB writes
+system.cpu.timesIdled                          287506                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         3526413                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9823058000                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   406947274                       # Number of Instructions Simulated
+system.cpu.committedOps                     804399711                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               1.143856                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.143856                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.874236                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.874236                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1088022059                       # number of integer regfile reads
+system.cpu.int_regfile_writes               653481018                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       156                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 414844045                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                320950754                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               264261421                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 400173                       # number of misc regfile writes
+system.cpu.dcache.tags.replacements           1656014                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.995636                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18946459                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1656526                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.437466                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          65644500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.992170                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999985                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999985                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.995636                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999991                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999991                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          190                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          229                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          87666283                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         87666283                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10818711                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10818711                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8076378                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8076378                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        63033                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         63033                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      18895089                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18895089                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18958122                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18958122                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1802383                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1802383                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       335313                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       335313                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       406423                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       406423                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      2137696                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2137696                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2544119                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2544119                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  30109912500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  30109912500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21130469723                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21130469723                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  51240382223                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  51240382223                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  51240382223                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  51240382223                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     12621094                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     12621094                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8411691                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8411691                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       469456                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       469456                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21032785                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21032785                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21502241                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21502241                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142807                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.142807                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039863                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.039863                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.865732                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.865732                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.101636                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.101636                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.118319                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.118319                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16705.612792                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16705.612792                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63017.150313                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 63017.150313                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23969.910700                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23969.910700                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20140.717562                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20140.717562                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       552645                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          87599396                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         87599396                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10805755                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10805755                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8075007                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8075007                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        62855                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         62855                       # number of SoftPFReq hits
+system.cpu.dcache.demand_hits::cpu.data      18880762                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18880762                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18943617                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18943617                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1800696                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1800696                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       334991                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       334991                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       406405                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       406405                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      2135687                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2135687                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2542092                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2542092                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  30137867500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  30137867500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21089945740                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21089945740                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  51227813240                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  51227813240                       # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::total  51227813240                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     12606451                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     12606451                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8409998                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8409998                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       469260                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       469260                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21016449                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21016449                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21485709                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21485709                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142839                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.142839                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039832                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.039832                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.866055                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.866055                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.101620                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.101620                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.118315                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.118315                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16736.788164                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16736.788164                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62956.753286                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62956.753286                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23986.573519                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23986.573519                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20151.832916                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20151.832916                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       556428                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             52313                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             52454                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.564200                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.607923                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1559051                       # number of writebacks
-system.cpu.dcache.writebacks::total           1559051                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       836185                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       836185                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44844                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        44844                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       881029                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       881029                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       881029                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       881029                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       966198                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       966198                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290469                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       290469                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402930                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       402930                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1256667                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1256667                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1659597                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1659597                       # number of overall MSHR misses
+system.cpu.dcache.writebacks::writebacks      1558074                       # number of writebacks
+system.cpu.dcache.writebacks::total           1558074                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       834885                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       834885                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44903                       # number of WriteReq MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       965811                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       965811                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290088                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       290088                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402915                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       402915                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1255899                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1255899                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1658814                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1658814                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       573460                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total       573460                       # number of ReadReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13902                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.WriteReq_mshr_uncacheable::total        13902                       # number of WriteReq MSHR uncacheable
-system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       587362                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total       587362                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14276500000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  14276500000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19191766223                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  19191766223                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6799993500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6799993500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33468266223                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  33468266223                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40268259723                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  40268259723                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  98146110500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  98146110500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2778958000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2778958000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100925068500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 100925068500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076554                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076554                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034532                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034532                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.858291                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.858291                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059748                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059748                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077183                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.077183                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14775.956895                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14775.956895                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66071.650410                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66071.650410                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16876.364381                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16876.364381                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26632.565527                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26632.565527                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24263.878353                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24263.878353                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171147.264848                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171147.264848                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199896.273917                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199896.273917                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171827.711871                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171827.711871                       # average overall mshr uncacheable latency
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13899                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total        13899                       # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       587359                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total       587359                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14288232000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  14288232000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19138141242                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19138141242                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6806565500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6806565500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33426373242                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  33426373242                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40232938742                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  40232938742                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  98114325000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  98114325000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2778681500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2778681500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100893006500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 100893006500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076612                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076612                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034493                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034493                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.858618                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.858618                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059758                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.059758                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077205                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.077205                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14794.024918                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14794.024918                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65973.570923                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65973.570923                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16893.303799                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16893.303799                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26615.494751                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26615.494751                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24254.038573                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24254.038573                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.837269                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.837269                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199919.526585                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199919.526585                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171774.002782                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171774.002782                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        70166                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    15.821895                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs       109067                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        70181                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.554082                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 199860126500                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.821895                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988868                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988868                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       431964                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       431964                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       109068                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       109068                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       109068                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       109068                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       109068                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       109068                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        71276                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        71276                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        71276                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        71276                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        71276                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        71276                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    917687000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    917687000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    917687000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    917687000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    917687000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    917687000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       180344                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       180344                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       180344                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       180344                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       180344                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       180344                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.395222                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.395222                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.395222                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.395222                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.395222                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.395222                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12875.119255                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12875.119255                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12875.119255                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12875.119255                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12875.119255                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12875.119255                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.replacements        76780                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    15.821773                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs       101894                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        76796                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.326814                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 199830391500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.821773                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988861                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988861                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses       437119                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       437119                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       101894                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       101894                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       101894                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       101894                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       101894                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       101894                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        77777                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        77777                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        77777                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        77777                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        77777                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        77777                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    965958500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    965958500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    965958500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    965958500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    965958500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    965958500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       179671                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       179671                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       179671                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       179671                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       179671                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       179671                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.432886                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.432886                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.432886                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.432886                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.432886                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.432886                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12419.590624                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12419.590624                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12419.590624                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12419.590624                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12419.590624                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12419.590624                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -822,183 +822,182 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        21382                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        21382                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        71276                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        71276                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        71276                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        71276                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        71276                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        71276                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    846411000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    846411000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    846411000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    846411000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    846411000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    846411000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.395222                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.395222                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.395222                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.395222                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.395222                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.395222                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11875.119255                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11875.119255                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11875.119255                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11875.119255                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11875.119255                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11875.119255                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        21553                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        21553                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        77777                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        77777                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        77777                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        77777                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        77777                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        77777                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    888181500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    888181500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    888181500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    888181500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    888181500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    888181500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.432886                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.432886                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.432886                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.432886                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.432886                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.432886                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11419.590624                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11419.590624                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11419.590624                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            977252                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.169999                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7899773                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            977764                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              8.079427                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      150383300500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.169999                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994473                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994473                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            981325                       # number of replacements
+system.cpu.icache.tags.tagsinuse           508.752321                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7876209                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            981837                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              8.021911                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      150355632500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   508.752321                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.993657                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.993657                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          286                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          293                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          131                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses           9921559                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses          9921559                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7899773                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7899773                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7899773                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7899773                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7899773                       # number of overall hits
-system.cpu.icache.overall_hits::total         7899773                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1043950                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1043950                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1043950                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1043950                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1043950                       # number of overall misses
-system.cpu.icache.overall_misses::total       1043950                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15700851982                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15700851982                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15700851982                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15700851982                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15700851982                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15700851982                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8943723                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8943723                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8943723                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8943723                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8943723                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8943723                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116724                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.116724                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.116724                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.116724                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.116724                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.116724                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15039.850550                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15039.850550                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15039.850550                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15039.850550                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15039.850550                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15039.850550                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        15298                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          183                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               490                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    31.220408                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    91.500000                       # average number of cycles each access was blocked
+system.cpu.icache.tags.tag_accesses           9906588                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses          9906588                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7876209                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7876209                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7876209                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7876209                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7876209                       # number of overall hits
+system.cpu.icache.overall_hits::total         7876209                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1048476                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1048476                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1048476                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1048476                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1048476                       # number of overall misses
+system.cpu.icache.overall_misses::total       1048476                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  15750091989                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  15750091989                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  15750091989                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  15750091989                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  15750091989                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  15750091989                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8924685                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8924685                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8924685                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8924685                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8924685                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8924685                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.117480                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.117480                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.117480                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.117480                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.117480                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.117480                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15021.890810                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15021.890810                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15021.890810                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15021.890810                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15021.890810                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15021.890810                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        14497                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          291                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               495                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    29.286869                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    72.750000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       977252                       # number of writebacks
-system.cpu.icache.writebacks::total            977252                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        66114                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        66114                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        66114                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        66114                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        66114                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        66114                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       977836                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       977836                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       977836                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       977836                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       977836                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       977836                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13829997488                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  13829997488                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13829997488                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  13829997488                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13829997488                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  13829997488                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109332                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109332                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109332                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.109332                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109332                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.109332                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14143.473433                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14143.473433                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14143.473433                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14143.473433                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14143.473433                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14143.473433                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       981325                       # number of writebacks
+system.cpu.icache.writebacks::total            981325                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        66573                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        66573                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        66573                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        66573                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        66573                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        66573                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981903                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       981903                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       981903                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       981903                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       981903                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       981903                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13872010992                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  13872010992                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13872010992                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  13872010992                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13872010992                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  13872010992                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.110021                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.110021                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.110021                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.110021                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.110021                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.110021                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14127.679610                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14127.679610                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14127.679610                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14127.679610                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14127.679610                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14127.679610                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements        13555                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.033283                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        24087                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs        13571                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     1.774888                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5119783334000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.033283                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.377080                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.377080                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.replacements        13612                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     6.021123                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        25352                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs        13625                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     1.860697                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5116302133500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.021123                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376320                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.376320                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        91500                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        91500                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        24085                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        24085                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        94236                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        94236                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        25363                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        25363                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        24087                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        24087                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        24087                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        24087                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14442                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        14442                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14442                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        14442                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14442                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        14442                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    176053500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    176053500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    176053500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    176053500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    176053500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    176053500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        38527                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        38527                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        25365                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        25365                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        25365                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        25365                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14502                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        14502                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14502                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        14502                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14502                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        14502                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    176957500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    176957500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    176957500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    176957500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    176957500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    176957500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        39865                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        39865                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        38529                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        38529                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        38529                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        38529                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.374854                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.374854                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.374835                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.374835                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.374835                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.374835                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12190.382219                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12190.382219                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12190.382219                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12190.382219                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12190.382219                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12190.382219                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        39867                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        39867                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        39867                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        39867                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.363778                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.363778                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.363760                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.363760                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.363760                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.363760                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12202.282444                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12202.282444                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12202.282444                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12202.282444                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12202.282444                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12202.282444                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1007,187 +1006,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         2646                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         2646                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14442                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14442                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14442                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        14442                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14442                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        14442                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    161611500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    161611500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    161611500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    161611500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    161611500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    161611500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.374854                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.374854                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.374835                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.374835                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.374835                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.374835                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11190.382219                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11190.382219                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11190.382219                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11190.382219                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11190.382219                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11190.382219                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         2767                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         2767                       # number of writebacks
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+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14502                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14502                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        14502                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14502                       # number of overall MSHR misses
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+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    162455500                       # number of ReadReq MSHR miss cycles
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+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    162455500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    162455500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    162455500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.363778                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.363778                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.363760                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.363760                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.363760                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.363760                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11202.282444                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11202.282444                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11202.282444                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11202.282444                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11202.282444                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11202.282444                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           111866                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64806.585136                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4895184                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           176146                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            27.790492                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           112087                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64799.238973                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4898447                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           176177                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            27.804123                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50665.331172                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    16.461611                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.139358                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3133.879154                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10990.773840                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.773092                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000251                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50590.672109                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    12.620858                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.139554                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3112.121923                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11083.684529                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.771952                       # Average percentage of cache occupancy
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 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047819                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.167706                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.988870                       # Average percentage of cache occupancy
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          693                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3370                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6095                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54078                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.980835                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43505464                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43505464                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      1583079                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      1583079                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       976106                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       976106                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          322                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          322                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       155501                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       155501                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       961509                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       961509                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        64508                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        12006                       # number of ReadSharedReq hits
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-system.cpu.l2cache.demand_hits::cpu.itb.walker        12006                       # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.dtb.walker        64508                       # number of overall hits
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-system.cpu.l2cache.overall_hits::total        2526207                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1468                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1468                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       132819                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       132819                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16187                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        16187                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           64                       # number of ReadSharedReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047487                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.169124                       # Average percentage of cache occupancy
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53982                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.977936                       # Percentage of cache occupancy per task id
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+system.cpu.l2cache.WritebackDirty_hits::total      1582394                       # number of WritebackDirty hits
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 system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
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-system.cpu.l2cache.WritebackDirty_accesses::total      1583079                       # number of WritebackDirty accesses(hits+misses)
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-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64572                       # number of overall (read+write) accesses
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-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.820112                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.820112                       # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadExReq_miss_rate::total     0.460665                       # miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016556                       # miss rate for ReadCleanReq accesses
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-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024749                       # miss rate for ReadSharedReq accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016556                       # miss rate for demand accesses
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-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41155.653951                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41155.653951                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127896.046499                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127896.046499                       # average ReadExReq miss latency
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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134278.958423                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 144554.687500                       # average ReadSharedReq miss latency
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-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134516.740446                       # average ReadSharedReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129298.363312                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 129740.086163                       # average overall miss latency
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+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 142983.333333                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134921.352870                       # average ReadSharedReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 142983.333333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       135800                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134043.842822                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129316.860983                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 129735.492420                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 142983.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       135800                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134043.842822                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129316.860983                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 129735.492420                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1196,189 +1195,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       102439                       # number of writebacks
-system.cpu.l2cache.writebacks::total           102439                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       102517                       # number of writebacks
+system.cpu.l2cache.writebacks::total           102517                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            2                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total            2                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            1                       # number of ReadSharedReq MSHR hits
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 system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
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 system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            9                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            9                       # number of CleanEvict MSHR misses
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 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35690                       # number of ReadSharedReq MSHR misses
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 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
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 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
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 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       573460                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total       573460                       # number of ReadReq MSHR uncacheable
-system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13902                       # number of WriteReq MSHR uncacheable
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-system.cpu.l2cache.overall_mshr_uncacheable_misses::total       587362                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    104998500                       # number of UpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15658835000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15658835000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2011501500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2011501500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      8611500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       615000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4444509500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4453736000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8611500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       615000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2011501500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20103344500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  22124072500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8611500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       615000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2011501500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20103344500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  22124072500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90977820000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90977820000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2619013000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2619013000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  93596833000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  93596833000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13899                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13899                       # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       587359                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total       587359                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    102774999                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    102774999                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15611567500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15611567500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2004346500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2004346500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      7979000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       629000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4468306500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4476914500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      7979000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       629000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2004346500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20079874000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  22092828500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      7979000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       629000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2004346500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20079874000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  22092828500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90946019500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90946019500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2618766000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2618766000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  93564785500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  93564785500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.820112                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.820112                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.460665                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.460665                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016553                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016553                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000991                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000416                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026082                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024747                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000991                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000416                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016553                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101714                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.068153                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000991                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000416                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016553                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101714                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.068153                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71524.863760                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71524.863760                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117896.046499                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117896.046499                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124289.514335                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124289.514335                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 134554.687500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124530.947044                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124548.673061                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 134554.687500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124289.514335                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119301.310316                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119743.629642                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 134554.687500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124289.514335                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119301.310316                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119743.629642                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158647.194225                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158647.194225                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188391.094807                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188391.094807                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159351.188875                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159351.188875                       # average overall mshr uncacheable latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.807865                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.807865                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.460198                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.460198                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016457                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016457                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000897                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000413                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026140                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024758                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000897                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000413                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016457                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101620                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.067914                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000897                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000413                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016457                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101620                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.067914                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71470.792072                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71470.792072                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117804.480045                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117804.480045                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124054.372718                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124054.372718                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker       125800                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124952.642617                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124966.210747                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       125800                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124054.372718                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119323.476804                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119742.380883                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       125800                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124054.372718                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119323.476804                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119742.380883                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.740488                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.740488                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188413.986618                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188413.986618                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159297.440747                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159297.440747                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5440904                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2708527                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        66581                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1244                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1244                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5460741                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2718937                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        72407                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1221                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1221                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq         573460                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3006380                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13902                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13902                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      1732191                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       976106                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       117351                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2287                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2287                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       288332                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       288332                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       977836                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1455618                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::MessageReq         1647                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError            4                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3016607                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13899                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13899                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      1731587                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       980190                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       117679                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2259                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2259                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       287973                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       287973                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       981903                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1461779                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq         1645                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError            9                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2931638                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6148755                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        31077                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       165763                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           9277233                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    125043328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207521115                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       938048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5501056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          339003547                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      219501                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3519248                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.019893                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.161869                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2943868                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6146532                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        31429                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       174582                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           9296411                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    125565760                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207412623                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       951488                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5659456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          339589327                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      223808                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3529303                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.021448                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.165576                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3461036     98.35%     98.35% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              46415      1.32%     99.66% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              11797      0.34%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3464951     98.18%     98.18% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              53009      1.50%     99.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              11343      0.32%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3519248                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5581428473                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3529303                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5594725985                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       673784                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       671790                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1468574841                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1474740212                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3067922715                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3066745270                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      21677471                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      21763478                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     106983360                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     116728873                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq               212021                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              212021                       # Transaction distribution
+system.iobus.trans_dist::ReadReq               212016                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              212016                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57726                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              57726                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1647                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1647                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1645                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1645                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
@@ -1392,17 +1390,16 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio         2308                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       444236                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95258                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95258                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3294                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  542788                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95248                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95248                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3290                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3290                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  542774                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
@@ -1416,97 +1413,95 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio         4477                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       228398                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027816                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027816                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6588                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6588                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  3262802                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              3986144                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027776                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027776                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6580                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  3262754                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              3980596                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                43000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                42500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 6500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy             10452000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy             10514500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy               146500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy              1031500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy              1029000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy                92000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                94000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                59000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                58500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                32500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy                32500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy            300003000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            300003000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy              1175500                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy             1174500                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              212500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy              212500                       # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy            24561500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy            24568000                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           241121329                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           241169809                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy             1231500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy             1085500                       # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy           433230000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            50170000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            50160000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1647000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1645000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47574                       # number of replacements
-system.iocache.tags.tagsinuse                0.140717                       # Cycle average of tags in use
+system.iocache.tags.replacements                47569                       # number of replacements
+system.iocache.tags.tagsinuse                0.116025                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47585                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4999394542000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.140717                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008795                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.008795                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4999365177000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.116025                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007252                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.007252                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428661                       # Number of tag accesses
-system.iocache.tags.data_accesses              428661                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428616                       # Number of tag accesses
+system.iocache.tags.data_accesses              428616                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          909                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               909                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          909                       # number of overall misses
-system.iocache.overall_misses::total              909                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    147582673                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    147582673                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   6073068136                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   6073068136                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    147582673                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    147582673                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    147582673                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    147582673                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide          904                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               904                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          904                       # number of overall misses
+system.iocache.overall_misses::total              904                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    145501183                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    145501183                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   6077027146                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   6077027146                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    145501183                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    145501183                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    145501183                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    145501183                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          909                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             909                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          909                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            909                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          904                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             904                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          904                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            904                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -1515,40 +1510,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162357.176018                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 162357.176018                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129988.615925                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 129988.615925                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162357.176018                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 162357.176018                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162357.176018                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 162357.176018                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           921                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160952.636062                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 160952.636062                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 130073.355009                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130073.355009                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 160952.636062                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 160952.636062                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 160952.636062                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 160952.636062                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs          1232                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                  104                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                  114                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.855769                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.807018                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          909                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          909                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          904                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          904                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          909                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          909                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          909                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          909                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    102132673                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    102132673                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3737068136                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3737068136                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    102132673                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total    102132673                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    102132673                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total    102132673                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          904                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          904                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          904                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          904                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    100301183                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    100301183                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3741027146                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3741027146                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    100301183                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total    100301183                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    100301183                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total    100301183                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1557,81 +1552,81 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 112357.176018                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 112357.176018                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79988.615925                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79988.615925                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 112357.176018                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 112357.176018                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 112357.176018                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 112357.176018                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 110952.636062                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 80073.355009                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80073.355009                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 110952.636062                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 110952.636062                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq              573460                       # Transaction distribution
-system.membus.trans_dist::ReadResp             626308                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13902                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13902                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       149106                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             9689                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2235                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1738                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            132555                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           132549                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         52852                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1647                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1647                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            4                       # Transaction distribution
+system.membus.trans_dist::ReadResp             626337                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13899                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13899                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       149184                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             9829                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2188                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1709                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            132252                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           132250                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         52886                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1645                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1645                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            9                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3294                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3294                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3290                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3290                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       444236                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       730488                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       484041                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio            8                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1658773                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141815                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141815                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1803882                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6588                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6588                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       730482                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       483648                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           18                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1658384                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141810                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141810                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1803484                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6580                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       228398                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1460973                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18320640                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20010011                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1460961                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18308608                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     19997967                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                23031639                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             1655                       # Total snoops (count)
-system.membus.snoop_fanout::samples            982723                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.001676                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.040904                       # Request fanout histogram
+system.membus.pkt_size::total                23019587                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                             1629                       # Total snoops (count)
+system.membus.snoop_fanout::samples            982619                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.001674                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.040881                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  981076     99.83%     99.83% # Request fanout histogram
-system.membus.snoop_fanout::2                    1647      0.17%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  980974     99.83%     99.83% # Request fanout histogram
+system.membus.snoop_fanout::2                    1645      0.17%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total              982723                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           338949500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              982619                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           339006500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           369068500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           369115500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3985856                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3980404                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1013663510                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1013900787                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                5500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy               12000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            2338856                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            2335404                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2140705292                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2139201818                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           85841188                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           85763851                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
index dff91b228..5dc544b59 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
@@ -29,7 +29,7 @@ Built 1 zonelists.  Total pages: 30610
 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

 Initializing CPU#0

 PID hash table entries: 512 (order: 9, 4096 bytes)

-time.c: Detected 2000.000 MHz processor.

+time.c: Detected 2000.001 MHz processor.

 Console: colour dummy device 80x25

 console handover: boot [earlyser0] -> real [ttyS0]

 Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)

@@ -46,7 +46,7 @@ ACPI: Core revision 20070126
 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]

 ACPI: Unable to load the System Description Tables

 Using local APIC timer interrupts.

-result 7812528

+result 7812523

 Detected 7.812 MHz APIC timer.

 NET: Registered protocol family 16

 PCI: Using configuration type 1

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
index d7ee3e6f6..bf97d6d87 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
@@ -28,8 +28,9 @@ mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
+multi_thread=false
 num_work_ids=16
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -139,6 +140,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -155,6 +157,7 @@ system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=false
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
@@ -189,6 +192,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -205,6 +209,7 @@ system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 write_buffers=8
+writeback_clean=true
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
@@ -267,7 +272,7 @@ dtb=system.cpu1.dtb
 eventq_index=0
 function_trace=false
 function_trace_start=0
-interrupts=Null
+interrupts=
 isa=system.cpu1.isa
 itb=system.cpu1.itb
 max_insts_all_threads=0
@@ -363,7 +368,7 @@ iewToCommitDelay=1
 iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
-interrupts=Null
+interrupts=
 isa=system.cpu2.isa
 issueToExecuteDelay=1
 issueWidth=8
@@ -1215,8 +1220,8 @@ frontend_latency=2
 response_latency=2
 use_default_range=false
 width=16
-default=system.pc.pciconfig.pio
-master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+default=system.pc.pci_host.pio
+master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
@@ -1225,6 +1230,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
@@ -1241,7 +1247,8 @@ system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
-cpu_side=system.iobus.master[19]
+writeback_clean=false
+cpu_side=system.iobus.master[18]
 mem_side=system.membus.slave[4]
 
 [system.iocache.tags]
@@ -1260,6 +1267,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
 demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
@@ -1276,6 +1284,7 @@ system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
 write_buffers=8
+writeback_clean=false
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
@@ -1326,7 +1335,7 @@ pio=system.membus.default
 
 [system.pc]
 type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -1347,7 +1356,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[13]
+pio=system.iobus.master[12]
 
 [system.pc.com_1]
 type=Uart8250
@@ -1359,7 +1368,7 @@ pio_latency=100000
 platform=system.pc
 system=system
 terminal=system.pc.com_1.terminal
-pio=system.iobus.master[14]
+pio=system.iobus.master[13]
 
 [system.pc.com_1.terminal]
 type=Terminal
@@ -1385,7 +1394,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[15]
+pio=system.iobus.master[14]
 
 [system.pc.fake_com_3]
 type=IsaFake
@@ -1403,7 +1412,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[16]
+pio=system.iobus.master[15]
 
 [system.pc.fake_com_4]
 type=IsaFake
@@ -1421,7 +1430,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[17]
+pio=system.iobus.master[16]
 
 [system.pc.fake_floppy]
 type=IsaFake
@@ -1439,7 +1448,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[18]
+pio=system.iobus.master[17]
 
 [system.pc.i_dont_exist1]
 type=IsaFake
@@ -1457,7 +1466,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[11]
+pio=system.iobus.master[10]
 
 [system.pc.i_dont_exist2]
 type=IsaFake
@@ -1475,17 +1484,19 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[12]
+pio=system.iobus.master[11]
 
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
+[system.pc.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=13835058055282163712
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=9223372036854775808
 platform=system.pc
-size=16777216
 system=system
 pio=system.iobus.default
 
@@ -1608,14 +1619,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
 eventq_index=0
+host=system.pc.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=4
 pci_func=0
 pio_latency=30000
-platform=system.pc
 system=system
-config=system.iobus.master[4]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[3]
 
@@ -1639,7 +1649,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/work/gem5/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1662,7 +1672,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1767,7 +1777,7 @@ pio_addr=4273995776
 pio_latency=100000
 system=system
 int_master=system.iobus.slave[2]
-pio=system.iobus.master[10]
+pio=system.iobus.master[9]
 
 [system.pc.south_bridge.keyboard]
 type=I8042
@@ -1781,7 +1791,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
 pio_addr=0
 pio_latency=100000
 system=system
-pio=system.iobus.master[5]
+pio=system.iobus.master[4]
 
 [system.pc.south_bridge.keyboard.keyboard_int_pin]
 type=X86IntSourcePin
@@ -1802,7 +1812,7 @@ pio_addr=9223372036854775840
 pio_latency=100000
 slave=system.pc.south_bridge.pic2
 system=system
-pio=system.iobus.master[6]
+pio=system.iobus.master[5]
 
 [system.pc.south_bridge.pic1.output]
 type=X86IntSourcePin
@@ -1819,7 +1829,7 @@ pio_addr=9223372036854775968
 pio_latency=100000
 slave=Null
 system=system
-pio=system.iobus.master[7]
+pio=system.iobus.master[6]
 
 [system.pc.south_bridge.pic2.output]
 type=X86IntSourcePin
@@ -1834,7 +1844,7 @@ int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=100000
 system=system
-pio=system.iobus.master[8]
+pio=system.iobus.master[7]
 
 [system.pc.south_bridge.pit.int_pin]
 type=X86IntSourcePin
@@ -1848,7 +1858,7 @@ i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=100000
 system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[8]
 
 [system.physmem]
 type=DRAMCtrl
@@ -1952,12 +1962,13 @@ version=
 
 [system.toL2Bus]
 type=CoherentXBar
+children=snoop_filter
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 forward_latency=0
 frontend_latency=1
 response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
 snoop_response_latency=1
 system=system
 use_default_range=false
@@ -1965,6 +1976,13 @@ width=32
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
 [system.voltage_domain]
 type=VoltageDomain
 eventq_index=0
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
index 6cc193075..aed66fce8 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
@@ -2,7 +2,7 @@
     "name": null, 
     "sim_quantum": 0, 
     "system": {
-        "kernel": "/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9", 
+        "kernel": "/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9", 
         "mmap_using_noreserve": false, 
         "kernel_addr_check": true, 
         "bridge": {
@@ -40,7 +40,7 @@
             }, 
             "name": "iobus", 
             "default": {
-                "peer": "system.pc.pciconfig.pio", 
+                "peer": "system.pc.pci_host.pio", 
                 "role": "MASTER"
             }, 
             "forward_latency": 1, 
@@ -53,7 +53,6 @@
                     "system.pc.south_bridge.cmos.pio", 
                     "system.pc.south_bridge.dma1.pio", 
                     "system.pc.south_bridge.ide.pio", 
-                    "system.pc.south_bridge.ide.config", 
                     "system.pc.south_bridge.keyboard.pio", 
                     "system.pc.south_bridge.pic1.pio", 
                     "system.pc.south_bridge.pic2.pio", 
@@ -107,6 +106,7 @@
                 "peer": "system.toL2Bus.master[0]", 
                 "role": "SLAVE"
             }, 
+            "clusivity": "mostly_incl", 
             "prefetcher": null, 
             "clk_domain": "system.cpu_clk_domain", 
             "write_buffers": 8, 
@@ -133,11 +133,12 @@
                 "peer": "system.membus.slave[2]", 
                 "role": "MASTER"
             }, 
-            "mshrs": 20, 
+            "type": "Cache", 
             "forward_snoops": true, 
+            "writeback_clean": false, 
             "hit_latency": 20, 
-            "demand_mshr_reserve": 1, 
             "tgts_per_mshr": 12, 
+            "demand_mshr_reserve": 1, 
             "addr_ranges": [
                 "0:18446744073709551615"
             ], 
@@ -145,11 +146,11 @@
             "prefetch_on_access": false, 
             "path": "system.l2c", 
             "name": "l2c", 
-            "type": "Cache", 
+            "mshrs": 20, 
             "sequential_access": false, 
             "assoc": 8
         }, 
-        "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh", 
+        "readfile": "/work/gem5/outgoing/gem5_2/tests/halt.sh", 
         "intel_mp_table": {
             "oem_table_addr": 0, 
             "name": "intel_mp_table", 
@@ -631,9 +632,10 @@
         "load_offset": 0, 
         "iocache": {
             "cpu_side": {
-                "peer": "system.iobus.master[19]", 
+                "peer": "system.iobus.master[18]", 
                 "role": "SLAVE"
             }, 
+            "clusivity": "mostly_incl", 
             "prefetcher": null, 
             "clk_domain": "system.clk_domain", 
             "write_buffers": 8, 
@@ -660,11 +662,12 @@
                 "peer": "system.membus.slave[4]", 
                 "role": "MASTER"
             }, 
-            "mshrs": 20, 
+            "type": "Cache", 
             "forward_snoops": false, 
+            "writeback_clean": false, 
             "hit_latency": 50, 
-            "demand_mshr_reserve": 1, 
             "tgts_per_mshr": 12, 
+            "demand_mshr_reserve": 1, 
             "addr_ranges": [
                 "0:134217727"
             ], 
@@ -672,7 +675,7 @@
             "prefetch_on_access": false, 
             "path": "system.iocache", 
             "name": "iocache", 
-            "type": "Cache", 
+            "mshrs": 20, 
             "sequential_access": false, 
             "assoc": 8
         }, 
@@ -798,7 +801,7 @@
                 "name": "fake_com_4", 
                 "warn_access": "", 
                 "pio": {
-                    "peer": "system.iobus.master[17]", 
+                    "peer": "system.iobus.master[16]", 
                     "role": "SLAVE"
                 }, 
                 "ret_bad_addr": false, 
@@ -816,31 +819,13 @@
                 "type": "IsaFake", 
                 "ret_data16": 65535
             }, 
-            "pciconfig": {
-                "name": "pciconfig", 
-                "pio": {
-                    "peer": "system.iobus.default", 
-                    "role": "SLAVE"
-                }, 
-                "bus": 0, 
-                "pio_latency": 30000, 
-                "clk_domain": "system.clk_domain", 
-                "system": "system", 
-                "platform": "system.pc", 
-                "eventq_index": 0, 
-                "cxx_class": "PciConfigAll", 
-                "path": "system.pc.pciconfig", 
-                "pio_addr": 0, 
-                "type": "PciConfigAll", 
-                "size": 16777216
-            }, 
             "fake_com_2": {
                 "system": "system", 
                 "ret_data8": 255, 
                 "name": "fake_com_2", 
                 "warn_access": "", 
                 "pio": {
-                    "peer": "system.iobus.master[15]", 
+                    "peer": "system.iobus.master[14]", 
                     "role": "SLAVE"
                 }, 
                 "ret_bad_addr": false, 
@@ -985,7 +970,7 @@
                 "speaker": {
                     "name": "speaker", 
                     "pio": {
-                        "peer": "system.iobus.master[9]", 
+                        "peer": "system.iobus.master[8]", 
                         "role": "SLAVE"
                     }, 
                     "pio_latency": 100000, 
@@ -1003,7 +988,7 @@
                     "command_port": 9223372036854775908, 
                     "name": "keyboard", 
                     "pio": {
-                        "peer": "system.iobus.master[5]", 
+                        "peer": "system.iobus.master[4]", 
                         "role": "SLAVE"
                     }, 
                     "mouse_int_pin": {
@@ -1032,7 +1017,7 @@
                 "pit": {
                     "name": "pit", 
                     "pio": {
-                        "peer": "system.iobus.master[8]", 
+                        "peer": "system.iobus.master[7]", 
                         "role": "SLAVE"
                     }, 
                     "pio_latency": 100000, 
@@ -1058,7 +1043,7 @@
                     }, 
                     "name": "io_apic", 
                     "pio": {
-                        "peer": "system.iobus.master[10]", 
+                        "peer": "system.iobus.master[9]", 
                         "role": "SLAVE"
                     }, 
                     "pio_latency": 100000, 
@@ -1084,7 +1069,7 @@
                         "cxx_class": "X86ISA::IntSourcePin"
                     }, 
                     "pio": {
-                        "peer": "system.iobus.master[6]", 
+                        "peer": "system.iobus.master[5]", 
                         "role": "SLAVE"
                     }, 
                     "pio_latency": 100000, 
@@ -1108,7 +1093,7 @@
                         "cxx_class": "X86ISA::IntSourcePin"
                     }, 
                     "pio": {
-                        "peer": "system.iobus.master[7]", 
+                        "peer": "system.iobus.master[6]", 
                         "role": "SLAVE"
                     }, 
                     "pio_latency": 100000, 
@@ -1151,7 +1136,6 @@
                     "Revision": 0, 
                     "LegacyIOBase": 9223372036854775808, 
                     "pio_latency": 30000, 
-                    "platform": "system.pc", 
                     "PXCAPLinkCap": 0, 
                     "CapabilityPtr": 0, 
                     "MSIXCAPBaseOffset": 0, 
@@ -1183,7 +1167,7 @@
                                     "eventq_index": 0, 
                                     "cxx_class": "RawDiskImage", 
                                     "path": "system.pc.south_bridge.ide.disks0.image.child", 
-                                    "image_file": "/scratch/nilay/GEM5/system/disks/linux-x86.img", 
+                                    "image_file": "/work/gem5/dist/disks/linux-x86.img", 
                                     "type": "RawDiskImage"
                                 }, 
                                 "path": "system.pc.south_bridge.ide.disks0.image", 
@@ -1211,7 +1195,7 @@
                                     "eventq_index": 0, 
                                     "cxx_class": "RawDiskImage", 
                                     "path": "system.pc.south_bridge.ide.disks1.image.child", 
-                                    "image_file": "/scratch/nilay/GEM5/system/disks/linux-bigswap2.img", 
+                                    "image_file": "/work/gem5/dist/disks/linux-bigswap2.img", 
                                     "type": "RawDiskImage"
                                 }, 
                                 "path": "system.pc.south_bridge.ide.disks1.image", 
@@ -1242,6 +1226,7 @@
                     "PXCAPDevCap2": 0, 
                     "PXCAPDevCtrl": 0, 
                     "MSICAPMaskBits": 0, 
+                    "host": "system.pc.pci_host", 
                     "Command": 0, 
                     "SubClassCode": 1, 
                     "pci_func": 0, 
@@ -1285,10 +1270,6 @@
                     "clk_domain": "system.clk_domain", 
                     "SubsystemVendorID": 0, 
                     "PMCAPBaseOffset": 0, 
-                    "config": {
-                        "peer": "system.iobus.master[4]", 
-                        "role": "SLAVE"
-                    }, 
                     "MSICAPPendingBits": 0, 
                     "MSIXTableOffset": 0, 
                     "MSICAPMsgUpperAddr": 0, 
@@ -1330,7 +1311,7 @@
                 "name": "fake_floppy", 
                 "warn_access": "", 
                 "pio": {
-                    "peer": "system.iobus.master[18]", 
+                    "peer": "system.iobus.master[17]", 
                     "role": "SLAVE"
                 }, 
                 "ret_bad_addr": false, 
@@ -1354,7 +1335,7 @@
                 "name": "i_dont_exist2", 
                 "warn_access": "", 
                 "pio": {
-                    "peer": "system.iobus.master[12]", 
+                    "peer": "system.iobus.master[11]", 
                     "role": "SLAVE"
                 }, 
                 "ret_bad_addr": false, 
@@ -1379,7 +1360,7 @@
                 "name": "i_dont_exist1", 
                 "warn_access": "", 
                 "pio": {
-                    "peer": "system.iobus.master[11]", 
+                    "peer": "system.iobus.master[10]", 
                     "role": "SLAVE"
                 }, 
                 "ret_bad_addr": false, 
@@ -1401,7 +1382,7 @@
             "com_1": {
                 "name": "com_1", 
                 "pio": {
-                    "peer": "system.iobus.master[14]", 
+                    "peer": "system.iobus.master[13]", 
                     "role": "SLAVE"
                 }, 
                 "pio_latency": 100000, 
@@ -1425,6 +1406,26 @@
                 "pio_addr": 9223372036854776824, 
                 "type": "Uart8250"
             }, 
+            "pci_host": {
+                "conf_size": 16777216, 
+                "name": "pci_host", 
+                "conf_device_bits": 8, 
+                "pio": {
+                    "peer": "system.iobus.default", 
+                    "role": "SLAVE"
+                }, 
+                "conf_base": 13835058055282163712, 
+                "clk_domain": "system.clk_domain", 
+                "system": "system", 
+                "pci_dma_base": 0, 
+                "platform": "system.pc", 
+                "eventq_index": 0, 
+                "cxx_class": "GenericPciHost", 
+                "path": "system.pc.pci_host", 
+                "pci_pio_base": 9223372036854775808, 
+                "type": "GenericPciHost", 
+                "pci_mem_base": 0
+            }, 
             "eventq_index": 0, 
             "cxx_class": "Pc", 
             "path": "system.pc", 
@@ -1434,7 +1435,7 @@
                 "name": "behind_pci", 
                 "warn_access": "", 
                 "pio": {
-                    "peer": "system.iobus.master[13]", 
+                    "peer": "system.iobus.master[12]", 
                     "role": "SLAVE"
                 }, 
                 "ret_bad_addr": false, 
@@ -1459,7 +1460,7 @@
                 "name": "fake_com_3", 
                 "warn_access": "", 
                 "pio": {
-                    "peer": "system.iobus.master[16]", 
+                    "peer": "system.iobus.master[15]", 
                     "role": "SLAVE"
                 }, 
                 "ret_bad_addr": false, 
@@ -1704,7 +1705,16 @@
                 "role": "SLAVE"
             }, 
             "name": "toL2Bus", 
-            "snoop_filter": null, 
+            "snoop_filter": {
+                "name": "snoop_filter", 
+                "system": "system", 
+                "max_capacity": 8388608, 
+                "eventq_index": 0, 
+                "cxx_class": "SnoopFilter", 
+                "path": "system.toL2Bus.snoop_filter", 
+                "type": "SnoopFilter", 
+                "lookup_latency": 0
+            }, 
             "forward_latency": 0, 
             "clk_domain": "system.cpu_clk_domain", 
             "system": "system", 
@@ -1793,6 +1803,7 @@
                         "peer": "system.cpu0.icache_port", 
                         "role": "SLAVE"
                     }, 
+                    "clusivity": "mostly_incl", 
                     "prefetcher": null, 
                     "clk_domain": "system.cpu_clk_domain", 
                     "write_buffers": 8, 
@@ -1819,11 +1830,12 @@
                         "peer": "system.toL2Bus.slave[0]", 
                         "role": "MASTER"
                     }, 
-                    "mshrs": 4, 
+                    "type": "Cache", 
                     "forward_snoops": true, 
+                    "writeback_clean": true, 
                     "hit_latency": 2, 
-                    "demand_mshr_reserve": 1, 
                     "tgts_per_mshr": 20, 
+                    "demand_mshr_reserve": 1, 
                     "addr_ranges": [
                         "0:18446744073709551615"
                     ], 
@@ -1831,34 +1843,36 @@
                     "prefetch_on_access": false, 
                     "path": "system.cpu0.icache", 
                     "name": "icache", 
-                    "type": "Cache", 
+                    "mshrs": 4, 
                     "sequential_access": false, 
                     "assoc": 1
                 }, 
-                "interrupts": {
-                    "int_master": {
-                        "peer": "system.membus.slave[3]", 
-                        "role": "MASTER"
-                    }, 
-                    "name": "interrupts", 
-                    "pio": {
-                        "peer": "system.membus.master[1]", 
-                        "role": "SLAVE"
-                    }, 
-                    "int_slave": {
-                        "peer": "system.membus.master[2]", 
-                        "role": "SLAVE"
-                    }, 
-                    "pio_latency": 100000, 
-                    "clk_domain": "system.cpu0.apic_clk_domain", 
-                    "system": "system", 
-                    "int_latency": 1000, 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::Interrupts", 
-                    "path": "system.cpu0.interrupts", 
-                    "pio_addr": 2305843009213693952, 
-                    "type": "X86LocalApic"
-                }, 
+                "interrupts": [
+                    {
+                        "int_master": {
+                            "peer": "system.membus.slave[3]", 
+                            "role": "MASTER"
+                        }, 
+                        "name": "interrupts", 
+                        "pio": {
+                            "peer": "system.membus.master[1]", 
+                            "role": "SLAVE"
+                        }, 
+                        "int_slave": {
+                            "peer": "system.membus.master[2]", 
+                            "role": "SLAVE"
+                        }, 
+                        "pio_latency": 100000, 
+                        "clk_domain": "system.cpu0.apic_clk_domain", 
+                        "system": "system", 
+                        "int_latency": 1000, 
+                        "eventq_index": 0, 
+                        "cxx_class": "X86ISA::Interrupts", 
+                        "path": "system.cpu0.interrupts", 
+                        "pio_addr": 2305843009213693952, 
+                        "type": "X86LocalApic"
+                    }
+                ], 
                 "dcache_port": {
                     "peer": "system.cpu0.dcache.cpu_side", 
                     "role": "MASTER"
@@ -1902,6 +1916,7 @@
                         "peer": "system.cpu0.dcache_port", 
                         "role": "SLAVE"
                     }, 
+                    "clusivity": "mostly_incl", 
                     "prefetcher": null, 
                     "clk_domain": "system.cpu_clk_domain", 
                     "write_buffers": 8, 
@@ -1928,11 +1943,12 @@
                         "peer": "system.toL2Bus.slave[1]", 
                         "role": "MASTER"
                     }, 
-                    "mshrs": 4, 
+                    "type": "Cache", 
                     "forward_snoops": true, 
+                    "writeback_clean": false, 
                     "hit_latency": 2, 
-                    "demand_mshr_reserve": 1, 
                     "tgts_per_mshr": 20, 
+                    "demand_mshr_reserve": 1, 
                     "addr_ranges": [
                         "0:18446744073709551615"
                     ], 
@@ -1940,7 +1956,7 @@
                     "prefetch_on_access": false, 
                     "path": "system.cpu0.dcache", 
                     "name": "dcache", 
-                    "type": "Cache", 
+                    "mshrs": 4, 
                     "sequential_access": false, 
                     "assoc": 4
                 }, 
@@ -1995,7 +2011,7 @@
                 "do_quiesce": true, 
                 "type": "TimingSimpleCPU", 
                 "profile": 0, 
-                "interrupts": null, 
+                "interrupts": [], 
                 "socket_id": 0, 
                 "max_insts_all_threads": 0, 
                 "path": "system.cpu1", 
@@ -2593,7 +2609,7 @@
                 "eventq_index": 0, 
                 "type": "DerivO3CPU", 
                 "wbWidth": 8, 
-                "interrupts": null, 
+                "interrupts": [], 
                 "smtCommitPolicy": "RoundRobin", 
                 "issueToExecuteDelay": 1, 
                 "dtb": {
@@ -2644,6 +2660,7 @@
             "path": "system.intrctrl", 
             "type": "IntrControl"
         }, 
+        "multi_thread": false, 
         "work_begin_ckpt_count": 0, 
         "work_begin_cpu_id_exit": -1, 
         "work_item_id": -1, 
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
index fb8fdc7fa..30a665fe2 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
@@ -3,17 +3,9 @@ warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
 warn: Reading current count from inactive timer.
 warn: Don't know what interrupt to clear for console.
-warn: x86 cpuid: unknown family 0xbacc
-warn: x86 cpuid: unknown family 0xbacc
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: x86 cpuid: unknown family 0x8086
 warn: x86 cpuid: unknown family 0x8086
-warn: x86 cpuid: unknown family 0x8086
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -25,17 +17,7 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 7191, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 9400, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -43,33 +25,31 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6675, Bank: 2
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 6996, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 12287, Bank: 1
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6767, Bank: 1
+Command: 0, Timestamp: 6448, Bank: 4
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6921, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11289, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7232, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11338, Bank: 4
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+Command: 0, Timestamp: 7603, Bank: 3
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10369, Bank: 4
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9709, Bank: 5
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7701, Bank: 2
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11369, Bank: 1
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -89,17 +69,19 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: Tried to clear PCI interrupt 14
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8909, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6789, Bank: 3
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8215, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8557, Bank: 5
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11226, Bank: 4
 warn: Unknown mouse command 0xe1.
 warn: instruction 'wbinvd' unimplemented
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7075, Bank: 7
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 6474, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6837, Bank: 6
+Command: 0, Timestamp: 7944, Bank: 0
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
index 88f772da2..73370e2b3 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  6 2015 14:29:04
-gem5 started Jul  7 2015 09:32:35
-gem5 executing on e104799-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
+gem5 compiled Dec  4 2015 15:10:31
+gem5 started Dec  4 2015 16:03:32
+gem5 executing on e104799-lin, pid 2775
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
 
 Global frequency set at 1000000000000 ticks per second
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index cc30b102c..df59304a0 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -1,145 +1,145 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.140310                       # Number of seconds simulated
-sim_ticks                                5140310077000                       # Number of ticks simulated
-final_tick                               5140310077000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.142345                       # Number of seconds simulated
+sim_ticks                                5142345332000                       # Number of ticks simulated
+final_tick                               5142345332000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 193642                       # Simulator instruction rate (inst/s)
-host_op_rate                                   384932                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4095276555                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1038092                       # Number of bytes of host memory used
-host_seconds                                  1255.18                       # Real time elapsed on the host
-sim_insts                                   243055842                       # Number of instructions simulated
-sim_ops                                     483158927                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 328643                       # Simulator instruction rate (inst/s)
+host_op_rate                                   653294                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6944434004                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 993680                       # Number of bytes of host memory used
+host_seconds                                   740.50                       # Real time elapsed on the host
+sim_insts                                   243359937                       # Number of instructions simulated
+sim_ops                                     483763631                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           444160                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5333440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           157504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1822656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         2112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           355968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          3200064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           463872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5043712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           148160                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2254656                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         2176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           338432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          3039936                       # Number of bytes read from this memory
 system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11344576                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       444160                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       157504                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       355968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          957632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9154432                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9154432                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             11319616                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       463872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       148160                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       338432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          950464                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9139904                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9139904                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6940                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             83335                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2461                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             28479                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           33                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5562                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             50001                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              7248                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             78808                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2315                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             35229                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           34                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5288                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             47499                       # Number of read requests responded to by this memory
 system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                177259                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          143038                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143038                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                176869                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          142811                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142811                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               86407                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1037572                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               30641                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              354581                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           411                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               69250                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              622543                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5516                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2206983                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          86407                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          30641                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          69250                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             186298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1780910                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1780910                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1780910                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               90206                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              980819                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               28812                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              438449                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           423                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               65813                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              591157                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide         5513                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2201256                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          90206                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          28812                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          65813                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             184831                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1777380                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1777380                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1777380                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              86407                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1037572                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              30641                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             354581                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          411                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              69250                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             622543                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5516                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3987893                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         86979                       # Number of read requests accepted
-system.physmem.writeReqs                        83143                       # Number of write requests accepted
-system.physmem.readBursts                       86979                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      83143                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5559296                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5321152                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5566656                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5321152                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu0.inst              90206                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             980819                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              28812                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             438449                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          423                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              65813                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             591157                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide         5513                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3978636                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         90808                       # Number of read requests accepted
+system.physmem.writeReqs                        80864                       # Number of write requests accepted
+system.physmem.readBursts                       90808                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      80864                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  5799936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     11776                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5173504                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   5811712                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5175296                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      184                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          33940                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                5203                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4657                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5413                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5303                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5134                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                4786                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5593                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5448                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5260                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                4897                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5208                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5207                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5484                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6574                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6603                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6094                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5594                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5124                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                5270                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4838                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5433                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5211                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5102                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5101                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5096                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5186                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5320                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5088                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4612                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5353                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5452                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          28946                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                5471                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                4964                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5622                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                5619                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5375                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                4811                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5429                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                5659                       # Per bank write bursts
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+system.physmem.perBankRdBursts::9                5234                       # Per bank write bursts
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+system.physmem.perBankRdBursts::11               5583                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               6015                       # Per bank write bursts
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+system.physmem.perBankWrBursts::0                5328                       # Per bank write bursts
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+system.physmem.perBankWrBursts::15               5718                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5136428721000                       # Total gap between requests
+system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5141345197000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   86979                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   90808                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  83143                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     81214                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4352                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       808                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       172                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        44                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        38                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  80864                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     85390                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4130                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       610                       # What read queue length does an incoming req see
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+system.physmem.rdQLenPdf::4                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        40                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        42                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        26                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        26                       # What read queue length does an incoming req see
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 system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                       24                       # What read queue length does an incoming req see
@@ -161,1117 +161,1109 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       122                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1825                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::18                     4013                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4467                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4472                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24                     5576                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5555                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     6628                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4990                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4540                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::30                     4281                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::32                     4008                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::37                       82                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::39                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       69                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::42                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       83                       # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::45                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        39730                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      273.859753                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     164.661250                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     301.445638                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          16103     40.53%     40.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         9824     24.73%     65.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4113     10.35%     75.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2266      5.70%     81.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1547      3.89%     85.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1072      2.70%     87.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          721      1.81%     89.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          578      1.45%     91.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3506      8.82%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          39730                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4019                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.613337                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      232.441160                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            4016     99.93%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::0                       123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        64                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        5                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        40174                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      273.144621                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     165.560811                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     297.725081                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16113     40.11%     40.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         9912     24.67%     64.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4303     10.71%     75.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2413      6.01%     81.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1642      4.09%     85.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1065      2.65%     88.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          735      1.83%     90.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          648      1.61%     91.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3343      8.32%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          40174                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4096                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.121094                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      231.669266                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            4094     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1536-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4019                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4019                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.687484                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.141176                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.818199                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                66      1.64%      1.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 4      0.10%      1.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                1      0.02%      1.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               5      0.12%      1.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            3291     81.89%     83.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             104      2.59%     86.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              32      0.80%     87.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             108      2.69%     89.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              15      0.37%     90.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             105      2.61%     92.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              59      1.47%     94.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               4      0.10%     94.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              14      0.35%     94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              20      0.50%     95.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               2      0.05%     95.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               4      0.10%     95.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             144      3.58%     98.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               4      0.10%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              15      0.37%     99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               1      0.02%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             3      0.07%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            10      0.25%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.05%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4019                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1059562475                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2688262475                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    434320000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12197.95                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4096                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4096                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.735352                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.630791                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.122766                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                68      1.66%      1.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 3      0.07%      1.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                1      0.02%      1.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15               5      0.12%      1.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            3465     84.59%     86.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              91      2.22%     88.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              32      0.78%     89.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             114      2.78%     92.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              13      0.32%     92.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              74      1.81%     94.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              48      1.17%     95.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               3      0.07%     95.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              13      0.32%     95.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              10      0.24%     96.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               7      0.17%     96.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               2      0.05%     96.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             111      2.71%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.10%     99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               2      0.05%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              16      0.39%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.02%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             3      0.07%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             6      0.15%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4096                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1084591495                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2783791495                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    453120000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11968.04                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30947.95                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.08                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.04                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.08                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.04                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30718.04                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.13                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.01                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.13                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        1.01                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.23                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         6.40                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      68770                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     61507                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.17                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.98                       # Row buffer hit rate for writes
-system.physmem.avgGap                     30192618.95                       # Average gap between requests
-system.physmem.pageHitRate                      76.63                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  145673640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   79307250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 323988600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                270041040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           250383413280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            96324881400                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2240107908000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             2587635213210                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.890753                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   3686018034728                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    128007880000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         7.79                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      72353                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     58932                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   79.84                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  72.88                       # Row buffer hit rate for writes
+system.physmem.avgGap                     29948653.23                       # Average gap between requests
+system.physmem.pageHitRate                      76.56                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  144214560                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   78573000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 335010000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                259511040                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           250484108160                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            96378538635                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2237986517250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             2585666472645                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              667.978665                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   3687486057488                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    128059360000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     19864390272                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     19884905262                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  154685160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   84187125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 353550600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                268725600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           250383413280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            96580278450                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2233317414750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             2581142254965                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.102097                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   3685663172228                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    128007880000                       # Time in different power states
+system.physmem_1.actEnergy                  159500880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   86876625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 371841600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                264306240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           250484108160                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            97163933940                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2232534954750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             2581065522195                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.160201                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   3686335779224                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    128059360000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     20186348022                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     21009267026                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                      1072285093                       # number of cpu cycles simulated
+system.cpu0.numCycles                      1088115959                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.committedInsts                   71949472                       # Number of instructions committed
-system.cpu0.committedOps                    146629560                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            134558000                       # Number of integer alu accesses
+system.cpu0.committedInsts                   71651877                       # Number of instructions committed
+system.cpu0.committedOps                    146177129                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            134125177                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     963710                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14252688                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   134558000                       # number of integer instructions
+system.cpu0.num_func_calls                     958449                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14231951                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   134125177                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          246915381                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         115616486                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          245781224                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         115362346                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            83804950                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           55920138                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13826864                       # number of memory refs
-system.cpu0.num_load_insts                   10217566                       # Number of load instructions
-system.cpu0.num_store_insts                   3609298                       # Number of store instructions
-system.cpu0.num_idle_cycles              1017808343.518800                       # Number of idle cycles
-system.cpu0.num_busy_cycles              54476749.481200                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.050804                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.949196                       # Percentage of idle cycles
-system.cpu0.Branches                         15573120                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                93861      0.06%      0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu                132602488     90.43%     90.50% # Class of executed instruction
-system.cpu0.op_class::IntMult                   58992      0.04%     90.54% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    49734      0.03%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.57% # Class of executed instruction
-system.cpu0.op_class::MemRead                10215736      6.97%     97.54% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3609298      2.46%    100.00% # Class of executed instruction
+system.cpu0.num_cc_register_reads            83627387                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           55829285                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     13623500                       # number of memory refs
+system.cpu0.num_load_insts                   10168797                       # Number of load instructions
+system.cpu0.num_store_insts                   3454703                       # Number of store instructions
+system.cpu0.num_idle_cycles              1031530406.657702                       # Number of idle cycles
+system.cpu0.num_busy_cycles              56585552.342298                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.052003                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.947997                       # Percentage of idle cycles
+system.cpu0.Branches                         15545637                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                91075      0.06%      0.06% # Class of executed instruction
+system.cpu0.op_class::IntAlu                132356346     90.54%     90.61% # Class of executed instruction
+system.cpu0.op_class::IntMult                   58823      0.04%     90.65% # Class of executed instruction
+system.cpu0.op_class::IntDiv                    49650      0.03%     90.68% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.68% # Class of executed instruction
+system.cpu0.op_class::MemRead                10166974      6.96%     97.64% # Class of executed instruction
+system.cpu0.op_class::MemWrite                3454703      2.36%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 146630109                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          1637608                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999082                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19599059                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1638120                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            11.964361                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 146177571                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          1639042                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999458                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19611882                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1639554                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            11.961718                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.195835                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   211.604713                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   116.198534                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.359757                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.413290                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.226950                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999998                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   186.987910                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   208.755532                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   116.256017                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.365211                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.407726                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.227063                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          241                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          250                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          215                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          279                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88196204                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88196204                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4977443                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2399002                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4079601                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11456046                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3466928                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1632244                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2982379                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8081551                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        21705                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data         9720                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        28160                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        59585                       # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8444371                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      4031246                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      7061980                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19537597                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8466076                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      4040966                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      7090140                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19597182                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       370514                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       153427                       # number of ReadReq misses
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-system.cpu0.dcache.ReadReq_misses::total      1309224                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       138238                       # number of WriteReq misses
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-system.cpu0.dcache.WriteReq_misses::cpu2.data       133227                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       326642                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       157440                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        58723                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       190307                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       406470                       # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       508752                       # number of demand (read+write) misses
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-system.cpu0.dcache.demand_misses::total       1635866                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       666192                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       267327                       # number of overall misses
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-system.cpu0.dcache.overall_misses::total      2042336                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2248261000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  12713989500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  14962250500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   3673730495                       # number of WriteReq miss cycles
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-system.cpu0.dcache.WriteReq_miss_latency::total  10240166896                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   5921991495                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  19280425901                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  25202417396                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   5921991495                       # number of overall miss cycles
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-system.cpu0.dcache.overall_miss_latency::total  25202417396                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5347957                       # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.069281                       # miss rate for ReadReq accesses
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-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11428.335029                       # average ReadReq miss latency
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-system.cpu0.dcache.WriteReq_avg_miss_latency::total 31349.816913                       # average WriteReq miss latency
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-system.cpu0.dcache.overall_avg_miss_latency::total 12339.995670                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       206528                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         88233009                       # Number of tag accesses
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+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.872209                       # miss rate for SoftPFReq accesses
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+system.cpu0.dcache.demand_miss_rate::total     0.077044                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.072367                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.062226                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.135756                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.094156                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14636.049432                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15454.252662                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 11012.176924                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 71630.650827                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46535.015996                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 33719.129553                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31092.269510                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20108.799812                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 15555.401269                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24526.938944                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 16629.584434                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12454.429611                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       209532                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            21989                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            22224                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.392333                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.428186                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1548069                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1548069                       # number of writebacks
+system.cpu0.dcache.writebacks::writebacks      1549010                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1549010                       # number of writebacks
 system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           70                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       363845                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       363915                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1660                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        33563                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        35223                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         1730                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       397408                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       399138                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         1730                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       397408                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       399138                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       153357                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       421438                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       574795                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        53517                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        99664                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       153181                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58722                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       186898                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       245620                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       206874                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       521102                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       727976                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       265596                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       708000                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       973596                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       176326                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       193522                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total       369848                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3494                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         2876                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         6370                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       179820                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       196398                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total       376218                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2091939500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   6052493500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8144433000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   3446784995                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5707366401                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9154151396                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   1012257500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2960769500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3973027000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   5538724495                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  11759859901                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  17298584396                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   6550981995                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  14720629401                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  21271611396                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30675451000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  32998770000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63674221000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    673827500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    612008500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1285836000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31349278500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33610778500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64960057000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.060083                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086629                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045028                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.031715                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031989                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018218                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.857969                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.855498                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.527019                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.048793                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.065297                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.034382                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061648                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.086352                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.044992                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13640.978240                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14361.527674                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14169.282962                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64405.422483                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57266.078032                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59760.357982                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17238.130513                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15841.632869                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16175.502809                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26773.420029                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22567.289899                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23762.575134                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24665.213313                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20791.849436                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21848.499168                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173970.095165                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170516.892136                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172163.215699                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192852.747567                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212798.504868                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201858.084772                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174336.995329                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171136.052811                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172665.999500                       # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       358190                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       358260                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1746                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        33668                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        35414                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data         1816                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       391858                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       393674                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data         1816                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       391858                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       393674                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       158773                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       421604                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       580377                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        62735                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       103680                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       166415                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        59778                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       188477                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       248255                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       221508                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       525284                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       746792                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       281286                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       713761                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       995047                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       176153                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       193877                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total       370030                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         3295                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         3452                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total         6747                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       179448                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       197329                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total       376777                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2163130500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5958622500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   8121753000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   4375430996                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5531064377                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9906495373                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   1034307500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2977676500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   4011984000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   6538561496                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  11489686877                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  18028248373                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7572868996                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  14467363377                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  22040232373                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30638632000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33033633500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63672265500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    639710000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    711714500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1351424500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31278342000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33745348000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65023690000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.059966                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.087419                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.045438                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034238                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.033163                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019789                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.859324                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.856344                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.532877                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.049443                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.066080                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.035255                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.061827                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087372                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.045964                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13624.045020                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14133.220985                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13993.926362                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 69744.656029                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53347.457340                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59528.860818                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17302.477500                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15798.619991                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16160.737951                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 29518.398866                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21873.285455                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24140.923273                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26922.310374                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20269.198481                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22149.941031                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173931.934171                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170384.488619                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172073.252169                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 194145.675266                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 206174.536501                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200300.059286                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174303.096162                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171010.586381                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172578.713669                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           862096                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.743965                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          129388053                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           862608                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           149.996352                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle     149036221500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   146.474426                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   126.886783                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   237.382757                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.286083                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.247826                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.463638                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997547                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           863213                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.772348                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          129563028                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           863725                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           150.004953                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle     149035233500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   148.852314                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   120.504208                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   241.415826                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.290727                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.235360                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.471515                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997602                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          152                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          277                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          277                       # Occupied blocks per task id
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 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        131137351                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       131137351                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     87656735                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     38708289                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      3023029                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      129388053                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     87656735                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     38708289                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      3023029                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       129388053                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     87656735                       # number of overall hits
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-system.cpu0.icache.overall_hits::total      129388053                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       322601                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       163645                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       400432                       # number of ReadReq misses
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-system.cpu0.icache.demand_misses::total        886678                       # number of demand (read+write) misses
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-system.cpu0.icache.overall_misses::total       886678                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2424283000                       # number of ReadReq miss cycles
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-system.cpu0.icache.ReadReq_miss_latency::total   8368282964                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2424283000                       # number of demand (read+write) miss cycles
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-system.cpu0.icache.demand_miss_latency::total   8368282964                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2424283000                       # number of overall miss cycles
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-system.cpu0.icache.overall_miss_latency::total   8368282964                       # number of overall miss cycles
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-system.cpu0.icache.overall_accesses::total    130274731                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003667                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004210                       # miss rate for ReadReq accesses
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-system.cpu0.icache.ReadReq_miss_rate::total     0.006806                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003667                       # miss rate for demand accesses
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-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003667                       # miss rate for overall accesses
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-system.cpu0.icache.overall_miss_rate::total     0.006806                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14814.280913                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14843.968424                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  9437.792484                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14814.280913                       # average overall miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total  9437.792484                       # average overall miss latency
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-system.cpu0.icache.overall_avg_miss_latency::total  9437.792484                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        12787                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        131315867                       # Number of tag accesses
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+system.cpu0.icache.ReadReq_avg_miss_latency::total  9647.457678                       # average ReadReq miss latency
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+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14673.286006                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  9647.457678                       # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::total  9647.457678                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        13598                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              569                       # number of cycles access was blocked
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 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    22.472759                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.731239                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks       862096                       # number of writebacks
-system.cpu0.icache.writebacks::total           862096                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        24058                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        24058                       # number of ReadReq MSHR hits
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-system.cpu0.icache.demand_mshr_hits::total        24058                       # number of demand (read+write) MSHR hits
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-system.cpu0.icache.overall_mshr_hits::total        24058                       # number of overall MSHR hits
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-system.cpu0.icache.ReadReq_mshr_misses::total       540019                       # number of ReadReq MSHR misses
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-system.cpu0.icache.overall_mshr_misses::total       540019                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2260638000                       # number of ReadReq MSHR miss cycles
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-system.cpu0.icache.ReadReq_mshr_miss_latency::total   7514424466                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2260638000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5253786466                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   7514424466                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2260638000                       # number of overall MSHR miss cycles
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-system.cpu0.icache.overall_mshr_miss_latency::total   7514424466                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004210                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.109940                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004145                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004210                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.109940                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004145                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004210                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.109940                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004145                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13814.280913                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13958.951644                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13915.111257                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13814.280913                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13958.951644                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13915.111257                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13814.280913                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13958.951644                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13915.111257                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       863213                       # number of writebacks
+system.cpu0.icache.writebacks::total           863213                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        25359                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        25359                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        25359                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        25359                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        25359                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        25359                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       169918                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       389608                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       559526                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       169918                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       389608                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       559526                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       169918                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       389608                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       559526                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2318697500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5380005477                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   7698702977                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2318697500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5380005477                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   7698702977                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2318697500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5380005477                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   7698702977                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004307                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.114860                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004289                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004307                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.114860                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.004289                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004307                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.114860                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.004289                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13645.979237                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13808.765418                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13759.330178                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13645.979237                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13808.765418                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13759.330178                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13645.979237                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13808.765418                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13759.330178                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2606017773                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2608019031                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   35434857                       # Number of instructions committed
-system.cpu1.committedOps                     68967174                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             63950727                       # Number of integer alu accesses
+system.cpu1.committedInsts                   35872545                       # Number of instructions committed
+system.cpu1.committedOps                     69699402                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             64677814                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     471160                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6540311                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    63950727                       # number of integer instructions
+system.cpu1.num_func_calls                     478121                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6602854                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    64677814                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          118144335                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          55187205                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          119785728                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          55703367                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            36132607                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           26987111                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4484202                       # number of memory refs
-system.cpu1.num_load_insts                    2795233                       # Number of load instructions
-system.cpu1.num_store_insts                   1688969                       # Number of store instructions
-system.cpu1.num_idle_cycles              2475079638.158952                       # Number of idle cycles
-system.cpu1.num_busy_cycles              130938134.841048                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.050245                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.949755                       # Percentage of idle cycles
-system.cpu1.Branches                          7181922                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                31577      0.05%      0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 64399053     93.38%     93.42% # Class of executed instruction
-system.cpu1.op_class::IntMult                   30119      0.04%     93.47% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    23752      0.03%     93.50% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.50% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2793873      4.05%     97.55% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1688969      2.45%    100.00% # Class of executed instruction
+system.cpu1.num_cc_register_reads            36592003                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           27221835                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4725252                       # number of memory refs
+system.cpu1.num_load_insts                    2891470                       # Number of load instructions
+system.cpu1.num_store_insts                   1833782                       # Number of store instructions
+system.cpu1.num_idle_cycles              2475574417.457654                       # Number of idle cycles
+system.cpu1.num_busy_cycles              132444613.542345                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.050784                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.949216                       # Percentage of idle cycles
+system.cpu1.Branches                          7256649                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                36799      0.05%      0.05% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 64882747     93.09%     93.14% # Class of executed instruction
+system.cpu1.op_class::IntMult                   30615      0.04%     93.19% # Class of executed instruction
+system.cpu1.op_class::IntDiv                    25662      0.04%     93.22% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.22% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2890134      4.15%     97.37% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1833782      2.63%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  68967343                       # Class of executed instruction
-system.cpu2.branchPred.lookups               28923833                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         28923833                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           299320                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            26177104                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               25594852                       # Number of BTB hits
+system.cpu1.op_class::total                  69699739                       # Class of executed instruction
+system.cpu2.branchPred.lookups               28904699                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         28904699                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           301799                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26182960                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               25618019                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.775720                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 576883                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             63148                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       157005173                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            97.842333                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 577766                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             65377                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       157028917                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          10541640                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     142873863                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   28923833                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26171735                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    144747848                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 631807                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                    102981                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles               10810                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             7821                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        69710                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles           26                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles         1766                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3423471                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               155018                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   2920                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         155797854                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.805083                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.007319                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles          10756065                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     142934226                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   28904699                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26195785                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                    144559167                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 634442                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                    102497                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles               11445                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             9293                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        61170                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles           12                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles         1572                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3392030                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               159049                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   2822                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples         155817791                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.805701                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.007704                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0               100986987     64.82%     64.82% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  876917      0.56%     65.38% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23450339     15.05%     80.43% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  581596      0.37%     80.81% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  798015      0.51%     81.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  839359      0.54%     81.86% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  536249      0.34%     82.20% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  727748      0.47%     82.67% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27000644     17.33%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0               100969926     64.80%     64.80% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  864181      0.55%     65.35% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23515186     15.09%     80.45% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  574321      0.37%     80.81% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  784323      0.50%     81.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  832797      0.53%     81.85% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  526849      0.34%     82.19% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  721182      0.46%     82.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27029026     17.35%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           155797854                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.184222                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.909995                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 9166837                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             95859954                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 22256485                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              3994112                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                316555                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             278482972                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                316555                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                10781931                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               77376747                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       5125883                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 24368379                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             13624506                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             277324695                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents               194123                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               5339465                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 70652                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               6671965                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          331399724                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            605057293                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       371622887                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups              206                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            320041085                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                11358639                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            162877                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        164126                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 19798687                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6564509                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3714734                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           445796                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          396085                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 275510749                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             407738                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                273563069                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            95252                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        8356294                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     12697185                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         62746                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    155797854                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.755885                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.385565                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total           155817791                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.184072                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.910241                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 9372643                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             95636804                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 20963245                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              4000269                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                317872                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             278646605                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                317872                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                10991831                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               77276692                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       5181011                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 23079329                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles             13444163                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             277492076                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents               194116                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               5314185                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents                 68849                       # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents               6513408                       # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands          331462631                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            605120715                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       371802312                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups              234                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            320362920                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                11099709                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            163935                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        165202                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 19836823                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6505105                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3734190                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           446981                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          391369                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 275686580                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             411981                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                273842853                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            94839                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        8211456                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     12322633                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         64605                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples    155817791                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.757456                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.386043                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           93882941     60.26%     60.26% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            5118927      3.29%     63.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3721264      2.39%     65.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            3253797      2.09%     68.02% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           23197295     14.89%     82.91% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            2207034      1.42%     84.33% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           23724652     15.23%     99.56% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             467591      0.30%     99.86% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             224353      0.14%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           93841974     60.23%     60.23% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            5140662      3.30%     63.52% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3701702      2.38%     65.90% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            3241767      2.08%     67.98% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           23231728     14.91%     82.89% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            2206356      1.42%     84.31% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           23779364     15.26%     99.57% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             455294      0.29%     99.86% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8             218944      0.14%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      155797854                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total      155817791                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                1207723     81.78%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     81.78% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                207267     14.03%     95.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                61876      4.19%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                1209883     81.76%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     81.76% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                208644     14.10%     95.86% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                61248      4.14%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            77671      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            263072310     96.17%     96.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               56421      0.02%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                50248      0.02%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                 74      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.23% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             6863613      2.51%     98.74% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3442732      1.26%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            74059      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            263387979     96.18%     96.21% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               56208      0.02%     96.23% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                48343      0.02%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                104      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             6817856      2.49%     98.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3458304      1.26%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             273563069                       # Type of FU issued
-system.cpu2.iq.rate                          1.742383                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    1476866                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.005399                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         704495801                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        284279079                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    272064636                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                309                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes               294                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses          118                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             274962115                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                    149                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          723478                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             273842853                       # Type of FU issued
+system.cpu2.iq.rate                          1.743901                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    1479775                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.005404                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         705077754                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        284314372                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    272343231                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                356                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes               332                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses          144                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             275248392                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                    177                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          717023                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1134849                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         5659                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         5111                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       595348                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1119882                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         5658                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         5248                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       603569                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       712058                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        23525                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       712184                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        25029                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                316555                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               69932049                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              4483827                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          275918487                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            35063                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6564509                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3714734                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            243249                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                162438                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              4010481                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          5111                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        167096                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       181001                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              348097                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            273015158                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6728091                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           497866                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                317872                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles               69999671                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles              4334406                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          276098561                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            36227                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6505105                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3734190                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            245180                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                161697                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents              3862519                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          5248                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        168896                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       180792                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              349688                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            273296807                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              6682967                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           496833                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    10090158                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                27708578                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3362067                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.738893                       # Inst execution rate
-system.cpu2.iew.wb_sent                     272843265                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    272064754                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                212267822                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                348193993                       # num instructions consuming a value
-system.cpu2.iew.wb_rate                      1.732839                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.609625                       # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts        8353767                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         344992                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           303032                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    154549869                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.731235                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.636337                       # Number of insts commited each cycle
+system.cpu2.iew.exec_refs                    10058933                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                27720177                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3375966                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.740423                       # Inst execution rate
+system.cpu2.iew.wb_sent                     273120714                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    272343375                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                212424693                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                348436865                       # num instructions consuming a value
+system.cpu2.iew.wb_rate                      1.734352                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.609650                       # average fanout of values written-back
+system.cpu2.commit.commitSquashedInsts        8207919                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         347376                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           304652                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples    154587808                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.732912                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.636931                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     97453895     63.06%     63.06% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4255487      2.75%     65.81% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1275451      0.83%     66.64% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24388605     15.78%     82.42% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       953115      0.62%     83.03% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       708142      0.46%     83.49% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       433200      0.28%     83.77% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23018173     14.89%     98.66% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2063801      1.34%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     97422616     63.02%     63.02% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4263028      2.76%     65.78% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1258481      0.81%     66.59% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24441508     15.81%     82.40% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       948995      0.61%     83.02% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       702646      0.45%     83.47% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       422583      0.27%     83.75% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23085730     14.93%     98.68% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      2042221      1.32%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    154549869                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           135671513                       # Number of instructions committed
-system.cpu2.commit.committedOps             267562193                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total    154587808                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           135835515                       # Number of instructions committed
+system.cpu2.commit.committedOps             267887100                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8549046                       # Number of memory references committed
-system.cpu2.commit.loads                      5429660                       # Number of loads committed
-system.cpu2.commit.membars                     149565                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27339925                       # Number of branches committed
+system.cpu2.commit.refs                       8515843                       # Number of memory references committed
+system.cpu2.commit.loads                      5385222                       # Number of loads committed
+system.cpu2.commit.membars                     151391                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27354284                       # Number of branches committed
 system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                244518367                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              438140                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        46308      0.02%      0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       258864003     96.75%     96.77% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          54521      0.02%     96.79% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           48349      0.02%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        5429610      2.03%     98.83% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       3119386      1.17%    100.00% # Class of committed instruction
+system.cpu2.commit.int_insts                244770291                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              437535                       # Number of function calls committed.
+system.cpu2.commit.op_class_0::No_OpClass        44208      0.02%      0.02% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu       259226210     96.77%     96.78% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult          54262      0.02%     96.80% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv           46624      0.02%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult             0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     96.82% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead        5385159      2.01%     98.83% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite       3130621      1.17%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
 system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        267562193                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              2063801                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                   428372162                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  553085882                       # The number of ROB writes
-system.cpu2.timesIdled                         112358                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1207319                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4910585893                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  135671513                       # Number of Instructions Simulated
-system.cpu2.committedOps                    267562193                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.157245                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.157245                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.864121                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.864121                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               363757841                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              218039219                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    73086                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                138801079                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               106740366                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               88776769                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                143860                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq              3545348                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             3545348                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57726                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57726                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1644                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1644                       # Transaction distribution
+system.cpu2.commit.op_class_0::total        267887100                       # Class of committed instruction
+system.cpu2.commit.bw_lim_events              2042221                       # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads                   428611967                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  553425779                       # The number of ROB writes
+system.cpu2.timesIdled                         117856                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        1211126                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4911627157                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  135835515                       # Number of Instructions Simulated
+system.cpu2.committedOps                    267887100                       # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi                              1.156023                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.156023                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.865035                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.865035                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               364164831                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              218212592                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    73112                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   73024                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                138818129                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               106823368                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               88818544                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                142989                       # number of misc regfile writes
+system.iobus.trans_dist::ReadReq              3545369                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             3545369                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               57733                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              57733                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1667                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1667                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7066648                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7066646                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1182                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27866                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      7110880                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3288                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3288                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 7209436                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio         2308                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      7110938                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95266                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95266                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3334                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3334                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                 7209538                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3533324                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3533323                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2364                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13933                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      3561720                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027856                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027856                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6576                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  6596152                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2378420                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio         4477                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total      3561710                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027848                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027848                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6668                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6668                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  6596226                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy              2386632                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                41500                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy                41000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              5416500                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              6479000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                 8500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy               921000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy               921000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy                40500                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                40500                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                18000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy                21000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy            199976000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            199977500                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy               478500                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              507000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              170000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy            11026500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            11054500                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
+system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           117264991                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           144387481                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy             1060500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy             1052000                       # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           283491000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           284201000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            31080000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            25798000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy              979000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy              987000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47579                       # number of replacements
-system.iocache.tags.tagsinuse                0.099877                       # Cycle average of tags in use
+system.iocache.tags.replacements                47578                       # number of replacements
+system.iocache.tags.tagsinuse                0.106179                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47595                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47594                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5000697713509                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.099877                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006242                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.006242                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5000689447509                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.106179                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006636                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.006636                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428706                       # Number of tag accesses
-system.iocache.tags.data_accesses              428706                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          914                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              914                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428697                       # Number of tag accesses
+system.iocache.tags.data_accesses              428697                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          913                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              913                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide          914                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               914                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide          914                       # number of overall misses
-system.iocache.overall_misses::total              914                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    126880776                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    126880776                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   3631478705                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   3631478705                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide    126880776                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total    126880776                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide    126880776                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total    126880776                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          914                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            914                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide          913                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               913                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide          913                       # number of overall misses
+system.iocache.overall_misses::total              913                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    126475754                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    126475754                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   2945894237                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   2945894237                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide    126475754                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total    126475754                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide    126475754                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total    126475754                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          913                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            913                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide          914                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             914                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide          914                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            914                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide          913                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             913                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide          913                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            913                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
@@ -1280,327 +1272,327 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138819.229759                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 138819.229759                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 77728.568172                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 77728.568172                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138819.229759                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 138819.229759                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138819.229759                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 138819.229759                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           769                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138527.660460                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 138527.660460                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 63054.243086                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 63054.243086                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138527.660460                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 138527.660460                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138527.660460                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 138527.660460                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           657                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   71                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   59                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.830986                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.135593                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          756                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          756                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        27936                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        27936                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide          756                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          756                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide          756                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          756                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     89080776                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     89080776                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   2234678705                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2234678705                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     89080776                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     89080776                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     89080776                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     89080776                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.827133                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.827133                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.597945                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.597945                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.827133                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.827133                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.827133                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.827133                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 117831.714286                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79992.794423                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79992.794423                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 117831.714286                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 117831.714286                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          755                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          755                       # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        22656                       # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total        22656                       # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide          755                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          755                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide          755                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          755                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     88725754                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     88725754                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1813094237                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   1813094237                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     88725754                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     88725754                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     88725754                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     88725754                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.826944                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.826944                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.484932                       # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total     0.484932                       # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.826944                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.826944                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.826944                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.826944                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 117517.554967                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 80027.111450                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80027.111450                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 117517.554967                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 117517.554967                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   104623                       # number of replacements
-system.l2c.tags.tagsinuse                64807.193930                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4639141                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168699                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    27.499517                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   104233                       # number of replacements
+system.l2c.tags.tagsinuse                64807.184468                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4648895                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   168429                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    27.601512                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   51005.580247                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.135096                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1646.367272                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4933.030076                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      515.170725                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1886.196797                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker     9.248761                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst      884.127622                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     3927.337333                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.778283                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   50959.111320                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.136263                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1606.978228                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4944.954504                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      496.939087                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1891.921055                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker     9.257150                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst      951.270746                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     3946.616114                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.777574                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.025122                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.075272                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.007861                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.028781                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.024521                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.075454                       # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.data       0.028868                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000141                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.013491                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.059926                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.014515                       # Average percentage of cache occupancy
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 system.l2c.tags.occ_percent::total           0.988879                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64076                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          267                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2840                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6926                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        54004                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.977722                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 41427151                       # Number of tag accesses
-system.l2c.tags.data_accesses                41427151                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        20684                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        10937                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        10806                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5737                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        57444                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        12625                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 118233                       # number of ReadReq hits
+system.l2c.tags.occ_task_id_blocks::1024        64196                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          668                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3069                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5065                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55320                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.979553                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 41479817                       # Number of tag accesses
+system.l2c.tags.data_accesses                41479817                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        19668                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker        10402                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        11752                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         6500                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        59100                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker        12594                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 120016                       # number of ReadReq hits
 system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
 system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.WritebackDirty_hits::writebacks      1548069                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         1548069                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       861756                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          861756                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data             130                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              31                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data             115                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 276                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            69082                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            29187                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            61537                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               159806                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        315648                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        161184                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        370798                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            847630                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       512537                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       207468                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data       595557                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          1315562                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         20684                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         10939                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              315648                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              581619                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         10806                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5737                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              161184                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              236655                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         57444                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         12625                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              370798                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              657094                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2441233                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        20684                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        10939                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             315648                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             581619                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        10806                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5737                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             161184                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             236655                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        57444                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        12625                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             370798                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             657094                       # number of overall hits
-system.l2c.overall_hits::total                2441233                       # number of overall hits
+system.l2c.WritebackDirty_hits::writebacks      1549010                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total         1549010                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks       862717                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total          862717                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data              97                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              74                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data              95                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 266                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            60797                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            31555                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            67417                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               159769                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        296952                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        167603                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst        384294                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total            848849                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       505674                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       213822                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data       597828                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total          1317324                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         19668                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker         10404                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              296952                       # number of demand (read+write) hits
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 system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.820312                       # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 43274.834437                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 38302.857143                       # average UpgradeReq miss latency
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.822115                       # miss rate for UpgradeReq accesses
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1609,204 +1601,204 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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-system.l2c.writebacks::total                    96371                       # number of writebacks
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 system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
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-system.l2c.ReadReq_mshr_misses::total              33                       # number of ReadReq MSHR misses
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-system.l2c.overall_mshr_uncacheable_latency::total  60263663500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000574                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.000279                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.829670                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.820312                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.407474                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.452781                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.378885                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.212854                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.015039                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.014778                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.009301                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.021742                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.020926                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.012860                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.015039                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.108362                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000574                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014778                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.071063                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.033251                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.015039                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.108362                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000574                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014778                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.071063                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.033251                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 130272.727273                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 130272.727273                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70649.006623                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70805.714286                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70770.710059                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116170.600414                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119566.785657                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 118237.226041                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120352.905323                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126443.905070                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124575.532843                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121458.685751                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 127710.503575                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126048.039216                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120352.905323                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117018.392963                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 130272.727273                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126443.905070                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121629.001134                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 120381.005696                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120352.905323                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117018.392963                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 130272.727273                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126443.905070                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121629.001134                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 120381.005696                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161470.092329                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 158016.799124                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159663.165679                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181352.604465                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 201291.724618                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 190354.945055                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161856.420309                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158650.505606                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 160182.828839                       # average overall mshr uncacheable latency
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           34                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total              34                       # number of ReadReq MSHR misses
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+system.l2c.UpgradeReq_mshr_misses::total          809                       # number of UpgradeReq MSHR misses
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+system.l2c.demand_mshr_misses::total            91087                       # number of demand (read+write) MSHR misses
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+system.l2c.UpgradeReq_mshr_miss_latency::total     57281500                       # number of UpgradeReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28436719000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30610149000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  59046868000                       # number of ReadReq MSHR uncacheable cycles
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    671983500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1273800500                       # number of WriteReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::total  60320668500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000575                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.000283                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.822115                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.830961                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.479834                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.493670                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.346519                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.229774                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.013624                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.013573                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.008803                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.021638                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.020009                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.012544                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.013624                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.126374                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000575                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.013573                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.067239                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034722                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.013624                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.126374                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000575                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.013573                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.067239                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034722                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 137617.647059                       # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70937.901499                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70805.315204                       # average UpgradeReq mshr miss latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::total 160096.472184                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq             5063565                       # Transaction distribution
-system.membus.trans_dist::ReadResp            5112237                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13898                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13898                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       143038                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8555                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             1675                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1675                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            129715                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           129715                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         48672                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1644                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1644                       # Transaction distribution
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+system.membus.trans_dist::WriteReq              13928                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13928                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       142811                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             8387                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             1702                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1702                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            129429                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           129429                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         48569                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1667                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1667                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3288                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3288                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7110880                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3044046                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       462505                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total     10617431                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141987                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       141987                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               10762706                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3561720                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6088089                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17503808                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     27153617                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3334                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3334                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7110938                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3043868                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       461232                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total     10616038                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141982                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       141982                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               10761354                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6668                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total         6668                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3561710                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6087733                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17454144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     27103587                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3025152                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      3025152                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                30185345                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              665                       # Total snoops (count)
-system.membus.snoop_fanout::samples           5458032                       # Request fanout histogram
-system.membus.snoop_fanout::mean             1.000301                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.017353                       # Request fanout histogram
+system.membus.pkt_size::total                30135407                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                              824                       # Total snoops (count)
+system.membus.snoop_fanout::samples           5457240                       # Request fanout histogram
+system.membus.snoop_fanout::mean             1.000305                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.017475                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                 5456388     99.97%     99.97% # Request fanout histogram
-system.membus.snoop_fanout::2                    1644      0.03%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                 5455573     99.97%     99.97% # Request fanout histogram
+system.membus.snoop_fanout::2                    1667      0.03%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
-system.membus.snoop_fanout::total             5458032                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           219245500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             5457240                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           220305500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           286800000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           286836500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             2376580                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             2385368                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           547442853                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           534782231                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1397580                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1398368                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1208317879                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1230215238                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy           52360943                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy           43264654                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1820,60 +1812,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.snoop_filter.tot_requests      5045447                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2544703                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests          484                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1173                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1173                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5045999                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2542699                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests          716                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1209                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1209                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            5213999                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7425168                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13900                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13900                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      1631215                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean       861756                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           94957                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1659                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1659                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           289813                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          289813                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        862620                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1349075                       # Transaction distribution
-system.toL2Bus.trans_dist::MessageReq             979                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq        27936                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2586983                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15072215                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        70159                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       206201                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              17935558                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    110359232                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213581393                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       258600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       748792                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              324948017                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          226396                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          8918852                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.005051                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.070893                       # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq            5211020                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           7425092                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13930                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13930                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty      1629876                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean       862717                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           95523                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1686                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           1686                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           289480                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          289480                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq        863740                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1350844                       # Transaction distribution
+system.toL2Bus.trans_dist::MessageReq             987                       # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq        22656                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2590172                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15076396                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        68863                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       204307                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total              17939738                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    110491648                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    213734051                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       254408                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       750576                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              325230683                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          223463                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          8879878                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.004588                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.067577                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                8873800     99.49%     99.49% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  45052      0.51%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                8839140     99.54%     99.54% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  40738      0.46%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            8918852                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         3217820998                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            8879878                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         3300004999                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           406876                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           437354                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         810576399                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         839896281                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1832733252                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1865125250                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          23881478                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          24363482                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          87500568                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          87735122                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
index 898984ead..2e4dba06f 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
@@ -29,7 +29,7 @@ Built 1 zonelists.  Total pages: 30610
 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

 Initializing CPU#0

 PID hash table entries: 512 (order: 9, 4096 bytes)

-time.c: Detected 2000.005 MHz processor.

+time.c: Detected 2000.003 MHz processor.

 Console: colour dummy device 80x25

 console handover: boot [earlyser0] -> real [ttyS0]

 Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)

@@ -46,7 +46,7 @@ ACPI: Core revision 20070126
 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]

 ACPI: Unable to load the System Description Tables

 Using local APIC timer interrupts.

-result 7812539

+result 7812530

 Detected 7.812 MHz APIC timer.

 NET: Registered protocol family 16

 PCI: Using configuration type 1

diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
index 2807da6d7..e69de29bb 100755
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
@@ -1,39 +0,0 @@
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: rounding error > tolerance
-    0.145519 rounded to 0
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Don't know what interrupt to clear for console.
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index 0f037ca30..f0acb3441 100755
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -1,16 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 21 2014 21:13:41
-gem5 started Sep 21 2014 21:13:51
-gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /z/stever/hg/gem5/tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
-Global frequency set at 2000000000 ticks per second
-info: No kernel set for full system simulation. Assuming you know what you're doing
-      0: system.t1000.htod: Real-time clock set to Thu Jan  1 00:00:00 2009
+gem5 compiled Dec  4 2015 15:03:17
+gem5 started Dec  4 2015 15:03:30
+gem5 executing on e104799-lin, pid 26420
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 
-      0: system.t1000.htod: Real-time clock set to 1230768000
-info: Entering event queue @ 0.  Starting simulation...
-info: Ignoring write to SPARC ERROR regsiter
-info: Ignoring write to SPARC ERROR regsiter
-Exiting @ tick 4467555024 because m5_exit instruction encountered
+Skipping test: Can't find file 'disk.s10hw2' on path.
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index 89d9becf2..e69de29bb 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -1,251 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  2.233778                       # Number of seconds simulated
-sim_ticks                                  4467555024                       # Number of ticks simulated
-final_tick                                 4467555024                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                   2000000000                       # Frequency of simulated ticks
-host_inst_rate                                1794168                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1794873                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                3597181                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 569892                       # Number of bytes of host memory used
-host_seconds                                  1241.96                       # Real time elapsed on the host
-sim_insts                                  2228284650                       # Number of instructions simulated
-sim_ops                                    2229160714                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                             2                       # Clock period in ticks
-system.hypervisor_desc.bytes_read::cpu.data        16792                       # Number of bytes read from this memory
-system.hypervisor_desc.bytes_read::total        16792                       # Number of bytes read from this memory
-system.hypervisor_desc.num_reads::cpu.data         9024                       # Number of read requests responded to by this memory
-system.hypervisor_desc.num_reads::total          9024                       # Number of read requests responded to by this memory
-system.hypervisor_desc.bw_read::cpu.data         7517                       # Total read bandwidth from this memory (bytes/s)
-system.hypervisor_desc.bw_read::total            7517                       # Total read bandwidth from this memory (bytes/s)
-system.hypervisor_desc.bw_total::cpu.data         7517                       # Total bandwidth to/from this memory (bytes/s)
-system.hypervisor_desc.bw_total::total           7517                       # Total bandwidth to/from this memory (bytes/s)
-system.nvram.bytes_read::cpu.data                 284                       # Number of bytes read from this memory
-system.nvram.bytes_read::total                    284                       # Number of bytes read from this memory
-system.nvram.bytes_written::cpu.data               92                       # Number of bytes written to this memory
-system.nvram.bytes_written::total                  92                       # Number of bytes written to this memory
-system.nvram.num_reads::cpu.data                  284                       # Number of read requests responded to by this memory
-system.nvram.num_reads::total                     284                       # Number of read requests responded to by this memory
-system.nvram.num_writes::cpu.data                  92                       # Number of write requests responded to by this memory
-system.nvram.num_writes::total                     92                       # Number of write requests responded to by this memory
-system.nvram.bw_read::cpu.data                    127                       # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_read::total                       127                       # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_write::cpu.data                    41                       # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_write::total                       41                       # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_total::cpu.data                   168                       # Total bandwidth to/from this memory (bytes/s)
-system.nvram.bw_total::total                      168                       # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bytes_read::cpu.data         4846                       # Number of bytes read from this memory
-system.partition_desc.bytes_read::total          4846                       # Number of bytes read from this memory
-system.partition_desc.num_reads::cpu.data          608                       # Number of read requests responded to by this memory
-system.partition_desc.num_reads::total            608                       # Number of read requests responded to by this memory
-system.partition_desc.bw_read::cpu.data          2169                       # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_read::total             2169                       # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_total::cpu.data         2169                       # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bw_total::total            2169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem0.bytes_read::cpu.inst        612291324                       # Number of bytes read from this memory
-system.physmem0.bytes_read::cpu.data         97534024                       # Number of bytes read from this memory
-system.physmem0.bytes_read::total           709825348                       # Number of bytes read from this memory
-system.physmem0.bytes_inst_read::cpu.inst    612291324                       # Number of instructions bytes read from this memory
-system.physmem0.bytes_inst_read::total      612291324                       # Number of instructions bytes read from this memory
-system.physmem0.bytes_written::cpu.data      15400223                       # Number of bytes written to this memory
-system.physmem0.bytes_written::total         15400223                       # Number of bytes written to this memory
-system.physmem0.num_reads::cpu.inst         153072831                       # Number of read requests responded to by this memory
-system.physmem0.num_reads::cpu.data          12152054                       # Number of read requests responded to by this memory
-system.physmem0.num_reads::total            165224885                       # Number of read requests responded to by this memory
-system.physmem0.num_writes::cpu.data          1927067                       # Number of write requests responded to by this memory
-system.physmem0.num_writes::total             1927067                       # Number of write requests responded to by this memory
-system.physmem0.num_other::cpu.data                14                       # Number of other requests responded to by this memory
-system.physmem0.num_other::total                   14                       # Number of other requests responded to by this memory
-system.physmem0.bw_read::cpu.inst           274105779                       # Total read bandwidth from this memory (bytes/s)
-system.physmem0.bw_read::cpu.data            43663267                       # Total read bandwidth from this memory (bytes/s)
-system.physmem0.bw_read::total              317769046                       # Total read bandwidth from this memory (bytes/s)
-system.physmem0.bw_inst_read::cpu.inst      274105779                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem0.bw_inst_read::total         274105779                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem0.bw_write::cpu.data            6894251                       # Write bandwidth from this memory (bytes/s)
-system.physmem0.bw_write::total               6894251                       # Write bandwidth from this memory (bytes/s)
-system.physmem0.bw_total::cpu.inst          274105779                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem0.bw_total::cpu.data           50557518                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem0.bw_total::total             324663297                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bytes_read::cpu.inst       8318106840                       # Number of bytes read from this memory
-system.physmem1.bytes_read::cpu.data       1495885127                       # Number of bytes read from this memory
-system.physmem1.bytes_read::total          9813991967                       # Number of bytes read from this memory
-system.physmem1.bytes_inst_read::cpu.inst   8318106840                       # Number of instructions bytes read from this memory
-system.physmem1.bytes_inst_read::total     8318106840                       # Number of instructions bytes read from this memory
-system.physmem1.bytes_written::cpu.data     897268422                       # Number of bytes written to this memory
-system.physmem1.bytes_written::total        897268422                       # Number of bytes written to this memory
-system.physmem1.num_reads::cpu.inst        2079526710                       # Number of read requests responded to by this memory
-system.physmem1.num_reads::cpu.data         323962420                       # Number of read requests responded to by this memory
-system.physmem1.num_reads::total           2403489130                       # Number of read requests responded to by this memory
-system.physmem1.num_writes::cpu.data        187387796                       # Number of write requests responded to by this memory
-system.physmem1.num_writes::total           187387796                       # Number of write requests responded to by this memory
-system.physmem1.num_other::cpu.data           5403067                       # Number of other requests responded to by this memory
-system.physmem1.num_other::total              5403067                       # Number of other requests responded to by this memory
-system.physmem1.bw_read::cpu.inst          3723784842                       # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_read::cpu.data           669666123                       # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_read::total             4393450966                       # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_inst_read::cpu.inst     3723784842                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem1.bw_inst_read::total        3723784842                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem1.bw_write::cpu.data          401682091                       # Write bandwidth from this memory (bytes/s)
-system.physmem1.bw_write::total             401682091                       # Write bandwidth from this memory (bytes/s)
-system.physmem1.bw_total::cpu.inst         3723784842                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bw_total::cpu.data         1071348214                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bw_total::total            4795133057                       # Total bandwidth to/from this memory (bytes/s)
-system.rom.bytes_read::cpu.inst                432296                       # Number of bytes read from this memory
-system.rom.bytes_read::cpu.data                696392                       # Number of bytes read from this memory
-system.rom.bytes_read::total                  1128688                       # Number of bytes read from this memory
-system.rom.bytes_inst_read::cpu.inst           432296                       # Number of instructions bytes read from this memory
-system.rom.bytes_inst_read::total              432296                       # Number of instructions bytes read from this memory
-system.rom.num_reads::cpu.inst                 108074                       # Number of read requests responded to by this memory
-system.rom.num_reads::cpu.data                  87049                       # Number of read requests responded to by this memory
-system.rom.num_reads::total                    195123                       # Number of read requests responded to by this memory
-system.rom.bw_read::cpu.inst                   193527                       # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::cpu.data                   311755                       # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::total                      505282                       # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::cpu.inst              193527                       # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::total                 193527                       # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_total::cpu.inst                  193527                       # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::cpu.data                  311755                       # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::total                     505282                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu_clk_domain.clock                         2                       # Clock period in ticks
-system.cpu.numCycles                       2233777513                       # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  2228284650                       # Number of instructions committed
-system.cpu.committedOps                    2229160714                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1839325658                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses               14608322                       # Number of float alu accesses
-system.cpu.num_func_calls                    44037246                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    316367761                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1839325658                       # number of integer instructions
-system.cpu.num_fp_insts                      14608322                       # number of float instructions
-system.cpu.num_int_register_reads          4305540407                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         2100562807                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads             35401841                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes            22917558                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     547951940                       # number of memory refs
-system.cpu.num_load_insts                   349807670                       # Number of load instructions
-system.cpu.num_store_insts                  198144270                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 2233777513                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.Branches                         441057355                       # Number of branches fetched
-system.cpu.op_class::No_OpClass              49673656      2.22%      2.22% # Class of executed instruction
-system.cpu.op_class::IntAlu                1619015933     72.49%     74.71% # Class of executed instruction
-system.cpu.op_class::IntMult                        0      0.00%     74.71% # Class of executed instruction
-system.cpu.op_class::IntDiv                         0      0.00%     74.71% # Class of executed instruction
-system.cpu.op_class::FloatAdd                 8419779      0.38%     75.09% # Class of executed instruction
-system.cpu.op_class::FloatCmp                       0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::FloatCvt                       0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::FloatMult                      0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::FloatDiv                       0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::FloatSqrt                      0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdAdd                        0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc                     0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdAlu                        0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdCmp                        0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdCvt                        0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdMisc                       0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdMult                       0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc                    0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdShift                      0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc                   0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdSqrt                       0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd                   0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu                   0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp                   0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt                   0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv                   0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc                  0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult                  0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc               0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt                  0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::MemRead                356274529     15.95%     91.04% # Class of executed instruction
-system.cpu.op_class::MemWrite               200199782      8.96%    100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                 2233583679                       # Class of executed instruction
-system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.iobus.trans_dist::ReadReq              4348554                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             4348554                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                7569                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               7569                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_membnks.pio           40                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_2.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_3.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_4.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_1.pio            4                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_2.pio            4                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_3.pio            4                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_4.pio            4                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.fake_jbi.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.puart0.pio        29218                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.hvuart.pio           36                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.disk0.pio      8682882                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      8712246                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_membnks.pio          160                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_1.pio           64                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_2.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_3.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_4.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_1.pio           16                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_2.pio           16                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_3.pio           16                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_4.pio           16                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.fake_jbi.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.puart0.pio        14609                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.hvuart.pio           18                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.disk0.pio     34731524                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total     34746591                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.trans_dist::ReadReq          2573267624                       # Transaction distribution
-system.membus.trans_dist::ReadResp         2573267624                       # Transaction distribution
-system.membus.trans_dist::WriteReq          189322556                       # Transaction distribution
-system.membus.trans_dist::WriteResp         189322556                       # Transaction distribution
-system.membus.trans_dist::SwapReq             5403081                       # Transaction distribution
-system.membus.trans_dist::SwapResp            5403081                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.rom.port       216148                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::system.physmem0.port    306145662                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::system.physmem1.port   4159053420                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total   4465415230                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.t1000.iob.pio           64                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.t1000.htod.pio           32                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.bridge.slave      8712246                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.rom.port       174098                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.nvram.port          752                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.hypervisor_desc.port        18048                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.partition_desc.port         1216                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem0.port     28158270                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem1.port   1033506566                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total   1070571292                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total             5535986522                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.rom.port       432296                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem0.port    612291324                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem1.port   8318106840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total   8930830460                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.t1000.iob.pio          256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.t1000.htod.pio          128                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.bridge.slave     34746591                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.rom.port       696392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.nvram.port          376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.hypervisor_desc.port        16792                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.partition_desc.port         4846                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem0.port    112934471                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem1.port   2454584131                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total   2602983983                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total             11533814443                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples        2767993261                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.806616                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.394951                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0               535285646     19.34%     19.34% # Request fanout histogram
-system.membus.snoop_fanout::1              2232707615     80.66%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total          2767993261                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 147022c3d..26263fe30 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/work/gem5/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/work/gem5/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -28,8 +28,8 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/work/gem5/dist/binaries/ts_osfpal
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -357,7 +357,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -380,7 +380,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -403,10 +403,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.tsunami.pciconfig.pio
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
@@ -433,7 +432,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[29]
+cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[2]
 
 [system.iocache.tags]
@@ -541,7 +540,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -577,7 +576,7 @@ system=system
 
 [system.tsunami]
 type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -690,12 +689,12 @@ dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
 hardware_address=00:90:00:00:00:01
+host=system.tsunami.pchip
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 rss=false
 rx_delay=1000000
 rx_fifo_size=524288
@@ -705,9 +704,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.master[28]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[27]
+pio=system.iobus.master[26]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1140,14 +1138,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
 eventq_index=0
+host=system.tsunami.pchip
 io_shift=0
 pci_bus=0
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 system=system
-config=system.iobus.master[26]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[25]
 
@@ -1167,25 +1164,20 @@ pio=system.iobus.master[22]
 [system.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=system.clk_domain
+conf_base=8804649402368
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
+pci_dma_base=0
+pci_mem_base=8796093022208
+pci_pio_base=8804615847936
 pio_addr=8802535473152
 pio_latency=100000
+platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.master[1]
 
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
 [system.tsunami.uart]
 type=Uart8250
 clk_domain=system.clk_domain
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 9712abdc1..267d74a00 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:25
-gem5 executing on ribera.cs.wisc.edu, pid 29050
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+gem5 compiled Dec  4 2015 10:28:58
+gem5 started Dec  4 2015 11:07:13
+gem5 executing on e104799-lin, pid 25873
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /work/gem5/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 97861500
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 6db4bbedf..7d1787c51 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.869358                       # Nu
 sim_ticks                                1869358498000                       # Number of ticks simulated
 final_tick                               1869358498000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1547194                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1547193                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            44495947902                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 371328                       # Number of bytes of host memory used
-host_seconds                                    42.01                       # Real time elapsed on the host
+host_inst_rate                                1636822                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1636821                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            47073565091                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 332968                       # Number of bytes of host memory used
+host_seconds                                    39.71                       # Real time elapsed on the host
 sim_insts                                    65000470                       # Number of instructions simulated
 sim_ops                                      65000470                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -661,33 +661,27 @@ system.iobus.trans_dist::ReadResp                7628                       # Tr
 system.iobus.trans_dist::WriteReq               56140                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              56140                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14686                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1014                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio         1076                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18036                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total        44074                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83462                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83462                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  127536                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        58744                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2749                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio         1392                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9018                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total        86162                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661656                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661656                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 399564d33..fdc1c18f8 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/work/gem5/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/work/gem5/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -28,8 +28,8 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/work/gem5/dist/binaries/ts_osfpal
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -283,7 +283,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -306,7 +306,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -329,10 +329,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.tsunami.pciconfig.pio
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
@@ -359,7 +358,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[29]
+cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[2]
 
 [system.iocache.tags]
@@ -430,7 +429,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -443,7 +442,7 @@ port=3456
 
 [system.tsunami]
 type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -556,12 +555,12 @@ dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
 hardware_address=00:90:00:00:00:01
+host=system.tsunami.pchip
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 rss=false
 rx_delay=1000000
 rx_fifo_size=524288
@@ -571,9 +570,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.master[28]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[27]
+pio=system.iobus.master[26]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1006,14 +1004,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
 eventq_index=0
+host=system.tsunami.pchip
 io_shift=0
 pci_bus=0
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 system=system
-config=system.iobus.master[26]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[25]
 
@@ -1033,25 +1030,20 @@ pio=system.iobus.master[22]
 [system.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=system.clk_domain
+conf_base=8804649402368
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
+pci_dma_base=0
+pci_mem_base=8796093022208
+pci_pio_base=8804615847936
 pio_addr=8802535473152
 pio_latency=100000
+platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.master[1]
 
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
 [system.tsunami.uart]
 type=Uart8250
 clk_domain=system.clk_domain
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 2fef53741..f5d0532f3 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:58
-gem5 executing on ribera.cs.wisc.edu, pid 29091
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
+gem5 compiled Dec  4 2015 10:28:58
+gem5 started Dec  4 2015 10:35:24
+gem5 executing on e104799-lin, pid 22025
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /work/gem5/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1829332273500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 22bb41ee4..cb5e09d0f 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.829332                       # Nu
 sim_ticks                                1829332273500                       # Number of ticks simulated
 final_tick                               1829332273500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1568783                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1568783                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            47799849374                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 368252                       # Number of bytes of host memory used
-host_seconds                                    38.27                       # Real time elapsed on the host
+host_inst_rate                                1702079                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1702079                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            51861293564                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 329640                       # Number of bytes of host memory used
+host_seconds                                    35.27                       # Real time elapsed on the host
 sim_insts                                    60038341                       # Number of instructions simulated
 sim_ops                                      60038341                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -489,33 +489,27 @@ system.iobus.trans_dist::ReadResp                7358                       # Tr
 system.iobus.trans_dist::WriteReq               51390                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              51390                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5248                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1010                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio         1076                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18012                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total        34044                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  117496                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20992                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2733                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio         1392                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9006                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total        46126                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 20ac6fa35..419a63341 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/work/gem5/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/work/gem5/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -28,8 +28,8 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/work/gem5/dist/binaries/ts_osfpal
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -349,7 +349,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -372,7 +372,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -395,10 +395,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.tsunami.pciconfig.pio
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
@@ -425,7 +424,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[29]
+cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[2]
 
 [system.iocache.tags]
@@ -597,7 +596,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -633,7 +632,7 @@ system=system
 
 [system.tsunami]
 type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -746,12 +745,12 @@ dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
 hardware_address=00:90:00:00:00:01
+host=system.tsunami.pchip
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 rss=false
 rx_delay=1000000
 rx_fifo_size=524288
@@ -761,9 +760,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.master[28]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[27]
+pio=system.iobus.master[26]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1196,14 +1194,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
 eventq_index=0
+host=system.tsunami.pchip
 io_shift=0
 pci_bus=0
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 system=system
-config=system.iobus.master[26]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[25]
 
@@ -1223,25 +1220,20 @@ pio=system.iobus.master[22]
 [system.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=system.clk_domain
+conf_base=8804649402368
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
+pci_dma_base=0
+pci_mem_base=8796093022208
+pci_pio_base=8804615847936
 pio_addr=8802535473152
 pio_latency=100000
+platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.master[1]
 
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
 [system.tsunami.uart]
 type=Uart8250
 clk_domain=system.clk_domain
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 0661a98ef..19ef21baf 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,16 +1,14 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:28:24
-gem5 executing on ribera.cs.wisc.edu, pid 29049
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+gem5 compiled Dec  4 2015 10:28:58
+gem5 started Dec  4 2015 10:53:21
+gem5 executing on e104799-lin, pid 24287
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /work/gem5/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 881785000
-Exiting @ tick 1977709274000 because m5_exit instruction encountered
+Exiting @ tick 1982594146000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index feaac6b8f..faf036214 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,118 +1,118 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.977709                       # Number of seconds simulated
-sim_ticks                                1977709274000                       # Number of ticks simulated
-final_tick                               1977709274000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.982594                       # Number of seconds simulated
+sim_ticks                                1982594146000                       # Number of ticks simulated
+final_tick                               1982594146000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 813213                       # Simulator instruction rate (inst/s)
-host_op_rate                                   813212                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27059617080                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 371328                       # Number of bytes of host memory used
-host_seconds                                    73.09                       # Real time elapsed on the host
-sim_insts                                    59435338                       # Number of instructions simulated
-sim_ops                                      59435338                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 876674                       # Simulator instruction rate (inst/s)
+host_op_rate                                   876674                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            28498337600                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 332972                       # Number of bytes of host memory used
+host_seconds                                    69.57                       # Real time elapsed on the host
+sim_insts                                    60989111                       # Number of instructions simulated
+sim_ops                                      60989111                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           694336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         23907392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           165888                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1310592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           800320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24686528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            60096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           523456                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             26079168                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       694336                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       165888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          860224                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7747712                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7747712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             10849                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            373553                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2592                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             20478                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             26071360                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       800320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        60096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          860416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7740160                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7740160                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             12505                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            385727                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               939                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8179                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                407487                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          121058                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               121058                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              351081                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12088426                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               83879                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              662682                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               485                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13186553                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         351081                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          83879                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             434960                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3917518                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3917518                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3917518                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             351081                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12088426                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              83879                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             662682                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              485                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17104071                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        407487                       # Number of read requests accepted
-system.physmem.writeReqs                       121058                       # Number of write requests accepted
-system.physmem.readBursts                      407487                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     121058                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26071296                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7872                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7746112                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  26079168                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7747712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      123                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                407365                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          120940                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               120940                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              403673                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12451630                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               30312                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              264026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide               484                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13150125                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         403673                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          30312                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             433985                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3904057                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3904057                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3904057                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             403673                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12451630                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              30312                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             264026                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide              484                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               17054181                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        407365                       # Number of read requests accepted
+system.physmem.writeReqs                       120940                       # Number of write requests accepted
+system.physmem.readBursts                      407365                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     120940                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26063552                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7808                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7739008                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  26071360                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7740160                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      122                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         306935                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               25840                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26009                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               26271                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               25739                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               24904                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               25588                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25282                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               25179                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               24919                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               24911                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25224                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              25266                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              25817                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              25627                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25517                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25271                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8076                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7966                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8289                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8035                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7145                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7755                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7349                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7181                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                6971                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7004                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7220                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7086                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7863                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7891                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7798                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7404                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         310700                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               25226                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25379                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25426                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24856                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25157                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               25423                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25497                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               25344                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25239                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25589                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25746                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              25918                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              25947                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              25572                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              25277                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25647                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7851                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7778                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7471                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6887                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7104                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7345                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7441                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7150                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7161                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7315                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7729                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8151                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8256                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7924                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7541                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7818                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1977655892500                       # Total gap between requests
+system.physmem.totGap                    1982586778500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  407487                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  407365                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 121058                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    407280                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                        71                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 120940                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    407167                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                        63                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
@@ -158,187 +158,190 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1864                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6408                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6513                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8012                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     9465                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     8437                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6918                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5930                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5620                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      195                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       92                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      116                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       72                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       65                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        68003                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      497.292884                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     300.084252                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     405.105473                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          16504     24.27%     24.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        12590     18.51%     42.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5294      7.78%     50.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3182      4.68%     55.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2479      3.65%     58.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         4294      6.31%     65.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1483      2.18%     67.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2078      3.06%     70.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20099     29.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          68003                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5421                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        75.144069                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2865.262786                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-8191           5418     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     1876                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5780                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5821                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6758                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6579                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7992                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     8405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     9429                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     8504                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8718                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5833                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5622                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      211                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      154                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       87                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      115                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       76                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        67594                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      500.082256                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     302.770491                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     404.772373                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          16306     24.12%     24.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        12315     18.22%     42.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5219      7.72%     50.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3345      4.95%     55.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2482      3.67%     58.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4236      6.27%     64.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1519      2.25%     67.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2145      3.17%     70.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20027     29.63%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          67594                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5426                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        75.053815                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2863.944316                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           5423     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5421                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5421                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.326692                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       19.006479                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       21.134399                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4779     88.16%     88.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              22      0.41%     88.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              23      0.42%     88.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             175      3.23%     92.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               9      0.17%     92.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              25      0.46%     92.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              50      0.92%     93.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               2      0.04%     93.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              13      0.24%     94.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              19      0.35%     94.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.02%     94.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               6      0.11%     94.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               8      0.15%     94.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               2      0.04%     94.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              22      0.41%     95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              20      0.37%     95.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               4      0.07%     95.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87              34      0.63%     96.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     96.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               2      0.04%     96.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103           161      2.97%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             2      0.04%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             3      0.06%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.04%     99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             6      0.11%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             5      0.09%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171             3      0.06%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             1      0.02%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183            16      0.30%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::252-255             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5421                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2796894000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10434969000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2036820000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6865.83                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5426                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5426                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.285662                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.994987                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       21.002081                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4792     88.32%     88.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              23      0.42%     88.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              16      0.29%     89.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             184      3.39%     92.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               1      0.02%     92.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              19      0.35%     92.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              45      0.83%     93.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               3      0.06%     93.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               7      0.13%     93.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              30      0.55%     94.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               7      0.13%     94.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               4      0.07%     94.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               5      0.09%     94.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               4      0.07%     94.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              20      0.37%     95.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              26      0.48%     95.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87              28      0.52%     96.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.02%     96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               4      0.07%     96.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.02%     96.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103           168      3.10%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             1      0.02%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             1      0.02%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             2      0.04%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             1      0.02%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147             1      0.02%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.04%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163             2      0.04%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             5      0.09%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171             5      0.09%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183            10      0.18%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191             1      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207             1      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223             1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231             3      0.06%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5426                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2787487250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10423293500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2036215000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6844.78                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25615.83                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          13.18                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.92                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       13.19                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.92                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25594.78                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          13.15                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.90                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       13.15                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.90                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.13                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.10                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        25.07                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     363824                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     96570                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.31                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.77                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3741698.23                       # Average gap between requests
-system.physmem.pageHitRate                      87.13                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  262483200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  143220000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1597533600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                400438080                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           129174240000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            73962048600                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1121745657750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1327285621230                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.123235                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1865834845500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     66040000000                       # Time in different power states
+system.physmem.avgWrQLen                        23.89                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     363847                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     96724                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.34                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.98                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3752731.43                       # Average gap between requests
+system.physmem.pageHitRate                      87.20                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  243930960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  133097250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1578002400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                382494960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           129493107120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            72912858435                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1125595195500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1330338686625                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.010578                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1872246434250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     66203020000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     45832914500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     44140298250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  251619480                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  137292375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1579905600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                383855760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           129174240000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            73584887580                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1122076500750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1327188301545                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.074027                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1866389529250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     66040000000                       # Time in different power states
+system.physmem_1.actEnergy                  267079680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  145728000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1598493000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                401079600                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           129493107120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            73974222945                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1124664165750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1330543876095                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.114078                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1870697169250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     66203020000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     45278230750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     45689549500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     5727753                       # DTB read hits
+system.cpu0.dtb.read_hits                     7416215                       # DTB read hits
 system.cpu0.dtb.read_misses                      7442                       # DTB read misses
 system.cpu0.dtb.read_acv                          210                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  490672                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3981122                       # DTB write hits
+system.cpu0.dtb.write_hits                    5004240                       # DTB write hits
 system.cpu0.dtb.write_misses                      812                       # DTB write misses
 system.cpu0.dtb.write_acv                         134                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 187451                       # DTB write accesses
-system.cpu0.dtb.data_hits                     9708875                       # DTB hits
+system.cpu0.dtb.data_hits                    12420455                       # DTB hits
 system.cpu0.dtb.data_misses                      8254                       # DTB misses
 system.cpu0.dtb.data_acv                          344                       # DTB access violations
 system.cpu0.dtb.data_accesses                  678123                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3124468                       # ITB hits
+system.cpu0.itb.fetch_hits                    3482237                       # ITB hits
 system.cpu0.itb.fetch_misses                     3871                       # ITB misses
 system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                3128339                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3486108                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -351,36 +354,36 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3955086246                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3964851893                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4843                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    129735                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   41337     38.33%     38.33% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.12%     38.45% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1972      1.83%     40.28% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                     17      0.02%     40.29% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  64391     59.71%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              107848                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    40894     48.75%     48.75% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.16%     48.90% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1972      2.35%     51.25% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                      17      0.02%     51.27% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   40877     48.73%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total                83891                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1907093255000     96.44%     96.44% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               94033500      0.00%     96.44% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              783814000      0.04%     96.48% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30               14262000      0.00%     96.48% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            69557728500      3.52%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1977543093000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.989283                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6804                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    162792                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   55926     40.12%     40.12% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.09%     40.21% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1977      1.42%     41.63% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    435      0.31%     41.94% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  80934     58.06%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              139403                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    55417     49.07%     49.07% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.12%     49.18% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1977      1.75%     50.93% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     435      0.39%     51.32% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   54982     48.68%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               112942                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1904792162000     96.08%     96.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               93245000      0.00%     96.09% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              790775500      0.04%     96.13% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              326471500      0.02%     96.14% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            76423262500      3.86%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1982425916500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.990899                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.634825                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.777863                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.679344                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.810183                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
 system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
@@ -412,179 +415,179 @@ system.cpu0.kern.syscall::144                       2      0.90%     99.10% # nu
 system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
 system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                   93      0.08%      0.08% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.08% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.08% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.08% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 1998      1.74%      1.82% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      51      0.04%      1.87% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.01%      1.87% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               101884     88.63%     90.50% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6548      5.70%     96.19% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.20% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     96.20% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.21% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.21% # number of callpals executed
-system.cpu0.kern.callpal::rti                    3843      3.34%     99.55% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 381      0.33%     99.88% # number of callpals executed
-system.cpu0.kern.callpal::imb                     136      0.12%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                114960                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             5413                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1282                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  524      0.36%      0.36% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.36% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.36% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.36% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3024      2.05%      2.41% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      51      0.03%      2.44% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.45% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               132535     89.80%     92.24% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6593      4.47%     96.71% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.71% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     96.71% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     96.72% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.72% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4324      2.93%     99.65% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 381      0.26%     99.91% # number of callpals executed
+system.cpu0.kern.callpal::imb                     136      0.09%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                147594                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             6862                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1281                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1282                      
-system.cpu0.kern.mode_good::user                 1282                      
+system.cpu0.kern.mode_good::kernel               1281                      
+system.cpu0.kern.mode_good::user                 1281                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.236837                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.186680                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.382972                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1972827474000     99.80%     99.80% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3894173000      0.20%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.314626                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1977686351500     99.80%     99.80% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3896829000      0.20%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    1999                       # number of times the context was actually changed
-system.cpu0.committedInsts                   36251265                       # Number of instructions committed
-system.cpu0.committedOps                     36251265                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             33727452                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                135758                       # Number of float alu accesses
-system.cpu0.num_func_calls                     876834                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4248905                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    33727452                       # number of integer instructions
-system.cpu0.num_fp_insts                       135758                       # number of float instructions
-system.cpu0.num_int_register_reads           46333717                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          25193797                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               65701                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              66416                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      9739707                       # number of memory refs
-system.cpu0.num_load_insts                    5749561                       # Number of load instructions
-system.cpu0.num_store_insts                   3990146                       # Number of store instructions
-system.cpu0.num_idle_cycles              3736968981.972937                       # Number of idle cycles
-system.cpu0.num_busy_cycles              218117264.027063                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.055149                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.944851                       # Percentage of idle cycles
-system.cpu0.Branches                          5398761                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              1979626      5.46%      5.46% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 23753610     65.51%     70.97% # Class of executed instruction
-system.cpu0.op_class::IntMult                   36908      0.10%     71.07% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     71.07% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  22960      0.06%     71.13% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     71.13% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1656      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.14% # Class of executed instruction
-system.cpu0.op_class::MemRead                 5882505     16.22%     87.36% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3995282     11.02%     98.38% # Class of executed instruction
-system.cpu0.op_class::IprAccess                587316      1.62%    100.00% # Class of executed instruction
+system.cpu0.kern.swap_context                    3025                       # number of times the context was actually changed
+system.cpu0.committedInsts                   47311851                       # Number of instructions committed
+system.cpu0.committedOps                     47311851                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             43882265                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                206939                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1185568                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      5564719                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    43882265                       # number of integer instructions
+system.cpu0.num_fp_insts                       206939                       # number of float instructions
+system.cpu0.num_int_register_reads           60327433                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          32715156                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              100516                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             102286                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     12460349                       # number of memory refs
+system.cpu0.num_load_insts                    7443153                       # Number of load instructions
+system.cpu0.num_store_insts                   5017196                       # Number of store instructions
+system.cpu0.num_idle_cycles              3699958327.970898                       # Number of idle cycles
+system.cpu0.num_busy_cycles              264893565.029101                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.066810                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.933190                       # Percentage of idle cycles
+system.cpu0.Branches                          7132898                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass              2702955      5.71%      5.71% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 31171442     65.87%     71.59% # Class of executed instruction
+system.cpu0.op_class::IntMult                   51645      0.11%     71.69% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     71.69% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                  25566      0.05%     71.75% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                   1656      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc                 0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     71.75% # Class of executed instruction
+system.cpu0.op_class::MemRead                 7616230     16.10%     87.85% # Class of executed instruction
+system.cpu0.op_class::MemWrite                5023298     10.62%     98.46% # Class of executed instruction
+system.cpu0.op_class::IprAccess                727657      1.54%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  36259863                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements           822072                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          480.504845                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs            8885001                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           822496                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            10.802485                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                  47320449                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements          1172797                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.333348                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           11236424                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1173216                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.577455                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        144706500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.504845                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938486                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.938486                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          424                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          167                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3          257                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024     0.828125                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         39682070                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        39682070                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5000163                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5000163                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3644006                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3644006                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117543                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       117543                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       123259                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       123259                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8644169                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         8644169                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8644169                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        8644169                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       612538                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       612538                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       209263                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       209263                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6851                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         6851                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          636                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          636                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       821801                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        821801                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       821801                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       821801                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  38657814000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  38657814000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  14917066000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  14917066000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     93675500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     93675500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      8969500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      8969500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  53574880000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  53574880000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  53574880000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  53574880000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5612701                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      5612701                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3853269                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      3853269                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124394                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       124394                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       123895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      9465970                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total      9465970                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      9465970                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total      9465970                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.109134                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.109134                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.054308                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.054308                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055075                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055075                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.005133                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.005133                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086816                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.086816                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086816                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.086816                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 63110.882917                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 63110.882917                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71283.819882                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 71283.819882                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13673.259378                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13673.259378                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14102.987421                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14102.987421                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 65192.035541                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 65192.035541                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 65192.035541                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 65192.035541                       # average overall miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.333348                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986979                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.986979                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          419                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3          371                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.818359                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         50906675                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        50906675                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6342506                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6342506                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4600881                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       4600881                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       138108                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       138108                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       145430                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       145430                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10943387                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10943387                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10943387                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10943387                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       934212                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       934212                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       249094                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       249094                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13595                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        13595                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5739                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         5739                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1183306                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1183306                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1183306                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1183306                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  42884699000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  42884699000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  16803448000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  16803448000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    151690000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    151690000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     97426500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     97426500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  59688147000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  59688147000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  59688147000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  59688147000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7276718                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7276718                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4849975                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4849975                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       151703                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       151703                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       151169                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       151169                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12126693                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12126693                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12126693                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12126693                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.128384                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.128384                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051360                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.051360                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.089616                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.089616                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.037964                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.037964                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.097579                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.097579                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097579                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.097579                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45904.675812                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 45904.675812                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67458.260737                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 67458.260737                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11157.778595                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11157.778595                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16976.215369                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16976.215369                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50441.852741                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 50441.852741                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50441.852741                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 50441.852741                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -593,126 +596,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       366665                       # number of writebacks
-system.cpu0.dcache.writebacks::total           366665                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       612538                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       612538                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       209263                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       209263                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6851                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6851                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          636                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total          636                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       821801                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       821801                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       821801                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       821801                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         4814                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         4814                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data         8193                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         8193                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        13007                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        13007                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38045276000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  38045276000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  14707803000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  14707803000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     86824500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     86824500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      8333500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      8333500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  52753079000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  52753079000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  52753079000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  52753079000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1072338000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1072338000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1840159000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1840159000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2912497000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2912497000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.109134                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.109134                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.054308                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.054308                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.055075                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.055075                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.005133                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.005133                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086816                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.086816                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086816                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.086816                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 62110.882917                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 62110.882917                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 70283.819882                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70283.819882                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12673.259378                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.259378                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13102.987421                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13102.987421                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 64192.035541                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 64192.035541                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 64192.035541                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 64192.035541                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222754.050686                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222754.050686                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 224601.367021                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224601.367021                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 223917.659722                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 223917.659722                       # average overall mshr uncacheable latency
+system.cpu0.dcache.writebacks::writebacks       672822                       # number of writebacks
+system.cpu0.dcache.writebacks::total           672822                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       934212                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       934212                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       249094                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       249094                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13595                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13595                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5739                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         5739                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1183306                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1183306                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1183306                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1183306                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data         7080                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total         7080                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        10780                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        10780                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        17860                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        17860                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  41950487000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41950487000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  16554354000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  16554354000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    138095000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    138095000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     91687500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     91687500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  58504841000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  58504841000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  58504841000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  58504841000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1566158000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1566158000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2451078500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2451078500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   4017236500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4017236500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.128384                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.128384                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051360                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051360                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.089616                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.089616                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.037964                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.037964                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.097579                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.097579                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.097579                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.097579                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44904.675812                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44904.675812                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66458.260737                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66458.260737                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10157.778595                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10157.778595                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15976.215369                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15976.215369                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49441.852741                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49441.852741                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49441.852741                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49441.852741                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221208.757062                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221208.757062                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227372.773655                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227372.773655                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224929.255319                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224929.255319                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements           490042                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          506.476572                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           35769214                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           490554                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            72.915956                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements           686460                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          506.490701                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           46633355                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           686972                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            67.882468                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      58998281500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   506.476572                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.989212                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.989212                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   506.490701                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.989240                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.989240                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          216                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3          296                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           95                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3          417                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         36750512                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        36750512                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     35769214                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       35769214                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     35769214                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        35769214                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     35769214                       # number of overall hits
-system.cpu0.icache.overall_hits::total       35769214                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       490649                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       490649                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       490649                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        490649                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       490649                       # number of overall misses
-system.cpu0.icache.overall_misses::total       490649                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7808174000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   7808174000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   7808174000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   7808174000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   7808174000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   7808174000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     36259863                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     36259863                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     36259863                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     36259863                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     36259863                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     36259863                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013531                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.013531                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013531                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.013531                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013531                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.013531                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15913.971087                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 15913.971087                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15913.971087                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 15913.971087                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15913.971087                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 15913.971087                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         48007543                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        48007543                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     46633355                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       46633355                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     46633355                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        46633355                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     46633355                       # number of overall hits
+system.cpu0.icache.overall_hits::total       46633355                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       687094                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       687094                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       687094                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        687094                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       687094                       # number of overall misses
+system.cpu0.icache.overall_misses::total       687094                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10621840000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  10621840000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  10621840000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  10621840000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  10621840000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  10621840000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     47320449                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     47320449                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     47320449                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     47320449                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     47320449                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     47320449                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014520                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014520                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014520                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014520                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014520                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014520                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15459.078379                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 15459.078379                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15459.078379                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 15459.078379                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15459.078379                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 15459.078379                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -721,53 +724,53 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks       490042                       # number of writebacks
-system.cpu0.icache.writebacks::total           490042                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       490649                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       490649                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       490649                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       490649                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       490649                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       490649                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   7317525000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   7317525000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   7317525000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   7317525000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   7317525000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   7317525000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013531                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013531                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013531                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.013531                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013531                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.013531                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14913.971087                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14913.971087                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14913.971087                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 14913.971087                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14913.971087                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 14913.971087                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks       686460                       # number of writebacks
+system.cpu0.icache.writebacks::total           686460                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       687094                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       687094                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       687094                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       687094                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       687094                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       687094                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9934746000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   9934746000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9934746000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   9934746000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9934746000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   9934746000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014520                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014520                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014520                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014520                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014520                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014520                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14459.078379                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14459.078379                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14459.078379                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 14459.078379                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14459.078379                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 14459.078379                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     3965416                       # DTB read hits
+system.cpu1.dtb.read_hits                     2510685                       # DTB read hits
 system.cpu1.dtb.read_misses                      2993                       # DTB read misses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  239364                       # DTB read accesses
-system.cpu1.dtb.write_hits                    2725894                       # DTB write hits
+system.cpu1.dtb.write_hits                    1829711                       # DTB write hits
 system.cpu1.dtb.write_misses                      342                       # DTB write misses
 system.cpu1.dtb.write_acv                          29                       # DTB write access violations
 system.cpu1.dtb.write_accesses                 105248                       # DTB write accesses
-system.cpu1.dtb.data_hits                     6691310                       # DTB hits
+system.cpu1.dtb.data_hits                     4340396                       # DTB hits
 system.cpu1.dtb.data_misses                      3335                       # DTB misses
 system.cpu1.dtb.data_acv                           29                       # DTB access violations
 system.cpu1.dtb.data_accesses                  344612                       # DTB accesses
-system.cpu1.itb.fetch_hits                    2218092                       # ITB hits
+system.cpu1.itb.fetch_hits                    1990327                       # ITB hits
 system.cpu1.itb.fetch_misses                     1216                       # ITB misses
 system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                2219308                       # ITB accesses
+system.cpu1.itb.fetch_accesses                1991543                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -780,32 +783,32 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3955418548                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3965188292                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    3977                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                    108865                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   40405     40.60%     40.60% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1966      1.98%     42.57% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                     93      0.09%     42.67% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  57058     57.33%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               99522                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    39471     48.79%     48.79% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1966      2.43%     51.21% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                      93      0.11%     51.33% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   39378     48.67%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                80908                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1902956585000     96.22%     96.22% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              734079500      0.04%     96.26% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               70449000      0.00%     96.26% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            73947425500      3.74%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1977708539000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.976884                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2870                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     81053                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   27549     38.53%     38.53% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1971      2.76%     41.28% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    524      0.73%     42.01% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  41464     57.99%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               71508                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    26681     48.22%     48.22% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1971      3.56%     51.78% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     524      0.95%     52.73% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   26157     47.27%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                55333                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1912242644500     96.45%     96.45% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              731132000      0.04%     96.49% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              374834500      0.02%     96.51% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            69244798000      3.49%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1982593409000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.968493                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.690140                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.812966                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.630836                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.773802                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
 system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
@@ -821,179 +824,179 @@ system.cpu1.kern.syscall::74                       10      9.62%     97.12% # nu
 system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
 system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                   17      0.02%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 2247      2.20%      2.22% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      2.22% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      2.23% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                94014     91.97%     94.20% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2296      2.25%     96.44% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     96.44% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.00%     96.45% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     96.45% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3448      3.37%     99.82% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 136      0.13%     99.96% # number of callpals executed
-system.cpu1.kern.callpal::imb                      44      0.04%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  435      0.59%      0.59% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.59% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.59% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 2066      2.79%      3.38% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.00%      3.39% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      3.40% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                65186     88.12%     91.52% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2261      3.06%     94.57% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.57% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     94.58% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     94.58% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3826      5.17%     99.76% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 136      0.18%     99.94% # number of callpals executed
+system.cpu1.kern.callpal::imb                      44      0.06%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                102224                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             2738                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                463                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2043                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                518                      
-system.cpu1.kern.mode_good::user                  463                      
-system.cpu1.kern.mode_good::idle                   55                      
-system.cpu1.kern.mode_switch_good::kernel     0.189189                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 73976                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             2114                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                464                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2922                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                912                      
+system.cpu1.kern.mode_good::user                  464                      
+system.cpu1.kern.mode_good::idle                  448                      
+system.cpu1.kern.mode_switch_good::kernel     0.431410                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.026921                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.197559                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       70603027000      3.57%      3.57% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1708148000      0.09%      3.66% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1905397362000     96.34%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    2248                       # number of times the context was actually changed
-system.cpu1.committedInsts                   23184073                       # Number of instructions committed
-system.cpu1.committedOps                     23184073                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             21342235                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                193178                       # Number of float alu accesses
-system.cpu1.num_func_calls                     708348                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2510657                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    21342235                       # number of integer instructions
-system.cpu1.num_fp_insts                       193178                       # number of float instructions
-system.cpu1.num_int_register_reads           29195011                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          15673593                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              100176                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             102374                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      6716060                       # number of memory refs
-system.cpu1.num_load_insts                    3980976                       # Number of load instructions
-system.cpu1.num_store_insts                   2735084                       # Number of store instructions
-system.cpu1.num_idle_cycles              3859200221.998049                       # Number of idle cycles
-system.cpu1.num_busy_cycles              96218326.001951                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.024326                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.975674                       # Percentage of idle cycles
-system.cpu1.Branches                          3468812                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass              1369332      5.91%      5.91% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 14462485     62.37%     68.28% # Class of executed instruction
-system.cpu1.op_class::IntMult                   32790      0.14%     68.42% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     68.42% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                  15288      0.07%     68.48% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     68.48% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     68.48% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     68.48% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                   1986      0.01%     68.49% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.49% # Class of executed instruction
-system.cpu1.op_class::MemRead                 4085109     17.62%     86.11% # Class of executed instruction
-system.cpu1.op_class::MemWrite                2736216     11.80%     97.91% # Class of executed instruction
-system.cpu1.op_class::IprAccess                484231      2.09%    100.00% # Class of executed instruction
+system.cpu1.kern.mode_switch_good::idle      0.153320                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.331636                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       19465916000      0.98%      0.98% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1729420000      0.09%      1.07% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1961398071000     98.93%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    2067                       # number of times the context was actually changed
+system.cpu1.committedInsts                   13677260                       # Number of instructions committed
+system.cpu1.committedOps                     13677260                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             12615003                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                178612                       # Number of float alu accesses
+system.cpu1.num_func_calls                     430048                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1358006                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    12615003                       # number of integer instructions
+system.cpu1.num_fp_insts                       178612                       # number of float instructions
+system.cpu1.num_int_register_reads           17367613                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           9253143                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               93246                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              95234                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      4364552                       # number of memory refs
+system.cpu1.num_load_insts                    2525340                       # Number of load instructions
+system.cpu1.num_store_insts                   1839212                       # Number of store instructions
+system.cpu1.num_idle_cycles              3912229588.998027                       # Number of idle cycles
+system.cpu1.num_busy_cycles              52958703.001973                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.013356                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.986644                       # Percentage of idle cycles
+system.cpu1.Branches                          1948315                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass               733682      5.36%      5.36% # Class of executed instruction
+system.cpu1.op_class::IntAlu                  8093046     59.16%     64.52% # Class of executed instruction
+system.cpu1.op_class::IntMult                   23046      0.17%     64.69% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     64.69% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                  14372      0.11%     64.79% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     64.79% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                   1986      0.01%     64.81% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc                 0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     64.81% # Class of executed instruction
+system.cpu1.op_class::MemRead                 2600021     19.01%     83.81% # Class of executed instruction
+system.cpu1.op_class::MemWrite                1840236     13.45%     97.26% # Class of executed instruction
+system.cpu1.op_class::IprAccess                374235      2.74%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  23187437                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements           637928                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          487.645459                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            6059697                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           638440                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs             9.491412                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      77414441500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   487.645459                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.952433                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.952433                       # Average percentage of cache occupancy
+system.cpu1.op_class::total                  13680624                       # Class of executed instruction
+system.cpu1.dcache.tags.replacements           173715                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          481.481115                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            4164110                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           174227                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            23.900486                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      90323581500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   481.481115                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.940393                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.940393                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0          183                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         27453473                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        27453473                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3383453                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3383453                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2527183                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2527183                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        67642                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        67642                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        79428                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        79428                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5910636                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5910636                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      5910636                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5910636                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       511536                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       511536                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       119772                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       119772                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        12967                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        12967                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          653                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          653                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       631308                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        631308                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       631308                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       631308                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6625803500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   6625803500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3933748500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   3933748500                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    167428500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    167428500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     10386500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     10386500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  10559552000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  10559552000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  10559552000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  10559552000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3894989                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3894989                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2646955                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2646955                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        80609                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        80609                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        80081                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        80081                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      6541944                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      6541944                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      6541944                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      6541944                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.131332                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.131332                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.045249                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.045249                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.160863                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.160863                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.008154                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.008154                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.096502                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.096502                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.096502                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.096502                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12952.760901                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12952.760901                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32843.640417                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 32843.640417                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12911.891725                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12911.891725                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15905.819296                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15905.819296                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16726.466321                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16726.466321                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16726.466321                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16726.466321                       # average overall miss latency
+system.cpu1.dcache.tags.tag_accesses         17605365                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        17605365                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2339052                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2339052                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1706902                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1706902                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        50404                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        50404                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        53074                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        53074                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      4045954                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         4045954                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      4045954                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        4045954                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       123499                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       123499                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        65580                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        65580                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9274                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         9274                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         6110                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         6110                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       189079                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        189079                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       189079                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       189079                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1557395000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1557395000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1879104500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   1879104500                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     85318500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     85318500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     99555000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     99555000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   3436499500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   3436499500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   3436499500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   3436499500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2462551                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2462551                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1772482                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1772482                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        59678                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        59678                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        59184                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        59184                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      4235033                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      4235033                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      4235033                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      4235033                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.050151                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.050151                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.036999                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.036999                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.155401                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.155401                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.103237                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.103237                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.044646                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.044646                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.044646                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.044646                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12610.587940                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12610.587940                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28653.621531                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 28653.621531                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9199.751995                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9199.751995                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16293.780687                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16293.780687                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18174.940104                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18174.940104                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18174.940104                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18174.940104                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1002,128 +1005,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       496006                       # number of writebacks
-system.cpu1.dcache.writebacks::total           496006                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       511536                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       511536                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       119772                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       119772                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12967                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12967                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          653                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total          653                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       631308                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       631308                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       631308                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       631308                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         2385                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         2385                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         4228                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         4228                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         6613                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         6613                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   6114267500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   6114267500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   3813976500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   3813976500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    154461500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    154461500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      9733500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      9733500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9928244000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   9928244000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9928244000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   9928244000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    520029500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    520029500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    992921500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    992921500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1512951000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1512951000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.131332                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.131332                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.045249                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.045249                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.160863                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.160863                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.008154                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.008154                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.096502                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.096502                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.096502                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.096502                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.760901                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11952.760901                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31843.640417                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31843.640417                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11911.891725                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.891725                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14905.819296                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14905.819296                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15726.466321                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15726.466321                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15726.466321                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15726.466321                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 218041.719078                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218041.719078                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 234844.252602                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 234844.252602                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 228784.364131                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 228784.364131                       # average overall mshr uncacheable latency
+system.cpu1.dcache.writebacks::writebacks       119750                       # number of writebacks
+system.cpu1.dcache.writebacks::total           119750                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       123499                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       123499                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        65580                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        65580                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9274                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9274                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         6110                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         6110                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       189079                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       189079                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       189079                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       189079                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data          118                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total          118                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         3348                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         3348                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         3466                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         3466                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1433896000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1433896000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1813524500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1813524500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     76044500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     76044500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     93445000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     93445000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3247420500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   3247420500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3247420500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   3247420500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     25051000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     25051000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    789483500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    789483500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    814534500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    814534500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.050151                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.050151                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036999                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036999                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.155401                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.155401                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.103237                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.103237                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.044646                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.044646                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.044646                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.044646                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11610.587940                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11610.587940                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27653.621531                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27653.621531                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8199.751995                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8199.751995                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15293.780687                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15293.780687                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17174.940104                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17174.940104                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17174.940104                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17174.940104                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.497013                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.497013                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235007.068667                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235007.068667                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           510167                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          496.053321                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           22676720                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           510679                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            44.405037                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     117353975500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.053321                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.968854                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.968854                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements           331421                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          442.918144                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           13348652                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           331933                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            40.214899                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1976561020500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   442.918144                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.865074                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.865074                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          409                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          405                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::3           32                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         23698156                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        23698156                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     22676720                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       22676720                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     22676720                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        22676720                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     22676720                       # number of overall hits
-system.cpu1.icache.overall_hits::total       22676720                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       510718                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       510718                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       510718                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        510718                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       510718                       # number of overall misses
-system.cpu1.icache.overall_misses::total       510718                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7116614500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   7116614500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   7116614500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   7116614500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   7116614500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   7116614500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     23187438                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     23187438                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     23187438                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     23187438                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     23187438                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     23187438                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.022026                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.022026                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.022026                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.022026                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.022026                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.022026                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13934.528448                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13934.528448                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13934.528448                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13934.528448                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13934.528448                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13934.528448                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         14012598                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        14012598                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     13348652                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       13348652                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     13348652                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        13348652                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     13348652                       # number of overall hits
+system.cpu1.icache.overall_hits::total       13348652                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       331973                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       331973                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       331973                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        331973                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       331973                       # number of overall misses
+system.cpu1.icache.overall_misses::total       331973                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4541836000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4541836000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4541836000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4541836000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4541836000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4541836000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     13680625                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     13680625                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     13680625                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     13680625                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     13680625                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     13680625                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024266                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.024266                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024266                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.024266                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024266                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.024266                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13681.341555                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13681.341555                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13681.341555                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13681.341555                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13681.341555                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13681.341555                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1132,32 +1135,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       510167                       # number of writebacks
-system.cpu1.icache.writebacks::total           510167                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       510718                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       510718                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       510718                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       510718                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       510718                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       510718                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6605896500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   6605896500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6605896500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   6605896500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6605896500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   6605896500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.022026                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.022026                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.022026                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.022026                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.022026                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.022026                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12934.528448                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12934.528448                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12934.528448                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12934.528448                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12934.528448                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12934.528448                       # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks       331421                       # number of writebacks
+system.cpu1.icache.writebacks::total           331421                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       331973                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       331973                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       331973                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       331973                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       331973                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       331973                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4209863000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4209863000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4209863000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4209863000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4209863000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4209863000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024266                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024266                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024266                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.024266                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024266                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.024266                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.341555                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.341555                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.341555                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.341555                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.341555                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.341555                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -1171,110 +1174,98 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq                 7376                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7376                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               53973                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              53973                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10632                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          476                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               55680                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              55680                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14048                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2476                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        39240                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83458                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83458                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  122698                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        42528                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1904                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        42652                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  126106                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        56192                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9884                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        68786                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661640                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661640                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2730426                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             11275500                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total        82434                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2744058                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             15110500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               391000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               758000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy              174500                       # Layer occupancy (ticks)
+system.iobus.reqLayer22.occupancy              175000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            15840500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy            15842500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2460000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             6042000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             6039500                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              211500                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               83000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               82500                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           215050235                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              130500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           215040242                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               45000                       # Layer occupancy (ticks)
-system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            26819000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            28524000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            41954000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            41950000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                41699                       # number of replacements
-system.iocache.tags.tagsinuse                0.491123                       # Cycle average of tags in use
+system.iocache.tags.replacements                41695                       # number of replacements
+system.iocache.tags.tagsinuse                0.566864                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41715                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1769281205000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.491123                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.030695                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.030695                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1775104150000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.566864                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.035429                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.035429                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375561                       # Number of tag accesses
-system.iocache.tags.data_accesses              375561                       # Number of data accesses
-system.iocache.ReadReq_misses::tsunami.ide          177                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              177                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               375543                       # Number of tag accesses
+system.iocache.tags.data_accesses              375543                       # Number of data accesses
+system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide          177                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               177                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide          177                       # number of overall misses
-system.iocache.overall_misses::total              177                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     22195883                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     22195883                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   5429420359                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5429420359                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide     22195883                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     22195883                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide     22195883                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     22195883                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          177                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            177                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide          175                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               175                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide          175                       # number of overall misses
+system.iocache.overall_misses::total              175                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21956883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21956883                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::tsunami.ide   5428160352                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   5428160352                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide     21956883                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     21956883                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide     21956883                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     21956883                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide          177                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             177                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide          177                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            177                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide          175                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             175                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide          175                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            175                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
@@ -1283,40 +1274,40 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125400.468927                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125400.468927                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130665.680569                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130665.680569                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 125400.468927                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 125400.468927                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 125400.468927                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 125400.468927                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs            74                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125467.902857                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130635.356950                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130635.356950                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125467.902857                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125467.902857                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs            14                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    8                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                    2                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.250000                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs            7                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41522                       # number of writebacks
-system.iocache.writebacks::total                41522                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          177                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          177                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           41520                       # number of writebacks
+system.iocache.writebacks::total                41520                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::tsunami.ide        41552                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        41552                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide          177                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          177                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide          177                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          177                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13345883                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     13345883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3351820359                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   3351820359                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide     13345883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     13345883                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide     13345883                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     13345883                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide          175                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide          175                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          175                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     13206883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     13206883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   3350560352                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   3350560352                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide     13206883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     13206883                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide     13206883                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     13206883                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1325,199 +1316,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75400.468927                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 75400.468927                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80665.680569                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80665.680569                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75400.468927                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 75400.468927                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75400.468927                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 75400.468927                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80635.356950                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80635.356950                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 75467.902857                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 75467.902857                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   342255                       # number of replacements
-system.l2c.tags.tagsinuse                65190.453062                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3793407                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   407257                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     9.314529                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   342160                       # number of replacements
+system.l2c.tags.tagsinuse                65166.105156                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3684821                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   407166                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     9.049923                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle              12928623000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54971.310995                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3771.999936                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4805.186829                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1123.175084                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      518.780218                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.838796                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.057556                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.073321                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.017138                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.007916                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.994727                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65002                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          176                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         1065                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         4849                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6325                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52587                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.991852                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 36989627                       # Number of tag accesses
-system.l2c.tags.data_accesses                36989627                       # Number of data accesses
-system.l2c.WritebackDirty_hits::writebacks       862671                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          862671                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       732220                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          732220                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data             141                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              87                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 228                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            25                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            26                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                51                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           102038                       # number of ReadExReq hits
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-system.l2c.ReadExReq_hits::total               200524                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        479778                       # number of ReadCleanReq hits
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-system.l2c.ReadCleanReq_hits::total            987892                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       344131                       # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::total           839655                       # number of ReadSharedReq hits
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-system.l2c.demand_hits::cpu0.data              446169                       # number of demand (read+write) hits
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-system.l2c.demand_hits::total                 2028071                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             479778                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             446169                       # number of overall hits
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-system.l2c.overall_hits::total                2028071                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data          2602                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           483                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3085                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           77                       # number of SCUpgradeReq misses
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-system.l2c.SCUpgradeReq_misses::total             171                       # number of SCUpgradeReq misses
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-system.l2c.ReadExReq_misses::total             122622                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        10849                       # number of ReadCleanReq misses
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-system.l2c.ReadCleanReq_misses::total           13452                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       270704                       # number of ReadSharedReq misses
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-system.l2c.demand_misses::cpu0.inst             10849                       # number of demand (read+write) misses
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-system.l2c.overall_misses::total               407937                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu0.data      3090000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      2769500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      5859500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       569500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       892000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      1461500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  13105172500                       # number of ReadExReq miss cycles
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-system.l2c.ReadExReq_miss_latency::total  15660658500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst   1419877000                       # number of ReadCleanReq miss cycles
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-system.l2c.ReadCleanReq_miss_latency::total   1762067500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  33554759000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    151782000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  33706541000                       # number of ReadSharedReq miss cycles
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-system.l2c.demand_miss_latency::cpu1.data   2707268000                       # number of demand (read+write) miss cycles
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-system.l2c.overall_miss_latency::cpu0.inst   1419877000                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::total    51129267000                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       862671                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       862671                       # number of WritebackDirty accesses(hits+misses)
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-system.l2c.WritebackClean_accesses::total       732220                       # number of WritebackClean accesses(hits+misses)
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-system.l2c.overall_accesses::total            2436008                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.948596                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.847368                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.931180                       # miss rate for UpgradeReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.440287                       # miss rate for ReadSharedReq accesses
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-system.l2c.overall_miss_rate::total          0.167461                       # miss rate for overall accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5733.954451                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1899.351702                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7396.103896                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  9489.361702                       # average SCUpgradeReq miss latency
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-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130876.301963                       # average ReadCleanReq miss latency
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-system.l2c.ReadCleanReq_avg_miss_latency::total 130989.258103                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123953.687422                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130959.447800                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 123983.554217                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 130876.301963                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 124771.852488                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::cpu1.data 131913.852751                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 125336.184264                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 130876.301963                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 124771.852488                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::cpu1.data 131913.852751                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 125336.184264                       # average overall miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1526,248 +1517,248 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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 system.l2c.ReadCleanReq_mshr_hits::cpu1.inst           11                       # number of ReadCleanReq MSHR hits
 system.l2c.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
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+system.l2c.demand_mshr_misses::cpu1.inst          939                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         8217                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           408177                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        12505                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       386516                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst          939                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         8217                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          408177                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data         7080                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data          118                       # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total         7198                       # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data        10780                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data         3348                       # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total        14128                       # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data        17860                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data         3466                       # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total        21326                       # number of overall MSHR uncacheable misses
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    213181000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    129464500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    342645500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     66045000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     66671000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total    132716000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  13469504000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    961689500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total  14431193500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   1514992500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    114749500                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total   1629742000                       # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  30951803000                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data     39898500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total  30991701500                       # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst   1514992500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  44421307000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    114749500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1001588000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  47052637000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   1514992500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  44421307000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    114749500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1001588000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  47052637000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1477620500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     23575500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1501196000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2327025500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    750968500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   3077994000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3804646000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    774544000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4579190000                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.948596                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.847368                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.931180                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.754902                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.783333                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.770270                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.502971                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.164311                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.379463                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.022113                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005075                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013423                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.440287                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.002333                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.244587                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.022113                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.455978                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005075                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.033396                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.167457                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.022113                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.455978                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005075                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.033396                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.167457                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71625.864719                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71547.619048                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71613.614263                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71603.896104                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71484.042553                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71538.011696                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116916.776424                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121970.977071                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 117714.916573                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120876.301963                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121495.177469                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120995.647645                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113953.687422                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120959.447800                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113983.554217                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120876.301963                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114771.852488                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121495.177469                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121913.852751                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 115336.242358                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120876.301963                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114771.852488                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121495.177469                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121913.852751                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 115336.242358                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210247.818862                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205537.945493                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208687.456591                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 213090.076895                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223340.468307                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216579.220675                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212038.133313                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 216919.930440                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 213683.562691                       # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941754                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.767857                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.867538                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.959585                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.974895                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.967205                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.480860                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.139642                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.415708                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.018201                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.002829                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.013193                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.291658                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.002953                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260136                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018201                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.330320                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.002829                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.048182                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.172978                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018201                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.330320                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.002829                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.048182                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.172978                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71657.478992                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71685.769657                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71668.165656                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71322.894168                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71535.407725                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71429.494080                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117149.551649                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122041.814721                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 117463.339492                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121150.939624                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122203.940362                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121224.486760                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113986.583879                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118393.175074                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113992.046006                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121150.939624                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114927.472601                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122203.940362                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121892.174760                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 115275.081644                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121150.939624                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114927.472601                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122203.940362                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121892.174760                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 115275.081644                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208703.460452                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208557.377049                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215865.074212                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.614098                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217864.807475                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213026.091825                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223469.128679                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 214723.342399                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq                7199                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292680                       # Transaction distribution
-system.membus.trans_dist::WriteReq              12421                       # Transaction distribution
-system.membus.trans_dist::WriteResp             12421                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       121058                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261934                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4921                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           1238                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            3449                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            122558                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           122429                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        285481                       # Transaction distribution
+system.membus.trans_dist::ReadReq                7198                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292693                       # Transaction distribution
+system.membus.trans_dist::WriteReq              14128                       # Transaction distribution
+system.membus.trans_dist::WriteResp             14128                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       120940                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           261948                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            16888                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          11786                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            7203                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            123166                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           122293                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        285495                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39240                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1166399                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1205639                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124831                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124831                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1330470                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        68786                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31168512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     31237298                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658368                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2658368                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33895666                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3262                       # Total snoops (count)
-system.membus.snoop_fanout::samples            858545                       # Request fanout histogram
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42652                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1193065                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1235717                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124827                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124827                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1360544                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        82434                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     31153280                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     31235714                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2658240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2658240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                33893954                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                            22770                       # Total snoops (count)
+system.membus.snoop_fanout::samples            883282                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  858545    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  883282    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              858545                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            36672500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              883282                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            40488000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1323961648                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1327709899                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2184136804                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2192713302                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy           69798217                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy           69791959                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests      4935792                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2467069                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       374533                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1240                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1179                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops           61                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq               7199                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2152619                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             12421                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            12421                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       983748                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean       732220                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          760785                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            4956                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          1289                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           6245                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           324079                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          324079                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1001367                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1144069                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests      4790563                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2395444                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       362000                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops           1241                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops         1181                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops           60                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq               7198                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2107005                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             14128                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            14128                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       913531                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean       746399                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          756600                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           17054                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         11849                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          28903                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           297620                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          297620                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1019067                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq      1080755                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        41552                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1377223                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2478366                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1357708                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      1834010                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7047307                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     56740736                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     76009449                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     54207360                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     71099081                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              258056626                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          461903                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          2920905                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.131024                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.337667                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1917007                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3544626                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       867499                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       539645                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               6868777                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     78714432                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    118015028                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     34273664                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     18604942                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              249608066                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          484792                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          2873097                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.137110                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.344206                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2538432     86.91%     86.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 382238     13.09%     99.99% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                2479406     86.30%     86.30% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 393455     13.69%     99.99% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                    234      0.01%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3                      1      0.00%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3                      2      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::4                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              3                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2920905                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4346798496                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            2873097                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4223463995                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           299383                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           297883                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         736191563                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1248608962                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1030900979                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy        1802313287                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         767009132                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         499097220                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         969915969                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         293862892                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 0f3bcf1b2..7dba6063a 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/work/gem5/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/work/gem5/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -28,8 +28,8 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/work/gem5/dist/binaries/ts_osfpal
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -279,7 +279,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -302,7 +302,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -325,10 +325,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.tsunami.pciconfig.pio
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
+master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
@@ -355,7 +354,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[29]
+cpu_side=system.iobus.master[27]
 mem_side=system.membus.slave[2]
 
 [system.iocache.tags]
@@ -490,7 +489,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -503,7 +502,7 @@ port=3456
 
 [system.tsunami]
 type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -616,12 +615,12 @@ dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
 hardware_address=00:90:00:00:00:01
+host=system.tsunami.pchip
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 rss=false
 rx_delay=1000000
 rx_fifo_size=524288
@@ -631,9 +630,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.master[28]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[27]
+pio=system.iobus.master[26]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
@@ -1066,14 +1064,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
 eventq_index=0
+host=system.tsunami.pchip
 io_shift=0
 pci_bus=0
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.tsunami
 system=system
-config=system.iobus.master[26]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[25]
 
@@ -1093,25 +1090,20 @@ pio=system.iobus.master[22]
 [system.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=system.clk_domain
+conf_base=8804649402368
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
+pci_dma_base=0
+pci_mem_base=8796093022208
+pci_pio_base=8804615847936
 pio_addr=8802535473152
 pio_latency=100000
+platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.master[1]
 
-[system.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=system.tsunami
-size=16777216
-system=system
-pio=system.iobus.default
-
 [system.tsunami.uart]
 type=Uart8250
 clk_domain=system.clk_domain
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index a1d7247d8..d6487ca92 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:29:48
-gem5 executing on ribera.cs.wisc.edu, pid 29118
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
+gem5 compiled Dec  4 2015 10:28:58
+gem5 started Dec  4 2015 10:54:46
+gem5 executing on e104799-lin, pid 24468
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /work/gem5/dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1941275996000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index df40ca5c9..aff568203 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.941276                       # Nu
 sim_ticks                                1941275996000                       # Number of ticks simulated
 final_tick                               1941275996000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 815122                       # Simulator instruction rate (inst/s)
-host_op_rate                                   815122                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            28164805778                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 368252                       # Number of bytes of host memory used
-host_seconds                                    68.93                       # Real time elapsed on the host
+host_inst_rate                                 921196                       # Simulator instruction rate (inst/s)
+host_op_rate                                   921196                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            31829968739                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 330408                       # Number of bytes of host memory used
+host_seconds                                    60.99                       # Real time elapsed on the host
 sim_insts                                    56182743                       # Number of instructions simulated
 sim_ops                                      56182743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -197,23 +197,23 @@ system.physmem.wrQLenPdf::60                       62                       # Wh
 system.physmem.wrQLenPdf::61                       55                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                       24                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                       51                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        64941                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      509.747124                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     310.189706                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     406.049901                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          15359     23.65%     23.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11448     17.63%     41.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4958      7.63%     48.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3153      4.86%     53.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        64945                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      509.715729                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     310.174215                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     406.042967                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15358     23.65%     23.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11454     17.64%     41.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4958      7.63%     48.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3153      4.85%     53.77% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::512-639         2453      3.78%     57.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         4206      6.48%     64.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1429      2.20%     66.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4205      6.47%     64.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1430      2.20%     66.23% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023         2063      3.18%     69.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19872     30.60%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          64941                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19871     30.60%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          64945                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          5113                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::mean        78.517700                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2951.127642                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2951.127633                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-8191           5110     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
@@ -259,12 +259,12 @@ system.physmem.wrPerTurnAround::200-203             1      0.02%     99.96% # Wr
 system.physmem.wrPerTurnAround::212-215             1      0.02%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::228-231             1      0.02%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5113                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2717940750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               10245709500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     2718840250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               10246609000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                   2007405000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6769.79                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6772.03                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25519.79                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25522.03                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          13.24                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           3.82                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       13.24                       # Average system read bandwidth in MiByte/s
@@ -276,38 +276,38 @@ system.physmem.busUtilWrite                      0.03                       # Da
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        22.09                       # Average write queue length when enqueuing
 system.physmem.readRowHits                     358828                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93473                       # Number of row buffer hits during writes
+system.physmem.writeRowHits                     93469                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   89.38                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  80.72                       # Row buffer hit rate for writes
 system.physmem.avgGap                      3752025.30                       # Average gap between requests
 system.physmem.pageHitRate                      87.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  240362640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  131150250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy                  240377760                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  131158500                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                1565912400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                373358160                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy           126794687760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            71531321220                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1102018756500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1302655548930                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.030615                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1833026995250                       # Time in different power states
+system.physmem_0.actBackEnergy            71534855790                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1102015656000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1302656006370                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.030850                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   1833021874000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     64823460000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     43425441000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     43430562250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  250591320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  136731375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  250606440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  136739625                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                1565639400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                376773120                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy           126794687760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            72715172175                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1100980290750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1302819885900                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.115269                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1831298493250                       # Time in different power states
+system.physmem_1.actBackEnergy            72705843270                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1100988474000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1302818763615                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.114691                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   1831312114000                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     64823460000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     45153943000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     45140322250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -358,10 +358,10 @@ system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # nu
 system.cpu.kern.ipl_good::22                     1935      1.30%     50.69% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73545     49.31%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                149156                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1860509644500     95.84%     95.84% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1860509805500     95.84%     95.84% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::21                94040000      0.00%     95.84% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::22               770515500      0.04%     95.88% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             79901062000      4.12%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             79900901000      4.12%    100.00% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::total         1941275262000                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981752                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
@@ -523,16 +523,16 @@ system.cpu.dcache.demand_misses::cpu.data      1373670                       # n
 system.cpu.dcache.demand_misses::total        1373670                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1373670                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1373670                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  44770870500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  44770870500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  17634139000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  17634139000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    232897500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    232897500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  62405009500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  62405009500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  62405009500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  62405009500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  44771016500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  44771016500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  17634519000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  17634519000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    232810500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    232810500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  62405535500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  62405535500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  62405535500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  62405535500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data      8883757                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total      8883757                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6156599                       # number of WriteReq accesses(hits+misses)
@@ -555,16 +555,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.091332
 system.cpu.dcache.demand_miss_rate::total     0.091332                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.091332                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.091332                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.681715                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.681715                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57944.517100                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 57944.517100                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13503.652809                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13503.652809                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.404078                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45429.404078                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.404078                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45429.404078                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.818247                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.818247                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57945.765753                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 57945.765753                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.608454                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.608454                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.786994                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45429.786994                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.786994                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45429.786994                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,22 +591,22 @@ system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data         9653
 system.cpu.dcache.WriteReq_mshr_uncacheable::total         9653                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        16583                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        16583                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43701528500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43701528500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17329811000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17329811000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    215650500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    215650500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61031339500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  61031339500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61031339500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  61031339500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1527878500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1527878500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43701674500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43701674500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17330191000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  17330191000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    215563500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    215563500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  61031865500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  61031865500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  61031865500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  61031865500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1526978500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1526978500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2172467000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2172467000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3700345500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3700345500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3699445500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3699445500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120370                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120370                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049431                       # mshr miss rate for WriteReq accesses
@@ -617,22 +617,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091332
 system.cpu.dcache.demand_mshr_miss_rate::total     0.091332                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091332                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.091332                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.681715                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.681715                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56944.517100                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56944.517100                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12503.652809                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12503.652809                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.404078                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.404078                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.404078                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.404078                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220473.088023                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220473.088023                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.818247                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.818247                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56945.765753                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56945.765753                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.608454                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.608454                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.786994                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.786994                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.786994                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.786994                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225056.148348                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225056.148348                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223140.897304                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223140.897304                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223086.624857                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223086.624857                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            928920                       # number of replacements
 system.cpu.icache.tags.tagsinuse           506.355618                       # Cycle average of tags in use
@@ -663,12 +663,12 @@ system.cpu.icache.demand_misses::cpu.inst       929591                       # n
 system.cpu.icache.demand_misses::total         929591                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst       929591                       # number of overall misses
 system.cpu.icache.overall_misses::total        929591                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  13686380500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  13686380500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  13686380500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  13686380500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  13686380500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  13686380500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13686841500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  13686841500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  13686841500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  13686841500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  13686841500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  13686841500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     56194577                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     56194577                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     56194577                       # number of demand (read+write) accesses
@@ -681,12 +681,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.016542
 system.cpu.icache.demand_miss_rate::total     0.016542                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.016542                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.016542                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.013132                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14723.013132                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.013132                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14723.013132                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.013132                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14723.013132                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.509049                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14723.509049                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.509049                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14723.509049                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.509049                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14723.509049                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -703,34 +703,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst       929591
 system.cpu.icache.demand_mshr_misses::total       929591                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst       929591                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total       929591                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12756789500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12756789500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12756789500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12756789500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12756789500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12756789500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12757250500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12757250500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12757250500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12757250500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12757250500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12757250500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016542                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016542                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016542                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.016542                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016542                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.016542                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.013132                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.013132                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.013132                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.013132                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.013132                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.013132                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.509049                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.509049                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.509049                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.509049                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.509049                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.509049                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           336393                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65234.360025                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        65234.360010                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3930350                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           401556                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             9.787800                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      10619817000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 55072.826317                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4686.115204                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  5475.418504                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 55072.826279                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4686.115262                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5475.418469                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.840345                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.071504                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.083548                       # Average percentage of cache occupancy
@@ -778,18 +778,18 @@ system.cpu.l2cache.overall_misses::cpu.data       388791                       #
 system.cpu.l2cache.overall_misses::total       401991                       # number of overall misses
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       320500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       320500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14900273000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  14900273000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1727207500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1727207500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33719775000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  33719775000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1727207500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  48620048000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  50347255500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1727207500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  48620048000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  50347255500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14900653000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14900653000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1727668500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1727668500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  33719834000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  33719834000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1727668500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  48620487000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  50348155500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1727668500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  48620487000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  50348155500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       834936                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       834936                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks       928699                       # number of WritebackClean accesses(hits+misses)
@@ -824,18 +824,18 @@ system.cpu.l2cache.overall_miss_rate::cpu.data     0.279525
 system.cpu.l2cache.overall_miss_rate::total     0.173237                       # miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24653.846154                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24653.846154                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127548.989899                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127548.989899                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130849.053030                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130849.053030                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123982.979803                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123982.979803                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130849.053030                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125054.458565                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 125244.733091                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130849.053030                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125054.458565                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 125244.733091                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127552.242767                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127552.242767                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130883.977273                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130883.977273                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123983.196738                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123983.196738                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130883.977273                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125055.587707                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 125246.971947                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130883.977273                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125055.587707                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 125246.971947                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -868,24 +868,24 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        16583
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        16583                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       924500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       924500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13732073000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13732073000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1595207500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1595207500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31000065000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31000065000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1595207500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44732138000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  46327345500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1595207500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44732138000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  46327345500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1441222500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1441222500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13732453000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13732453000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1595668500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1595668500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  31000124000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  31000124000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1595668500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  44732577000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  46328245500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1595668500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  44732577000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  46328245500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1440322500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1440322500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2061377000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2061377000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3502599500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3502599500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3501699500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3501699500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383884                       # mshr miss rate for ReadExReq accesses
@@ -902,24 +902,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279525
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.173237                       # mshr miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71115.384615                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71115.384615                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117548.989899                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117548.989899                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120849.053030                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120849.053030                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113982.979803                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113982.979803                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120849.053030                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115054.458565                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115244.733091                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120849.053030                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115054.458565                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115244.733091                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207968.614719                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207968.614719                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117552.242767                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117552.242767                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120883.977273                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120883.977273                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113983.196738                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113983.196738                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120883.977273                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115055.587707                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115246.971947                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120883.977273                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115055.587707                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115246.971947                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213547.808971                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213547.808971                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211216.275704                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211216.275704                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211162.003256                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211162.003256                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      4639815                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2319473                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
@@ -984,40 +984,34 @@ system.iobus.trans_dist::ReadResp                7103                       # Tr
 system.iobus.trans_dist::WriteReq               51205                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              51205                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5162                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18120                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total        33166                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  116616                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20648                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9060                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total        44588                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2706196                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.reqLayer0.occupancy              5340500                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               371000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy               759000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1031,16 +1025,10 @@ system.iobus.reqLayer24.occupancy             1891500                       # La
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy             6032000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              212000                       # Layer occupancy (ticks)
+system.iobus.reqLayer26.occupancy               82500                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy               82500                       # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy           215014002                       # Layer occupancy (ticks)
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy              131000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           215014002                       # Layer occupancy (ticks)
-system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer30.occupancy               45000                       # Layer occupancy (ticks)
-system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23513000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            41946000                       # Layer occupancy (ticks)
@@ -1183,7 +1171,7 @@ system.membus.reqLayer0.occupancy            30116000                       # La
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy          1287207146                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2143288852                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2143289352                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy           69814679                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
index 2db2ddc0e..ec0c9ed73 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -419,10 +419,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -449,7 +448,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -512,12 +511,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -610,16 +606,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -635,7 +630,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -798,13 +793,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -814,9 +809,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -858,7 +852,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -939,14 +933,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -963,7 +956,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -978,7 +971,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1101,17 +1094,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1163,7 +1158,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1178,7 +1173,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
index 8406c4bfc..ecb1a29da 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
@@ -19,10 +19,6 @@
                 "role": "SLAVE"
             }, 
             "name": "iobus", 
-            "default": {
-                "peer": "system.realview.pciconfig.pio", 
-                "role": "MASTER"
-            }, 
             "forward_latency": 1, 
             "clk_domain": "system.clk_domain", 
             "width": 16, 
@@ -31,6 +27,7 @@
                 "peer": [
                     "system.realview.uart.pio", 
                     "system.realview.realview_io.pio", 
+                    "system.realview.pci_host.pio", 
                     "system.realview.timer0.pio", 
                     "system.realview.timer1.pio", 
                     "system.realview.clcd.pio", 
@@ -38,7 +35,6 @@
                     "system.realview.kmi0.pio", 
                     "system.realview.kmi1.pio", 
                     "system.realview.cf_ctrl.pio", 
-                    "system.realview.cf_ctrl.config", 
                     "system.realview.rtc.pio", 
                     "system.realview.vram.port", 
                     "system.realview.l2x0_fake.pio", 
@@ -53,9 +49,7 @@
                     "system.realview.mmc_fake.pio", 
                     "system.realview.energy_ctrl.pio", 
                     "system.realview.ide.pio", 
-                    "system.realview.ide.config", 
                     "system.realview.ethernet.pio", 
-                    "system.realview.ethernet.config", 
                     "system.iocache.cpu_side"
                 ], 
                 "role": "MASTER"
@@ -64,11 +58,11 @@
             "cxx_class": "NoncoherentXBar", 
             "path": "system.iobus", 
             "type": "NoncoherentXBar", 
-            "use_default_range": true, 
+            "use_default_range": false, 
             "frontend_latency": 2
         }, 
         "symbolfile": "", 
-        "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh", 
+        "readfile": "/work/gem5/outgoing/gem5_2/tests/halt.sh", 
         "have_large_asid_64": false, 
         "phys_addr_range_64": 40, 
         "have_lpae": false, 
@@ -115,7 +109,7 @@
                 "workaround_dma_line_count": true, 
                 "amba_id": 1314816, 
                 "pio": {
-                    "peer": "system.iobus.master[5]", 
+                    "peer": "system.iobus.master[6]", 
                     "role": "SLAVE"
                 }, 
                 "pio_latency": 10000, 
@@ -174,7 +168,23 @@
                 "pio_addr": 471269376, 
                 "type": "PL031"
             }, 
-            "pci_cfg_gen_offsets": false, 
+            "watchdog_fake": {
+                "name": "watchdog_fake", 
+                "pio": {
+                    "peer": "system.iobus.master[17]", 
+                    "role": "SLAVE"
+                }, 
+                "amba_id": 0, 
+                "ignore_access": false, 
+                "pio_latency": 100000, 
+                "clk_domain": "system.clk_domain", 
+                "system": "system", 
+                "eventq_index": 0, 
+                "cxx_class": "AmbaFake", 
+                "path": "system.realview.watchdog_fake", 
+                "pio_addr": 470745088, 
+                "type": "AmbaFake"
+            }, 
             "vgic": {
                 "system": "system", 
                 "name": "vgic", 
@@ -348,7 +358,7 @@
             "timer1": {
                 "name": "timer1", 
                 "pio": {
-                    "peer": "system.iobus.master[3]", 
+                    "peer": "system.iobus.master[4]", 
                     "role": "SLAVE"
                 }, 
                 "amba_id": 1316868, 
@@ -369,7 +379,7 @@
             "timer0": {
                 "name": "timer0", 
                 "pio": {
-                    "peer": "system.iobus.master[2]", 
+                    "peer": "system.iobus.master[3]", 
                     "role": "SLAVE"
                 }, 
                 "amba_id": 1316868, 
@@ -422,6 +432,26 @@
                 "pio_addr": 470286336
             }, 
             "type": "RealView", 
+            "pci_host": {
+                "conf_size": 268435456, 
+                "name": "pci_host", 
+                "conf_device_bits": 16, 
+                "pio": {
+                    "peer": "system.iobus.master[2]", 
+                    "role": "SLAVE"
+                }, 
+                "conf_base": 805306368, 
+                "clk_domain": "system.clk_domain", 
+                "system": "system", 
+                "pci_dma_base": 0, 
+                "platform": "system.realview", 
+                "eventq_index": 0, 
+                "cxx_class": "GenericPciHost", 
+                "path": "system.realview.pci_host", 
+                "pci_pio_base": 0, 
+                "type": "GenericPciHost", 
+                "pci_mem_base": 0
+            }, 
             "lan_fake": {
                 "system": "system", 
                 "ret_data8": 255, 
@@ -617,25 +647,6 @@
                     "type": "RealViewOsc"
                 }
             }, 
-            "pciconfig": {
-                "name": "pciconfig", 
-                "pio": {
-                    "peer": "system.iobus.default", 
-                    "role": "SLAVE"
-                }, 
-                "bus": 0, 
-                "pio_latency": 30000, 
-                "clk_domain": "system.clk_domain", 
-                "system": "system", 
-                "platform": "system.realview", 
-                "eventq_index": 0, 
-                "cxx_class": "PciConfigAll", 
-                "path": "system.realview.pciconfig", 
-                "pio_addr": 0, 
-                "type": "PciConfigAll", 
-                "size": 268435456
-            }, 
-            "pci_cfg_base": 805306368, 
             "path": "system.realview", 
             "vram": {
                 "range": "402653184:436207615", 
@@ -656,7 +667,6 @@
                 }, 
                 "in_addr_map": true
             }, 
-            "pci_io_base": 0, 
             "nvmem": {
                 "range": "0:67108863", 
                 "latency": 30000, 
@@ -685,7 +695,7 @@
                 "vnc": "system.vncserver", 
                 "name": "clcd", 
                 "pio": {
-                    "peer": "system.iobus.master[4]", 
+                    "peer": "system.iobus.master[5]", 
                     "role": "SLAVE"
                 }, 
                 "amba_id": 1315089, 
@@ -723,30 +733,13 @@
                 "pio_addr": 470351872, 
                 "type": "Pl011"
             }, 
-            "watchdog_fake": {
-                "name": "watchdog_fake", 
-                "pio": {
-                    "peer": "system.iobus.master[17]", 
-                    "role": "SLAVE"
-                }, 
-                "amba_id": 0, 
-                "ignore_access": false, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
-                "system": "system", 
-                "eventq_index": 0, 
-                "cxx_class": "AmbaFake", 
-                "path": "system.realview.watchdog_fake", 
-                "pio_addr": 470745088, 
-                "type": "AmbaFake"
-            }, 
             "intrctrl": "system.intrctrl", 
             "kmi1": {
                 "vnc": "system.vncserver", 
                 "name": "kmi1", 
                 "int_delay": 1000000, 
                 "pio": {
-                    "peer": "system.iobus.master[7]", 
+                    "peer": "system.iobus.master[8]", 
                     "role": "SLAVE"
                 }, 
                 "amba_id": 1314896, 
@@ -767,7 +760,7 @@
                 "name": "kmi0", 
                 "int_delay": 1000000, 
                 "pio": {
-                    "peer": "system.iobus.master[6]", 
+                    "peer": "system.iobus.master[7]", 
                     "role": "SLAVE"
                 }, 
                 "amba_id": 1314896, 
@@ -794,7 +787,6 @@
                 "Revision": 0, 
                 "LegacyIOBase": 0, 
                 "pio_latency": 30000, 
-                "platform": "system.realview", 
                 "PXCAPLinkCap": 0, 
                 "CapabilityPtr": 0, 
                 "MSIXCAPBaseOffset": 0, 
@@ -828,6 +820,7 @@
                 "PXCAPDevCap2": 0, 
                 "PXCAPDevCtrl": 0, 
                 "MSICAPMaskBits": 0, 
+                "host": "system.realview.pci_host", 
                 "Command": 1, 
                 "SubClassCode": 1, 
                 "pci_func": 0, 
@@ -862,7 +855,7 @@
                 "config_latency": 20000, 
                 "BAR1Size": 4096, 
                 "pio": {
-                    "peer": "system.iobus.master[8]", 
+                    "peer": "system.iobus.master[9]", 
                     "role": "SLAVE"
                 }, 
                 "pci_dev": 0, 
@@ -871,10 +864,6 @@
                 "clk_domain": "system.clk_domain", 
                 "SubsystemVendorID": 0, 
                 "PMCAPBaseOffset": 0, 
-                "config": {
-                    "peer": "system.iobus.master[9]", 
-                    "role": "SLAVE"
-                }, 
                 "MSICAPPendingBits": 0, 
                 "MSIXTableOffset": 0, 
                 "MSICAPMsgUpperAddr": 0, 
@@ -914,7 +903,6 @@
                 "hardware_address": "00:90:00:00:00:01", 
                 "LegacyIOBase": 0, 
                 "pio_latency": 30000, 
-                "platform": "system.realview", 
                 "PXCAPLinkCap": 0, 
                 "CapabilityPtr": 0, 
                 "MSIXCAPBaseOffset": 0, 
@@ -949,6 +937,7 @@
                 "PXCAPDevCap2": 0, 
                 "PXCAPDevCtrl": 0, 
                 "MSICAPMaskBits": 0, 
+                "host": "system.realview.pci_host", 
                 "Command": 0, 
                 "SubClassCode": 0, 
                 "pci_func": 0, 
@@ -986,7 +975,7 @@
                 "config_latency": 20000, 
                 "BAR1Size": 0, 
                 "pio": {
-                    "peer": "system.iobus.master[25]", 
+                    "peer": "system.iobus.master[24]", 
                     "role": "SLAVE"
                 }, 
                 "pci_dev": 0, 
@@ -997,10 +986,6 @@
                 "clk_domain": "system.clk_domain", 
                 "SubsystemVendorID": 32902, 
                 "PMCAPBaseOffset": 0, 
-                "config": {
-                    "peer": "system.iobus.master[26]", 
-                    "role": "SLAVE"
-                }, 
                 "MSICAPPendingBits": 0, 
                 "MSIXTableOffset": 0, 
                 "MSICAPMsgUpperAddr": 0, 
@@ -1025,7 +1010,6 @@
                 "Revision": 0, 
                 "LegacyIOBase": 0, 
                 "pio_latency": 30000, 
-                "platform": "system.realview", 
                 "PXCAPLinkCap": 0, 
                 "CapabilityPtr": 0, 
                 "MSIXCAPBaseOffset": 0, 
@@ -1061,6 +1045,7 @@
                 "PXCAPDevCap2": 0, 
                 "PXCAPDevCtrl": 0, 
                 "MSICAPMaskBits": 0, 
+                "host": "system.realview.pci_host", 
                 "Command": 0, 
                 "SubClassCode": 1, 
                 "pci_func": 0, 
@@ -1104,10 +1089,6 @@
                 "clk_domain": "system.clk_domain", 
                 "SubsystemVendorID": 0, 
                 "PMCAPBaseOffset": 0, 
-                "config": {
-                    "peer": "system.iobus.master[24]", 
-                    "role": "SLAVE"
-                }, 
                 "MSICAPPendingBits": 0, 
                 "MSIXTableOffset": 0, 
                 "MSICAPMsgUpperAddr": 0, 
@@ -1187,7 +1168,7 @@
         "eventq_index": 0, 
         "iocache": {
             "cpu_side": {
-                "peer": "system.iobus.master[27]", 
+                "peer": "system.iobus.master[25]", 
                 "role": "SLAVE"
             }, 
             "clusivity": "mostly_incl", 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
index 4f7058700..5b276d871 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.783867                       # Nu
 sim_ticks                                2783867052000                       # Number of ticks simulated
 final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 648383                       # Simulator instruction rate (inst/s)
-host_op_rate                                   789303                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            12642549042                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 580896                       # Number of bytes of host memory used
-host_seconds                                   220.20                       # Real time elapsed on the host
+host_inst_rate                                 948377                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1154497                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18491991143                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 582460                       # Number of bytes of host memory used
+host_seconds                                   150.54                       # Real time elapsed on the host
 sim_insts                                   142772879                       # Number of instructions simulated
 sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -589,6 +589,7 @@ system.iobus.trans_dist::WriteReq               59002                       # Tr
 system.iobus.trans_dist::WriteResp              59002                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
@@ -604,16 +605,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105404                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72928                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72928                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  178332                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67833                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
@@ -629,10 +628,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159061                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 540fdcdef..6a7585bd4 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -763,10 +763,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -793,7 +792,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -893,12 +892,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -991,16 +987,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1016,7 +1011,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1179,13 +1174,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1195,9 +1190,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1239,7 +1233,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1320,14 +1314,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1344,7 +1337,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1359,7 +1352,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1482,17 +1475,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1544,7 +1539,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1559,7 +1554,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index d22933e16..581036fd9 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 15:54:29
-gem5 executing on e104799-lin, pid 1782
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 11:24:30
+gem5 executing on e104799-lin, pid 30065
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 5ccc65a5c..583c12b60 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.802895                       # Nu
 sim_ticks                                2802894699500                       # Number of ticks simulated
 final_tick                               2802894699500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 515393                       # Simulator instruction rate (inst/s)
-host_op_rate                                   627998                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9838648327                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 594196                       # Number of bytes of host memory used
-host_seconds                                   284.89                       # Real time elapsed on the host
+host_inst_rate                                 917511                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1117974                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            17514936450                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 594132                       # Number of bytes of host memory used
+host_seconds                                   160.03                       # Real time elapsed on the host
 sim_insts                                   146828240                       # Number of instructions simulated
 sim_ops                                     178908039                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -1116,6 +1116,7 @@ system.iobus.trans_dist::WriteReq               59419                       # Tr
 system.iobus.trans_dist::WriteResp              59419                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56582                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
@@ -1131,16 +1132,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       107876                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  180828                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71526                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
@@ -1156,10 +1155,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       162766                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 2db2ddc0e..ec0c9ed73 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -419,10 +419,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -449,7 +448,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -512,12 +511,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -610,16 +606,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -635,7 +630,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -798,13 +793,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -814,9 +809,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -858,7 +852,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -939,14 +933,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -963,7 +956,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -978,7 +971,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1101,17 +1094,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1163,7 +1158,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1178,7 +1173,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index 7352915d9..e8d7b453f 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 15:54:29
-gem5 executing on e104799-lin, pid 1776
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 11:39:25
+gem5 executing on e104799-lin, pid 31608
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index ed7366920..58a48feae 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.783867                       # Nu
 sim_ticks                                2783867052000                       # Number of ticks simulated
 final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 528399                       # Simulator instruction rate (inst/s)
-host_op_rate                                   643241                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10303020007                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 581016                       # Number of bytes of host memory used
-host_seconds                                   270.20                       # Real time elapsed on the host
+host_inst_rate                                 960961                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1169816                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18737357971                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 579868                       # Number of bytes of host memory used
+host_seconds                                   148.57                       # Real time elapsed on the host
 sim_insts                                   142772879                       # Number of instructions simulated
 sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -589,6 +589,7 @@ system.iobus.trans_dist::WriteReq               59002                       # Tr
 system.iobus.trans_dist::WriteResp              59002                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
@@ -604,16 +605,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105404                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72928                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72928                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  178332                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67833                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
@@ -629,10 +628,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159061                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 58c91ec69..cfa7c7917 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -755,10 +755,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -785,7 +784,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -949,12 +948,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -1047,16 +1043,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -1072,7 +1067,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -1235,13 +1230,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -1251,9 +1246,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1295,7 +1289,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1376,14 +1370,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1400,7 +1393,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1415,7 +1408,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1538,17 +1531,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1600,7 +1595,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1615,7 +1610,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index 4bb037bf9..c04c65778 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 15:54:29
-gem5 executing on e104799-lin, pid 1787
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 13:19:17
+gem5 executing on e104799-lin, pid 9442
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2871819744000 because m5_exit instruction encountered
+Exiting @ tick 2871850306000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index c9db9f143..4d40e792f 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,160 +1,160 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.871820                       # Number of seconds simulated
-sim_ticks                                2871819744000                       # Number of ticks simulated
-final_tick                               2871819744000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.871850                       # Number of seconds simulated
+sim_ticks                                2871850306000                       # Number of ticks simulated
+final_tick                               2871850306000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 357244                       # Simulator instruction rate (inst/s)
-host_op_rate                                   432116                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7805602288                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 614840                       # Number of bytes of host memory used
-host_seconds                                   367.92                       # Real time elapsed on the host
-sim_insts                                   131436334                       # Number of instructions simulated
-sim_ops                                     158983282                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 595194                       # Simulator instruction rate (inst/s)
+host_op_rate                                   719909                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            12993896386                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 612660                       # Number of bytes of host memory used
+host_seconds                                   221.02                       # Real time elapsed on the host
+sim_insts                                   131546959                       # Number of instructions simulated
+sim_ops                                     159110973                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          384                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          1155428                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          1268388                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher      8606976                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst          1178404                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          1267556                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher      8608576                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           151764                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           551380                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher       345088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           129300                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           549908                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher       341632                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12080624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      1155428                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       151764                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1307192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8516928                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             12076912                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst      1178404                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       129300                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1307704                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8530240                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8534492                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           8547804                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker            6                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             26507                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             20338                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher       134484                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             26866                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             20325                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher       134509                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2526                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              8636                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher         5392                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2175                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8613                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher         5338                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                197908                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          133077                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                197850                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          133285                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               137468                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker           156                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               137676                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker           134                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            45                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              402333                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              441667                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher      2997046                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              410329                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data              441373                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher      2997571                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               52846                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              191997                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher       120164                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               45023                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              191482                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher       118959                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              334                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4206609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         402333                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          52846                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             455179                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2965690                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4205272                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         410329                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          45023                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             455352                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2970294                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6102                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2971806                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2965690                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          156                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2976410                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2970294                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          134                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           45                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             402333                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             447769                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher      2997046                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             410329                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data             447475                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher      2997571                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              52846                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             192011                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher       120164                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              45023                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             191496                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher       118959                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             334                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7178416                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        197908                       # Number of read requests accepted
-system.physmem.writeReqs                       137468                       # Number of write requests accepted
-system.physmem.readBursts                      197908                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     137468                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12655744                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     10368                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8547392                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12080624                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8534492                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      162                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                7181682                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        197850                       # Number of read requests accepted
+system.physmem.writeReqs                       137676                       # Number of write requests accepted
+system.physmem.readBursts                      197850                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     137676                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12652352                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10048                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8560960                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12076912                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8547804                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      157                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3895                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          64406                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               11744                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               11857                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               11924                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11590                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               20227                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               11881                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12481                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12857                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12335                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               12711                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              11891                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              11251                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              11484                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              11698                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10879                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10936                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8367                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                8665                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8799                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8189                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7964                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8309                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8959                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8936                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8719                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                9048                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               8437                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               8181                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8223                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7876                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7572                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7309                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs          64578                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               11583                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               11800                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               11971                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11847                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               20098                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11961                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12460                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12487                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               11821                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12495                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              11828                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              11338                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              11476                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              11922                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              11270                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11336                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8288                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8566                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8821                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8522                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7854                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8398                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8910                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8793                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8333                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                8912                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8495                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               8357                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8083                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7998                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7822                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7613                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          22                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2871819304000                       # Total gap between requests
+system.physmem.numWrRetry                          27                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2871849883000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9732                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      28                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  188148                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  188090                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4391                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 133077                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    139055                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     15611                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     10231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8666                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6945                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5399                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4517                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      3779                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3330                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        87                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       68                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       39                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       12                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 133285                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    138613                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     15680                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     10206                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8777                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7036                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5467                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4577                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3802                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3339                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        81                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       56                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       33                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                       15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -184,163 +184,161 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2831                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7850                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7805                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     8728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     8917                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     8948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    10581                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9640                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8066                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7235                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6906                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      243                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      168                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      129                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       82                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       29                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       79                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        87485                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      242.362371                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     136.946957                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     304.393854                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          46305     52.93%     52.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        17523     20.03%     72.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6069      6.94%     79.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3389      3.87%     83.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2483      2.84%     86.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1521      1.74%     88.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          858      0.98%     89.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          952      1.09%     90.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8385      9.58%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          87485                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          6517                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        30.342949                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      586.244331                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           6515     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2732                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4416                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5092                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6151                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6617                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7823                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     8781                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::25                     9011                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::27                     8444                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::49                      127                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::57                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       53                       # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::62                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       80                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        87676                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      241.950454                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     136.764211                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     303.933653                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          46396     52.92%     52.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        17641     20.12%     73.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5908      6.74%     79.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3515      4.01%     83.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2504      2.86%     86.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1565      1.78%     88.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          855      0.98%     89.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          945      1.08%     90.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8347      9.52%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          87676                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6535                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        30.251262                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      585.438505                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6533     99.97%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-4095            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::47104-49151            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            6517                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          6517                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.493018                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.920871                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       12.293044                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            5326     81.72%     81.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             466      7.15%     88.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              68      1.04%     89.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             161      2.47%     92.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              25      0.38%     92.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             129      1.98%     94.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              31      0.48%     95.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              20      0.31%     95.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              32      0.49%     96.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              18      0.28%     96.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               9      0.14%     96.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               7      0.11%     96.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             150      2.30%     98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               6      0.09%     98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               7      0.11%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              24      0.37%     99.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               5      0.08%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               4      0.06%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               3      0.05%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             3      0.05%     99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             3      0.05%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             1      0.02%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.02%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             9      0.14%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147             1      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151             1      0.02%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            6517                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4471540489                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8179277989                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    988730000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       22612.55                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            6535                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6535                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.469013                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.883832                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.598321                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            5330     81.56%     81.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             483      7.39%     88.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              73      1.12%     90.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             153      2.34%     92.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              33      0.50%     92.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             123      1.88%     94.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              36      0.55%     95.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              26      0.40%     95.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              25      0.38%     96.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              15      0.23%     96.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               6      0.09%     96.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.09%     96.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             152      2.33%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               6      0.09%     98.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               2      0.03%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              26      0.40%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               7      0.11%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.02%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95               2      0.03%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.03%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.03%     99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119             1      0.02%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             2      0.03%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            13      0.20%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             3      0.05%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             1      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::244-247             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6535                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4503336233                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8210079983                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    988465000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       22779.44                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  41362.55                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  41529.44                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           4.41                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.98                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        4.21                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.97                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.98                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.13                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.95                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     164996                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     78817                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.44                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  59.01                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8562983.95                       # Average gap between requests
-system.physmem.pageHitRate                      73.59                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  341636400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  186408750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 815575800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                441858240                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           187573201920                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            85932696690                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1647711485250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1923002863050                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.611581                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2740967841659                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     95896320000                       # Time in different power states
+system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.35                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     165103                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     78678                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.51                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  58.81                       # Row buffer hit rate for writes
+system.physmem.avgGap                      8559246.92                       # Average gap between requests
+system.physmem.pageHitRate                      73.54                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  341250840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  186198375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 812814600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                441624960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           187575236160                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            85820448015                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1647828636000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1923006208950                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.605484                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2741162536487                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     95897360000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     34954258341                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     34789668513                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  319750200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  174466875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 726835200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                423565200                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           187573201920                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            85000293540                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1648529382750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1922747495685                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.522659                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2742335596201                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     95896320000                       # Time in different power states
+system.physmem_1.actEnergy                  321579720                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  175465125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 729183000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                425172240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           187575236160                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            84866434740                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1648665489750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1922758560735                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.519251                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2742561244982                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     95897360000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     33587665799                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     33391555518                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
@@ -396,57 +394,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     8797                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                8797                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1607                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         7190                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples         8797                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           8797    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         8797                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         7279                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 12032.971562                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.534367                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  6527.254746                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767         7242     99.49%     99.49% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535           32      0.44%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839            3      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         7279                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                     8830                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                8830                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1617                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         7213                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples         8830                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           8830    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         8830                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         7312                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 12253.145514                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11429.774492                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  6252.045789                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767         7284     99.62%     99.62% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535           24      0.33%     99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839            3      0.04%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total         7312                       # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walksPending::samples   1809726500                       # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::0     1809726500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.dtb.walker.walksPending::total   1809726500                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         5719     78.57%     78.57% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1560     21.43%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         7279                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         8797                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K         5742     78.53%     78.53% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1570     21.47%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         7312                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         8830                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         8797                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7279                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         8830                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         7312                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7279                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        16076                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         7312                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        16142                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    25745693                       # DTB read hits
-system.cpu0.dtb.read_misses                      7581                       # DTB read misses
-system.cpu0.dtb.write_hits                   19246585                       # DTB write hits
-system.cpu0.dtb.write_misses                     1216                       # DTB write misses
+system.cpu0.dtb.read_hits                    25809403                       # DTB read hits
+system.cpu0.dtb.read_misses                      7606                       # DTB read misses
+system.cpu0.dtb.write_hits                   19327142                       # DTB write hits
+system.cpu0.dtb.write_misses                     1224                       # DTB write misses
 system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3751                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3761                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  1856                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                  1861                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      321                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                25753274                       # DTB read accesses
-system.cpu0.dtb.write_accesses               19247801                       # DTB write accesses
+system.cpu0.dtb.read_accesses                25817009                       # DTB read accesses
+system.cpu0.dtb.write_accesses               19328366                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         44992278                       # DTB hits
-system.cpu0.dtb.misses                           8797                       # DTB misses
-system.cpu0.dtb.accesses                     45001075                       # DTB accesses
+system.cpu0.dtb.hits                         45136545                       # DTB hits
+system.cpu0.dtb.misses                           8830                       # DTB misses
+system.cpu0.dtb.accesses                     45145375                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -484,12 +481,12 @@ system.cpu0.itb.walker.walkWaitTime::samples         3674
 system.cpu0.itb.walker.walkWaitTime::0           3674    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkWaitTime::total         3674                       # Table walker wait (enqueue to first request) latency
 system.cpu0.itb.walker.walkCompletionTime::samples         2576                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 12417.119565                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11509.653289                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  6255.531301                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-16383         2268     88.04%     88.04% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-32767          277     10.75%     98.80% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-49151           28      1.09%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 12688.276398                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11839.861434                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  6240.244766                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-16383         2261     87.77%     87.77% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-32767          282     10.95%     98.72% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-49151           30      1.16%     99.88% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::49152-65535            1      0.04%     99.92% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::131072-147455            1      0.04%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walkCompletionTime::163840-180223            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
@@ -507,7 +504,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2576                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2576                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin::total         6250                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   121573780                       # ITB inst hits
+system.cpu0.itb.inst_hits                   121850168                       # ITB inst hits
 system.cpu0.itb.inst_misses                      3674                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -524,172 +521,172 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               121577454                       # ITB inst accesses
-system.cpu0.itb.hits                        121573780                       # DTB hits
+system.cpu0.itb.inst_accesses               121853842                       # ITB inst accesses
+system.cpu0.itb.hits                        121850168                       # DTB hits
 system.cpu0.itb.misses                           3674                       # DTB misses
-system.cpu0.itb.accesses                    121577454                       # DTB accesses
-system.cpu0.numCycles                      5743639488                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                    121853842                       # DTB accesses
+system.cpu0.numCycles                      5743700612                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    1907                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  117757184                       # Number of instructions committed
-system.cpu0.committedOps                    142314769                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            125928094                       # Number of integer alu accesses
+system.cpu0.kern.inst.quiesce                    1892                       # number of quiesce instructions executed
+system.cpu0.committedInsts                  118029542                       # Number of instructions committed
+system.cpu0.committedOps                    142673635                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            126253590                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                 11483                       # Number of float alu accesses
-system.cpu0.num_func_calls                   12772213                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     16007583                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   125928094                       # number of integer instructions
+system.cpu0.num_func_calls                   12792333                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     16043976                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   126253590                       # number of integer instructions
 system.cpu0.num_fp_insts                        11483                       # number of float instructions
-system.cpu0.num_int_register_reads          231704258                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          87445622                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          232324144                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          87654298                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                8771                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               2716                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           515435615                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           53492348                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     46148278                       # number of memory refs
-system.cpu0.num_load_insts                   26004695                       # Number of load instructions
-system.cpu0.num_store_insts                  20143583                       # Number of store instructions
-system.cpu0.num_idle_cycles              5456012961.442100                       # Number of idle cycles
-system.cpu0.num_busy_cycles              287626526.557900                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.050077                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.949923                       # Percentage of idle cycles
-system.cpu0.Branches                         29545337                       # Number of branches fetched
+system.cpu0.num_cc_register_reads           516734560                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           53610723                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     46299073                       # number of memory refs
+system.cpu0.num_load_insts                   26069844                       # Number of load instructions
+system.cpu0.num_store_insts                  20229229                       # Number of store instructions
+system.cpu0.num_idle_cycles              5455076908.366100                       # Number of idle cycles
+system.cpu0.num_busy_cycles              288623703.633900                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.050250                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.949750                       # Percentage of idle cycles
+system.cpu0.Branches                         29603215                       # Number of branches fetched
 system.cpu0.op_class::No_OpClass                 2315      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 99836654     68.33%     68.33% # Class of executed instruction
-system.cpu0.op_class::IntMult                  112117      0.08%     68.41% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              8321      0.01%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.41% # Class of executed instruction
-system.cpu0.op_class::MemRead                26004695     17.80%     86.21% # Class of executed instruction
-system.cpu0.op_class::MemWrite               20143583     13.79%    100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                100054313     68.31%     68.31% # Class of executed instruction
+system.cpu0.op_class::IntMult                  112340      0.08%     68.39% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              8369      0.01%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.39% # Class of executed instruction
+system.cpu0.op_class::MemRead                26069844     17.80%     86.19% # Class of executed instruction
+system.cpu0.op_class::MemWrite               20229229     13.81%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 146107685                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements           732170                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          488.694805                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           44080957                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           732682                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            60.163832                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                 146476410                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements           740882                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          488.760528                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           44216040                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           741394                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            59.639058                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1836359000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   488.694805                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.954482                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.954482                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   488.760528                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.954610                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.954610                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          313                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         90660887                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        90660887                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     24440244                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       24440244                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     18493380                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18493380                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       326498                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       326498                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374202                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       374202                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       371573                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       371573                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     42933624                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        42933624                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     43260122                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       43260122                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       418073                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       418073                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       337261                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       337261                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       133156                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       133156                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22252                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        22252                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19918                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total        19918                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       755334                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        755334                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       888490                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       888490                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5661692500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5661692500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6946372000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   6946372000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    344716000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    344716000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    507189500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total    507189500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1629000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1629000                       # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  12608064500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  12608064500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  12608064500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  12608064500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     24858317                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     24858317                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     18830641                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     18830641                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       459654                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       459654                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       396454                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       396454                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       391491                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       391491                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     43688958                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     43688958                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     44148612                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     44148612                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016818                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.016818                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017910                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.017910                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.289687                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.289687                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056128                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056128                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.050877                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.050877                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.017289                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.017289                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.020125                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.020125                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13542.353847                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13542.353847                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20596.428286                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20596.428286                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15491.461442                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15491.461442                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25463.876895                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25463.876895                       # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses         90957934                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        90957934                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     24496228                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       24496228                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data     18570022                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      18570022                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       327271                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       327271                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       374846                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       374846                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       372508                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       372508                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     43066250                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        43066250                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     43393521                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       43393521                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       423502                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       423502                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       340254                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       340254                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data       133712                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       133712                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22535                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        22535                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data        19849                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total        19849                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       763756                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        763756                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       897468                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       897468                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5717292500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5717292500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6989183500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   6989183500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    344979500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    344979500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data    511150000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total    511150000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      1456500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total      1456500                       # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  12706476000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  12706476000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  12706476000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  12706476000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     24919730                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     24919730                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data     18910276                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     18910276                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       460983                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       460983                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       397381                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       397381                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       392357                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       392357                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     43830006                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     43830006                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     44290989                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     44290989                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.016995                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.016995                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.017993                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.017993                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.290058                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.290058                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056709                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056709                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.050589                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.050589                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.017425                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.017425                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.020263                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.020263                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13500.036600                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13500.036600                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20541.076666                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 20541.076666                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15308.608831                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15308.608831                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25751.927049                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25751.927049                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16692.038886                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16692.038886                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14190.440523                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14190.440523                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16636.826421                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16636.826421                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14158.138229                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14158.138229                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -698,149 +695,147 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       732170                       # number of writebacks
-system.cpu0.dcache.writebacks::total           732170                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25278                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        25278                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data            1                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15552                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15552                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        25279                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        25279                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        25279                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        25279                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       392795                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       392795                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       337260                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       337260                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       106103                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       106103                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6700                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6700                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19918                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total        19918                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       730055                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       730055                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       836158                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       836158                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31819                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31819                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60318                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60318                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4839458000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4839458000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6609064500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6609064500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1736821000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1736821000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    104360500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    104360500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    487321500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    487321500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1579000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1579000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11448522500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  11448522500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13185343500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  13185343500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6629856000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6629856000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5400865000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5400865000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12030721000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12030721000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015801                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015801                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017910                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017910                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.230832                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.230832                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016900                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016900                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.050877                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.050877                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016710                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.016710                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.018940                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018940                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12320.569254                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12320.569254                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19596.348514                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19596.348514                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16369.197855                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16369.197855                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15576.194030                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15576.194030                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24466.387187                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24466.387187                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       740882                       # number of writebacks
+system.cpu0.dcache.writebacks::total           740882                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        25304                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total        25304                       # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        15852                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        15852                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data        25304                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total        25304                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data        25304                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total        25304                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       398198                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       398198                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       340254                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       340254                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       106613                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total       106613                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6683                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6683                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data        19849                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total        19849                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       738452                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       738452                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       845065                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       845065                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        31860                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31860                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        28553                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total        28553                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        60413                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total        60413                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   4887280000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4887280000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6648929500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6648929500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   1745313500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1745313500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    102495000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    102495000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data    491343000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total    491343000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      1414500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      1414500                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  11536209500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  11536209500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13281523000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  13281523000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   6641550500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6641550500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   5414724500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5414724500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  12056275000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12056275000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.015979                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.015979                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.017993                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017993                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231273                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.231273                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.016818                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.016818                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.050589                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.050589                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016848                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.016848                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019080                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.019080                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12273.492082                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12273.492082                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19541.076666                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19541.076666                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16370.550496                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16370.550496                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15336.675146                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15336.675146                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24754.043025                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24754.043025                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15681.726034                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15681.726034                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15768.961727                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15768.961727                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208361.544989                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208361.544989                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189510.684585                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189510.684585                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199454.905667                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199454.905667                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15622.152151                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15622.152151                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15716.569731                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15716.569731                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208460.467671                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208460.467671                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189637.673800                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189637.673800                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199564.249417                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199564.249417                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1146899                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.321434                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          120426360                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1147411                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           104.954859                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1154605                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.321447                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          120695042                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1155117                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           104.487287                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      14862010000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.321434                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.321447                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998675                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.998675                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        244294980                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       244294980                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst    120426360                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      120426360                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    120426360                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       120426360                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    120426360                       # number of overall hits
-system.cpu0.icache.overall_hits::total      120426360                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1147420                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1147420                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1147420                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1147420                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1147420                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1147420                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12257879000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  12257879000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  12257879000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  12257879000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  12257879000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  12257879000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    121573780                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    121573780                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    121573780                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    121573780                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    121573780                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    121573780                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009438                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.009438                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009438                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.009438                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009438                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.009438                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10682.992278                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10682.992278                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10682.992278                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10682.992278                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10682.992278                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10682.992278                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        244855462                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       244855462                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst    120695042                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      120695042                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst    120695042                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       120695042                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst    120695042                       # number of overall hits
+system.cpu0.icache.overall_hits::total      120695042                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1155126                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1155126                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1155126                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1155126                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1155126                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1155126                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  12352499000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  12352499000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  12352499000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  12352499000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  12352499000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  12352499000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst    121850168                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    121850168                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst    121850168                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    121850168                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst    121850168                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    121850168                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.009480                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.009480                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.009480                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.009480                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.009480                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.009480                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10693.637750                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 10693.637750                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10693.637750                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 10693.637750                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10693.637750                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 10693.637750                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -849,331 +844,330 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1146899                       # number of writebacks
-system.cpu0.icache.writebacks::total          1146899                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1147420                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1147420                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      1147420                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1147420                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      1147420                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1147420                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1154605                       # number of writebacks
+system.cpu0.icache.writebacks::total          1154605                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      1155126                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1155126                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst      1155126                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1155126                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst      1155126                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1155126                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11684169000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11684169000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11684169000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11684169000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11684169000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11684169000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11774936000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11774936000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11774936000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11774936000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11774936000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11774936000                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1253876500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1253876500                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1253876500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009438                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009438                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009438                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009438                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009438                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009438                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10182.992278                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10182.992278                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10182.992278                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 10182.992278                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10182.992278                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 10182.992278                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.009480                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009480                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.009480                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009480                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.009480                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009480                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10193.637750                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10193.637750                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10193.637750                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 10193.637750                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10193.637750                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 10193.637750                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.num_hwpf_issued      1935560                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.pfIdentified      1935650                       # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit           78                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.num_hwpf_issued      1946486                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified      1946511                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit           22                       # number of redundant prefetches already in prefetch queue
 system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage       245750                       # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements          273082                       # number of replacements
-system.cpu0.l2cache.tags.tagsinuse       16075.027062                       # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs           3061877                       # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs          289178                       # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs           10.588209                       # Average number of references to valid blocks.
+system.cpu0.l2cache.prefetcher.pfSpanPage       246425                       # number of prefetches not generated due to page crossing
+system.cpu0.l2cache.tags.replacements          273842                       # number of replacements
+system.cpu0.l2cache.tags.tagsinuse       16083.519419                       # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs           3089138                       # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs          289977                       # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs           10.653045                       # Average number of references to valid blocks.
 system.cpu0.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 14584.410184                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     2.385544                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.137322                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1488.094013                       # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks     0.890162                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000146                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_blocks::writebacks 14593.575431                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     0.644607                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.130850                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher  1489.168531                       # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks     0.890721                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000039                       # Average percentage of cache occupancy
 system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000008                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.090826                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total     0.981142                       # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1066                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023            8                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15022                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          271                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          320                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          458                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            4                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3316                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7592                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3838                       # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.065063                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000488                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.916870                       # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses        62794753                       # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses       62794753                       # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        10867                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4767                       # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total         15634                       # number of ReadReq hits
-system.cpu0.l2cache.WritebackDirty_hits::writebacks       501313                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackDirty_hits::total       501313                       # number of WritebackDirty hits
-system.cpu0.l2cache.WritebackClean_hits::writebacks      1348863                       # number of WritebackClean hits
-system.cpu0.l2cache.WritebackClean_hits::total      1348863                       # number of WritebackClean hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.data       238469                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total       238469                       # number of ReadExReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1100555                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadCleanReq_hits::total      1100555                       # number of ReadCleanReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       411293                       # number of ReadSharedReq hits
-system.cpu0.l2cache.ReadSharedReq_hits::total       411293                       # number of ReadSharedReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        10867                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4767                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst      1100555                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.data       649762                       # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::total        1765951                       # number of demand (read+write) hits
-system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        10867                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4767                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.inst      1100555                       # number of overall hits
-system.cpu0.l2cache.overall_hits::cpu0.data       649762                       # number of overall hits
-system.cpu0.l2cache.overall_hits::total       1765951                       # number of overall hits
-system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          177                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker           76                       # number of ReadReq misses
-system.cpu0.l2cache.ReadReq_misses::total          253                       # number of ReadReq misses
-system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55141                       # number of UpgradeReq misses
-system.cpu0.l2cache.UpgradeReq_misses::total        55141                       # number of UpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19907                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeReq_misses::total        19907                       # number of SCUpgradeReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data           11                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.SCUpgradeFailReq_misses::total           11                       # number of SCUpgradeFailReq misses
-system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43650                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadExReq_misses::total        43650                       # number of ReadExReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        46865                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadCleanReq_misses::total        46865                       # number of ReadCleanReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        94305                       # number of ReadSharedReq misses
-system.cpu0.l2cache.ReadSharedReq_misses::total        94305                       # number of ReadSharedReq misses
-system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          177                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.itb.walker           76                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.inst        46865                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::cpu0.data       137955                       # number of demand (read+write) misses
-system.cpu0.l2cache.demand_misses::total       185073                       # number of demand (read+write) misses
-system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          177                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.itb.walker           76                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.inst        46865                       # number of overall misses
-system.cpu0.l2cache.overall_misses::cpu0.data       137955                       # number of overall misses
-system.cpu0.l2cache.overall_misses::total       185073                       # number of overall misses
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      4896500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2045000                       # number of ReadReq miss cycles
-system.cpu0.l2cache.ReadReq_miss_latency::total      6941500                       # number of ReadReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    165758000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.UpgradeReq_miss_latency::total    165758000                       # number of UpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     42773000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     42773000                       # number of SCUpgradeReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1499992                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1499992                       # number of SCUpgradeFailReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2791235000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadExReq_miss_latency::total   2791235000                       # number of ReadExReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3308401000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3308401000                       # number of ReadCleanReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3237666000                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3237666000                       # number of ReadSharedReq miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      4896500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2045000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3308401000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::cpu0.data   6028901000                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.demand_miss_latency::total   9344243500                       # number of demand (read+write) miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      4896500                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2045000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3308401000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::cpu0.data   6028901000                       # number of overall miss cycles
-system.cpu0.l2cache.overall_miss_latency::total   9344243500                       # number of overall miss cycles
-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        11044                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4843                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total        15887                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::writebacks       501313                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackDirty_accesses::total       501313                       # number of WritebackDirty accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::writebacks      1348863                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.WritebackClean_accesses::total      1348863                       # number of WritebackClean accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55141                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total        55141                       # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19907                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total        19907                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data           11                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeFailReq_accesses::total           11                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       282119                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadExReq_accesses::total       282119                       # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1147420                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadCleanReq_accesses::total      1147420                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       505598                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.ReadSharedReq_accesses::total       505598                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        11044                       # number of demand (read+write) accesses
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-system.cpu0.l2cache.demand_accesses::cpu0.inst      1147420                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data       787717                       # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total      1951024                       # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        11044                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4843                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst      1147420                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data       787717                       # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total      1951024                       # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.016027                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.015693                       # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total     0.015925                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.090892                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total     0.981660                       # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022         1031                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023            3                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15101                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          282                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          325                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4          414                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            1                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         3285                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7655                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         3857                       # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.062927                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000183                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.921692                       # Percentage of cache occupancy per task id
+system.cpu0.l2cache.tags.tag_accesses        63340451                       # Number of tag accesses
+system.cpu0.l2cache.tags.data_accesses       63340451                       # Number of data accesses
+system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        11537                       # number of ReadReq hits
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+system.cpu0.l2cache.ReadReq_hits::total         16516                       # number of ReadReq hits
+system.cpu0.l2cache.WritebackDirty_hits::writebacks       507696                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackDirty_hits::total       507696                       # number of WritebackDirty hits
+system.cpu0.l2cache.WritebackClean_hits::writebacks      1358751                       # number of WritebackClean hits
+system.cpu0.l2cache.WritebackClean_hits::total      1358751                       # number of WritebackClean hits
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data       241135                       # number of ReadExReq hits
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+system.cpu0.l2cache.ReadCleanReq_hits::total      1108628                       # number of ReadCleanReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       416937                       # number of ReadSharedReq hits
+system.cpu0.l2cache.ReadSharedReq_hits::total       416937                       # number of ReadSharedReq hits
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+system.cpu0.l2cache.demand_hits::cpu0.inst      1108628                       # number of demand (read+write) hits
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+system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4979                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.inst      1108628                       # number of overall hits
+system.cpu0.l2cache.overall_hits::cpu0.data       658072                       # number of overall hits
+system.cpu0.l2cache.overall_hits::total       1783216                       # number of overall hits
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+system.cpu0.l2cache.ReadReq_misses::total          252                       # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        55316                       # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total        55316                       # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        19844                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total        19844                       # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data        43803                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total        43803                       # number of ReadExReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        46498                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadCleanReq_misses::total        46498                       # number of ReadCleanReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data        94557                       # number of ReadSharedReq misses
+system.cpu0.l2cache.ReadSharedReq_misses::total        94557                       # number of ReadSharedReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          155                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.itb.walker           97                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.inst        46498                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data       138360                       # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total       185110                       # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          155                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.itb.walker           97                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.inst        46498                       # number of overall misses
+system.cpu0.l2cache.overall_misses::cpu0.data       138360                       # number of overall misses
+system.cpu0.l2cache.overall_misses::total       185110                       # number of overall misses
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker      4266000                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker      2540500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.ReadReq_miss_latency::total      6806500                       # number of ReadReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    172322000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.UpgradeReq_miss_latency::total    172322000                       # number of UpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data     43306000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeReq_miss_latency::total     43306000                       # number of SCUpgradeReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      1349997                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      1349997                       # number of SCUpgradeFailReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data   2802544000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadExReq_miss_latency::total   2802544000                       # number of ReadExReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst   3338173500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadCleanReq_miss_latency::total   3338173500                       # number of ReadCleanReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data   3246573500                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.ReadSharedReq_miss_latency::total   3246573500                       # number of ReadSharedReq miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker      4266000                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker      2540500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.inst   3338173500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::cpu0.data   6049117500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.demand_miss_latency::total   9394097500                       # number of demand (read+write) miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker      4266000                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker      2540500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.inst   3338173500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::cpu0.data   6049117500                       # number of overall miss cycles
+system.cpu0.l2cache.overall_miss_latency::total   9394097500                       # number of overall miss cycles
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        11692                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         5076                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total        16768                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::writebacks       507696                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackDirty_accesses::total       507696                       # number of WritebackDirty accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::writebacks      1358751                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.WritebackClean_accesses::total      1358751                       # number of WritebackClean accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        55316                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total        55316                       # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        19844                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total        19844                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       284938                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_accesses::total       284938                       # number of ReadExReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1155126                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadCleanReq_accesses::total      1155126                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       511494                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.ReadSharedReq_accesses::total       511494                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        11692                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         5076                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.inst      1155126                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.data       796432                       # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total      1968326                       # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        11692                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         5076                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst      1155126                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data       796432                       # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total      1968326                       # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.013257                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.019110                       # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total     0.015029                       # miss rate for ReadReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.154722                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total     0.154722                       # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.040844                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.040844                       # miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.186522                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.186522                       # miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.016027                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.015693                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040844                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.175133                       # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total     0.094859                       # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.016027                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.015693                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040844                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.175133                       # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total     0.094859                       # miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27663.841808                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26907.894737                       # average ReadReq miss latency
-system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27436.758893                       # average ReadReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3006.075334                       # average UpgradeReq miss latency
-system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3006.075334                       # average UpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2148.641181                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2148.641181                       # average SCUpgradeReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 136362.909091                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 136362.909091                       # average SCUpgradeFailReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63945.819015                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63945.819015                       # average ReadExReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 70594.281447                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 70594.281447                       # average ReadCleanReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34331.859392                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34331.859392                       # average ReadSharedReq miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27663.841808                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26907.894737                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 70594.281447                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43701.939038                       # average overall miss latency
-system.cpu0.l2cache.demand_avg_miss_latency::total 50489.501440                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27663.841808                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26907.894737                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 70594.281447                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43701.939038                       # average overall miss latency
-system.cpu0.l2cache.overall_avg_miss_latency::total 50489.501440                       # average overall miss latency
-system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.153728                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total     0.153728                       # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.040254                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.040254                       # miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.184864                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.184864                       # miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.013257                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.019110                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040254                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.173725                       # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total     0.094044                       # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.013257                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.019110                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040254                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.173725                       # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total     0.094044                       # miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27522.580645                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26190.721649                       # average ReadReq miss latency
+system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27009.920635                       # average ReadReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3115.228867                       # average UpgradeReq miss latency
+system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3115.228867                       # average UpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  2182.322112                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  2182.322112                       # average SCUpgradeReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 269999.400000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 269999.400000                       # average SCUpgradeFailReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63980.640595                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63980.640595                       # average ReadExReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71791.765237                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71791.765237                       # average ReadCleanReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34334.565394                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34334.565394                       # average ReadSharedReq miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27522.580645                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26190.721649                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71791.765237                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43720.132264                       # average overall miss latency
+system.cpu0.l2cache.demand_avg_miss_latency::total 50748.730485                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27522.580645                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26190.721649                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71791.765237                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43720.132264                       # average overall miss latency
+system.cpu0.l2cache.overall_avg_miss_latency::total 50748.730485                       # average overall miss latency
+system.cpu0.l2cache.blocked_cycles::no_mshrs           32                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
+system.cpu0.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
 system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu0.l2cache.avg_blocked_cycles::no_mshrs           32                       # average number of cycles each access was blocked
 system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks       231742                       # number of writebacks
-system.cpu0.l2cache.writebacks::total          231742                       # number of writebacks
-system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1776                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadExReq_mshr_hits::total         1776                       # number of ReadExReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           53                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           53                       # number of ReadSharedReq MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1829                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.demand_mshr_hits::total         1829                       # number of demand (read+write) MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1829                       # number of overall MSHR hits
-system.cpu0.l2cache.overall_mshr_hits::total         1829                       # number of overall MSHR hits
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          177                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           76                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.ReadReq_mshr_misses::total          253                       # number of ReadReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       265136                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.HardPFReq_mshr_misses::total       265136                       # number of HardPFReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55141                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55141                       # number of UpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19907                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19907                       # number of SCUpgradeReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data           11                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total           11                       # number of SCUpgradeFailReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41874                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadExReq_mshr_misses::total        41874                       # number of ReadExReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        46865                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        46865                       # number of ReadCleanReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        94252                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        94252                       # number of ReadSharedReq MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          177                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker           76                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        46865                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::cpu0.data       136126                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.demand_mshr_misses::total       183244                       # number of demand (read+write) MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          177                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker           76                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        46865                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.data       136126                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       265136                       # number of overall MSHR misses
-system.cpu0.l2cache.overall_mshr_misses::total       448380                       # number of overall MSHR misses
+system.cpu0.l2cache.writebacks::writebacks       232272                       # number of writebacks
+system.cpu0.l2cache.writebacks::total          232272                       # number of writebacks
+system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data         1851                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadExReq_mshr_hits::total         1851                       # number of ReadExReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data           57                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.ReadSharedReq_mshr_hits::total           57                       # number of ReadSharedReq MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::cpu0.data         1908                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.demand_mshr_hits::total         1908                       # number of demand (read+write) MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::cpu0.data         1908                       # number of overall MSHR hits
+system.cpu0.l2cache.overall_mshr_hits::total         1908                       # number of overall MSHR hits
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker          155                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker           97                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.ReadReq_mshr_misses::total          252                       # number of ReadReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       264558                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.HardPFReq_mshr_misses::total       264558                       # number of HardPFReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data        55316                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.UpgradeReq_mshr_misses::total        55316                       # number of UpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data        19844                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total        19844                       # number of SCUpgradeReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data        41952                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadExReq_mshr_misses::total        41952                       # number of ReadExReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst        46498                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadCleanReq_mshr_misses::total        46498                       # number of ReadCleanReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data        94500                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.ReadSharedReq_mshr_misses::total        94500                       # number of ReadSharedReq MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker          155                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker           97                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.inst        46498                       # number of demand (read+write) MSHR misses
+system.cpu0.l2cache.demand_mshr_misses::cpu0.data       136452                       # number of demand (read+write) MSHR misses
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+system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker          155                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker           97                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.inst        46498                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.data       136452                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       264558                       # number of overall MSHR misses
+system.cpu0.l2cache.overall_mshr_misses::total       447760                       # number of overall MSHR misses
 system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst         9022                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31819                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40841                       # number of ReadReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28499                       # number of WriteReq MSHR uncacheable
-system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28499                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        31860                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        40882                       # number of ReadReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        28553                       # number of WriteReq MSHR uncacheable
+system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        28553                       # number of WriteReq MSHR uncacheable
 system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60318                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69340                       # number of overall MSHR uncacheable misses
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3834500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1589000                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      5423500                       # number of ReadReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  20369501795                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  20369501795                       # number of HardPFReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1428543500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1428543500                       # number of UpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    338252500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    338252500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1199992                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1199992                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2362760500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2362760500                       # number of ReadExReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3027211000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3027211000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2665459000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2665459000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3834500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1589000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3027211000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5028219500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.demand_mshr_miss_latency::total   8060854000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3834500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1589000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3027211000                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5028219500                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  20369501795                       # number of overall MSHR miss cycles
-system.cpu0.l2cache.overall_mshr_miss_latency::total  28430355795                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        60413                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        69435                       # number of overall MSHR uncacheable misses
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker      3336000                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker      1958500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_latency::total      5294500                       # number of ReadReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  20402670222                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  20402670222                       # number of HardPFReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   1434169000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   1434169000                       # number of UpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data    342730000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total    342730000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      1097997                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      1097997                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data   2366849000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total   2366849000                       # number of ReadExReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst   3059185500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total   3059185500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data   2673492000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total   2673492000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker      3336000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker      1958500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst   3059185500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data   5040341000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total   8104821000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker      3336000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker      1958500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst   3059185500                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data   5040341000                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  20402670222                       # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total  28507491222                       # number of overall MSHR miss cycles
 system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6374890500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7561102000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5187001000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5187001000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   6386259500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   7572471000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data   5200454500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total   5200454500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1186211500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11561891500                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12748103000                       # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.016027                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.015693                       # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.015925                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data  11586714000                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total  12772925500                       # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.013257                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.019110                       # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.015029                       # mshr miss rate for ReadReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for UpgradeReq accesses
@@ -1182,117 +1176,117 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data            1
 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
 system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.148427                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.148427                       # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.040844                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040844                       # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.186417                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.186417                       # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.016027                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.015693                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.040844                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.172811                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total     0.093922                       # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.016027                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.015693                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.040844                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.172811                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.147232                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.147232                       # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.040254                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040254                       # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.184753                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.184753                       # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.013257                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.019110                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.040254                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.171329                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total     0.093075                       # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.013257                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.019110                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.040254                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.171329                       # mshr miss rate for overall accesses
 system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229818                       # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21436.758893                       # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76826.616510                       # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25907.101794                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25907.101794                       # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16991.636108                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16991.636108                       # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109090.181818                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109090.181818                       # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56425.478817                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56425.478817                       # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 64594.281447                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64594.281447                       # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28280.131987                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28280.131987                       # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 64594.281447                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36937.980254                       # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43989.729541                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 64594.281447                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36937.980254                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510                       # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63406.833032                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total     0.227483                       # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21009.920635                       # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77119.838455                       # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25926.838528                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25926.838528                       # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17271.215481                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17271.215481                       # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 219599.400000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 219599.400000                       # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56418.025362                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56418.025362                       # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65791.765237                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65791.765237                       # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28290.920635                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28290.920635                       # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65791.765237                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36938.564477                       # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44239.806334                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65791.765237                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36938.564477                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455                       # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63666.900174                       # average overall mshr miss latency
 system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200348.549609                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185135.084841                       # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.421278                       # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.421278                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200447.567483                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185227.508439                       # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182133.383532                       # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182133.383532                       # average WriteReq mshr uncacheable latency
 system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191682.275606                       # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183849.192385                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191791.733567                       # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183955.145100                       # average overall mshr uncacheable latency
 system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests      3903345                       # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1968246                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        28892                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops       321222                       # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       317069                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         4153                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq         63874                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp      1765403                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq        28499                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp        28499                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackDirty       733576                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WritebackClean      1348863                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict       190188                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq       312390                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq        85764                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        42077                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp       112758                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           45                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           84                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq       301102                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp       297729                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1147420                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq       574776                       # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq         3316                       # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3438002                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2673168                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        11871                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        27031                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total          6150072                       # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    145478520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    101119646                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        19372                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        44176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total         246661714                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops                     988213                       # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples      2981714                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean       0.123543                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev      0.333265                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests      3935499                       # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1983981                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        29039                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops       320941                       # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       317478                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         3463                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq         63971                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp      1779248                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq        28553                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp        28553                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackDirty       740475                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WritebackClean      1358751                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict       190136                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq       311790                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq        85728                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        41989                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp       112642                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           35                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp           72                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq       304006                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp       300714                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1155126                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq       580591                       # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq         3227                       # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3461069                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2699694                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12104                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        27735                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total          6200602                       # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    146461624                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    102248167                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        20304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        46768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total         248776863                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops                     987005                       # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples      2997932                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean       0.122336                       # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev      0.331180                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0           2617497     87.78%     87.78% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1            360064     12.08%     99.86% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2              4153      0.14%    100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0           2634639     87.88%     87.88% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1            359830     12.00%     99.88% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2              3463      0.12%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total       2981714                       # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy    3884130992                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total       2997932                       # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy    3917122496                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy    115184885                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy    115533329                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy   1730152000                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy   1741711000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy   1265237983                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy   1278424980                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu0.toL2Bus.respLayer2.occupancy      7028000                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy     15993487                       # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy     16050485                       # Layer occupancy (ticks)
 system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -1323,57 +1317,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     2355                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                2355                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          481                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1874                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         2355                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           2355    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         2355                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         1709                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11678.466940                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11002.721261                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  5695.537695                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-16383         1565     91.57%     91.57% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-32767          135      7.90%     99.47% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                     2352                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                2352                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          487                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1865                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         2352                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           2352    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         2352                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         1706                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 11672.919109                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11010.748339                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  5645.878722                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-16383         1558     91.32%     91.32% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-32767          139      8.15%     99.47% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::32768-49151            5      0.29%     99.77% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::49152-65535            3      0.18%     99.94% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::147456-163839            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         1709                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         1706                       # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walksPending::samples  -1207257828                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0    -1207257828    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total  -1207257828                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         1228     71.85%     71.85% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M          481     28.15%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         1709                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         2355                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K         1219     71.45%     71.45% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          487     28.55%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         1706                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         2352                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         2355                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1709                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         2352                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1706                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1709                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total         4064                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1706                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         4058                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     3323284                       # DTB read hits
-system.cpu1.dtb.read_misses                      1962                       # DTB read misses
-system.cpu1.dtb.write_hits                    2909831                       # DTB write hits
-system.cpu1.dtb.write_misses                      393                       # DTB write misses
+system.cpu1.dtb.read_hits                     3283088                       # DTB read hits
+system.cpu1.dtb.read_misses                      1969                       # DTB read misses
+system.cpu1.dtb.write_hits                    2849660                       # DTB write hits
+system.cpu1.dtb.write_misses                      383                       # DTB write misses
 system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1652                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1653                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   231                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   218                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      124                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 3325246                       # DTB read accesses
-system.cpu1.dtb.write_accesses                2910224                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 3285057                       # DTB read accesses
+system.cpu1.dtb.write_accesses                2850043                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          6233115                       # DTB hits
-system.cpu1.dtb.misses                           2355                       # DTB misses
-system.cpu1.dtb.accesses                      6235470                       # DTB accesses
+system.cpu1.dtb.hits                          6132748                       # DTB hits
+system.cpu1.dtb.misses                           2352                       # DTB misses
+system.cpu1.dtb.accesses                      6135100                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1411,20 +1405,21 @@ system.cpu1.itb.walker.walkWaitTime::samples         1376
 system.cpu1.itb.walker.walkWaitTime::0           1376    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkWaitTime::total         1376                       # Table walker wait (enqueue to first request) latency
 system.cpu1.itb.walker.walkCompletionTime::samples          819                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11895.604396                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 11259.508648                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  5169.477869                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191          116     14.16%     14.16% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287          583     71.18%     85.35% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383           72      8.79%     94.14% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479            8      0.98%     95.12% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575            1      0.12%     95.24% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671           22      2.69%     97.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767            7      0.85%     98.78% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.12%     98.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959            5      0.61%     99.51% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055            1      0.12%     99.63% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::49152-53247            3      0.37%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 11896.825397                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11258.920739                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  5216.232861                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191          112     13.68%     13.68% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287          592     72.28%     85.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383           66      8.06%     94.02% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479            7      0.85%     94.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575            2      0.24%     95.12% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671           24      2.93%     98.05% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767            5      0.61%     98.66% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863            1      0.12%     98.78% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959            6      0.73%     99.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055            2      0.24%     99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::49152-53247            1      0.12%     99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::57344-61439            1      0.12%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::total          819                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples  -1208095828                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0    -1208095828    100.00%    100.00% # Table walker pending requests distribution
@@ -1439,7 +1434,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          819                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::total          819                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin::total         2195                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    13877832                       # ITB inst hits
+system.cpu1.itb.inst_hits                    13713445                       # ITB inst hits
 system.cpu1.itb.inst_misses                      1376                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -1456,171 +1451,171 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                13879208                       # ITB inst accesses
-system.cpu1.itb.hits                         13877832                       # DTB hits
+system.cpu1.itb.inst_accesses                13714821                       # ITB inst accesses
+system.cpu1.itb.hits                         13713445                       # DTB hits
 system.cpu1.itb.misses                           1376                       # DTB misses
-system.cpu1.itb.accesses                     13879208                       # DTB accesses
-system.cpu1.numCycles                      5742698802                       # number of cpu cycles simulated
+system.cpu1.itb.accesses                     13714821                       # DTB accesses
+system.cpu1.numCycles                      5742759797                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2717                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   13679150                       # Number of instructions committed
-system.cpu1.committedOps                     16668513                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             15113644                       # Number of integer alu accesses
+system.cpu1.kern.inst.quiesce                    2753                       # number of quiesce instructions executed
+system.cpu1.committedInsts                   13517417                       # Number of instructions committed
+system.cpu1.committedOps                     16437338                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             14911378                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     913162                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1492467                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    15113644                       # number of integer instructions
+system.cpu1.num_func_calls                     901174                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1468136                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    14911378                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads           27463830                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          10666857                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           27063131                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          10536793                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            61159895                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes            5174219                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      6447631                       # number of memory refs
-system.cpu1.num_load_insts                    3428751                       # Number of load instructions
-system.cpu1.num_store_insts                   3018880                       # Number of store instructions
-system.cpu1.num_idle_cycles              5696160545.959164                       # Number of idle cycles
-system.cpu1.num_busy_cycles              46538256.040836                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.008104                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.991896                       # Percentage of idle cycles
-system.cpu1.Branches                          2456488                       # Number of branches fetched
+system.cpu1.num_cc_register_reads            60344215                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes            5099594                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      6349896                       # number of memory refs
+system.cpu1.num_load_insts                    3389045                       # Number of load instructions
+system.cpu1.num_store_insts                   2960851                       # Number of store instructions
+system.cpu1.num_idle_cycles              5696813538.222876                       # Number of idle cycles
+system.cpu1.num_busy_cycles              45946258.777124                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.008001                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.991999                       # Percentage of idle cycles
+system.cpu1.Branches                          2418797                       # Number of branches fetched
 system.cpu1.op_class::No_OpClass                   24      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 10511910     61.88%     61.88% # Class of executed instruction
-system.cpu1.op_class::IntMult                   24272      0.14%     62.03% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.03% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              3188      0.02%     62.04% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.04% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.04% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.04% # Class of executed instruction
-system.cpu1.op_class::MemRead                 3428751     20.18%     82.23% # Class of executed instruction
-system.cpu1.op_class::MemWrite                3018880     17.77%    100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 10377527     61.94%     61.94% # Class of executed instruction
+system.cpu1.op_class::IntMult                   24492      0.15%     62.08% # Class of executed instruction
+system.cpu1.op_class::IntDiv                        0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::FloatAdd                      0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::FloatCmp                      0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::FloatCvt                      0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::FloatMult                     0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::FloatDiv                      0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt                     0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdAdd                       0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc                    0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdAlu                       0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdCmp                       0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdCvt                       0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdMisc                      0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdMult                      0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc                   0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdShift                     0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc                  0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt                      0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd                  0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu                  0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp                  0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt                  0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv                  0      0.00%     62.08% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              3134      0.02%     62.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult                 0      0.00%     62.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     62.10% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     62.10% # Class of executed instruction
+system.cpu1.op_class::MemRead                 3389045     20.23%     82.33% # Class of executed instruction
+system.cpu1.op_class::MemWrite                2960851     17.67%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  16987025                       # Class of executed instruction
-system.cpu1.dcache.tags.replacements           147592                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          468.392474                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            6004450                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           147942                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            40.586514                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     106294932000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   468.392474                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.914829                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.914829                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          318                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           32                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.683594                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         12646180                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        12646180                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3055213                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3055213                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2743263                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2743263                       # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41902                       # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total        41902                       # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69872                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        69872                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61606                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        61606                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5798476                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5798476                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      5840378                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5840378                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       112221                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       112221                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        79294                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        79294                       # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data        24421                       # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total        24421                       # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16601                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        16601                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23085                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        23085                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       191515                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        191515                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       215936                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       215936                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1751790500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1751790500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2724343500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   2724343500                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    320772500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    320772500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    629240500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total    629240500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3762500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3762500                       # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   4476134000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   4476134000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   4476134000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   4476134000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3167434                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3167434                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2822557                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2822557                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        66323                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total        66323                       # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        86473                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        86473                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84691                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        84691                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      5989991                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      5989991                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      6056314                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      6056314                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035430                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.035430                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028093                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.028093                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.368213                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total     0.368213                       # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.191979                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.191979                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.272579                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.272579                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031973                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.031973                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035655                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.035655                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15610.184368                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15610.184368                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34357.498676                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 34357.498676                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19322.480573                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19322.480573                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27257.548191                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27257.548191                       # average StoreCondReq miss latency
+system.cpu1.op_class::total                  16755073                       # Class of executed instruction
+system.cpu1.dcache.tags.replacements           144073                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          473.219627                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            5912733                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           144418                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            40.941801                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     106295131000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   473.219627                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.924257                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.924257                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          345                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          319                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           26                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.673828                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         12441829                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        12441829                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3018165                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3018165                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2685196                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2685196                       # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data        41245                       # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total        41245                       # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        69563                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        69563                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        61182                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        61182                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5703361                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5703361                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      5744606                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5744606                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       110713                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       110713                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        77621                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        77621                       # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data        23905                       # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total        23905                       # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        16417                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        16417                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        23076                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        23076                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       188334                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        188334                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       212239                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       212239                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1730591500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1730591500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2713528000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2713528000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    316809000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    316809000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data    632764000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total    632764000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3307000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3307000                       # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   4444119500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   4444119500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   4444119500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   4444119500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3128878                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3128878                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2762817                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2762817                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        65150                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total        65150                       # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        85980                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        85980                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        84258                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        84258                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      5891695                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      5891695                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      5956845                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      5956845                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035384                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.035384                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028095                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.028095                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.366922                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total     0.366922                       # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.190940                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.190940                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.273873                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.273873                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031966                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.031966                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035629                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.035629                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15631.330557                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15631.330557                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34958.683861                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 34958.683861                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19297.618322                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19297.618322                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27420.870168                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27420.870168                       # average StoreCondReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23372.237162                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23372.237162                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20728.984514                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 20728.984514                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23597.011161                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 23597.011161                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20939.221821                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20939.221821                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1629,102 +1624,102 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       147592                       # number of writebacks
-system.cpu1.dcache.writebacks::total           147592                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          221                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          221                       # number of ReadReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11676                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11676                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          221                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          221                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          221                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          221                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       112000                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       112000                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        79294                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        79294                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23950                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total        23950                       # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4925                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4925                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23085                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        23085                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       191294                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       191294                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       215244                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       215244                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3081                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3081                       # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2423                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2423                       # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5504                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5504                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1626671000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1626671000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2645049500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2645049500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    437326000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    437326000                       # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     90573500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     90573500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    606189500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    606189500                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3728500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3728500                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4271720500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   4271720500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4709046500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   4709046500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    439448500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    439448500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    303112500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    303112500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    742561000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    742561000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035360                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035360                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028093                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028093                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.361112                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.361112                       # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056954                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056954                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.272579                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.272579                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031936                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.031936                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035540                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.035540                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14523.848214                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14523.848214                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33357.498676                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33357.498676                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18259.958246                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18259.958246                       # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18390.558376                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18390.558376                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26259.021009                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26259.021009                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       144073                       # number of writebacks
+system.cpu1.dcache.writebacks::total           144073                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          168                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          168                       # number of ReadReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data        11530                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total        11530                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          168                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          168                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          168                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          168                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       110545                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       110545                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        77621                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        77621                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data        23508                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total        23508                       # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         4887                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         4887                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        23076                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        23076                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       188166                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       188166                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       211674                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       211674                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data         3107                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total         3107                       # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data         2430                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total         2430                       # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data         5537                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total         5537                       # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1611627000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1611627000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2635907000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2635907000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    421753500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total    421753500                       # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     88480500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     88480500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data    609718000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total    609718000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      3277000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      3277000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   4247534000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   4247534000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   4669287500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   4669287500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    430617000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    430617000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    292641500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    292641500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    723258500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    723258500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035331                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035331                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028095                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028095                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.360829                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.360829                       # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056839                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056839                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.273873                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.273873                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031937                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.031937                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.035535                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.035535                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14578.922611                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14578.922611                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33958.683861                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33958.683861                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17940.849923                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17940.849923                       # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18105.279312                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18105.279312                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26422.170220                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26422.170220                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22330.655954                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22330.655954                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21877.713200                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21877.713200                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142631.775398                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142631.775398                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125098.018985                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125098.018985                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134912.972384                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134912.972384                       # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22573.334184                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22573.334184                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22058.861740                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22058.861740                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138595.751529                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 138595.751529                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 120428.600823                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 120428.600823                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 130622.810186                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 130622.810186                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements           463636                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.311121                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           13413679                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           464148                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            28.899573                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     106195496500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.311121                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.replacements           461792                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          498.311266                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           13251136                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           462304                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            28.663252                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     106195905000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.311266                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973264                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.973264                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -1732,44 +1727,44 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2          387
 system.cpu1.icache.tags.age_task_id_blocks_1024::3          118                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         28219802                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        28219802                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     13413679                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       13413679                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     13413679                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        13413679                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     13413679                       # number of overall hits
-system.cpu1.icache.overall_hits::total       13413679                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       464148                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       464148                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       464148                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        464148                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       464148                       # number of overall misses
-system.cpu1.icache.overall_misses::total       464148                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4215419500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4215419500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4215419500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4215419500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4215419500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4215419500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     13877827                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     13877827                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     13877827                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     13877827                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     13877827                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     13877827                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.033445                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.033445                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.033445                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.033445                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.033445                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.033445                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  9082.058955                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total  9082.058955                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  9082.058955                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total  9082.058955                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  9082.058955                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total  9082.058955                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         27889184                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        27889184                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     13251136                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       13251136                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     13251136                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        13251136                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     13251136                       # number of overall hits
+system.cpu1.icache.overall_hits::total       13251136                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       462304                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       462304                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       462304                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        462304                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       462304                       # number of overall misses
+system.cpu1.icache.overall_misses::total       462304                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4149723500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4149723500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4149723500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4149723500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4149723500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4149723500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     13713440                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     13713440                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     13713440                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     13713440                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     13713440                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     13713440                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.033712                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.033712                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.033712                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.033712                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.033712                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.033712                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst  8976.179094                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total  8976.179094                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst  8976.179094                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total  8976.179094                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst  8976.179094                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total  8976.179094                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1778,451 +1773,442 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks       463636                       # number of writebacks
-system.cpu1.icache.writebacks::total           463636                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       464148                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       464148                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       464148                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       464148                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       464148                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       464148                       # number of overall MSHR misses
+system.cpu1.icache.writebacks::writebacks       461792                       # number of writebacks
+system.cpu1.icache.writebacks::total           461792                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       462304                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       462304                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       462304                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       462304                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       462304                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       462304                       # number of overall MSHR misses
 system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.ReadReq_mshr_uncacheable::total          177                       # number of ReadReq MSHR uncacheable
 system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.overall_mshr_uncacheable_misses::total          177                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3983345500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3983345500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3983345500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3983345500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3983345500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3983345500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3918571500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   3918571500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3918571500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   3918571500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3918571500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   3918571500                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst     23546500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total     23546500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst     23546500                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total     23546500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.033445                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.033445                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.033445                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.033445                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.033445                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.033445                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8582.058955                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8582.058955                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8582.058955                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total  8582.058955                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8582.058955                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total  8582.058955                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.033712                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.033712                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.033712                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.033712                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.033712                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.033712                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst  8476.179094                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total  8476.179094                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst  8476.179094                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total  8476.179094                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst  8476.179094                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total  8476.179094                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued       118070                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified       118078                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.num_hwpf_issued       106104                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified       106112                       # number of prefetch candidates identified
 system.cpu1.l2cache.prefetcher.pfBufferHit            7                       # number of redundant prefetches already in prefetch queue
 system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage        50218                       # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements           30957                       # number of replacements
-system.cpu1.l2cache.tags.tagsinuse       14956.632857                       # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs           1041724                       # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs           46098                       # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs           22.598030                       # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage        50448                       # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements           30131                       # number of replacements
+system.cpu1.l2cache.tags.tagsinuse       14949.290291                       # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs           1034569                       # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs           45193                       # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs           22.892240                       # Average number of references to valid blocks.
 system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 14500.509333                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     1.321768                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.084166                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   452.717591                       # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks     0.885041                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000081                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000127                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.027632                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total     0.912880                       # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022          931                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023           37                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14173                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            2                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           38                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          891                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks 14514.476865                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     2.312401                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.041451                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   430.459574                       # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks     0.885893                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000141                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000125                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.026273                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_percent::total     0.912432                       # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1022          971                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023           32                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14059                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::3           54                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          913                       # Occupied blocks per task id
 system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            5                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           32                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          396                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1648                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12129                       # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.056824                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.002258                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.865051                       # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses        21133576                       # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses       21133576                       # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         2455                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1470                       # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total          3925                       # number of ReadReq hits
-system.cpu1.l2cache.WritebackDirty_hits::writebacks        91545                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackDirty_hits::total        91545                       # number of WritebackDirty hits
-system.cpu1.l2cache.WritebackClean_hits::writebacks       509576                       # number of WritebackClean hits
-system.cpu1.l2cache.WritebackClean_hits::total       509576                       # number of WritebackClean hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data        18096                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total        18096                       # number of ReadExReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       455478                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadCleanReq_hits::total       455478                       # number of ReadCleanReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        77072                       # number of ReadSharedReq hits
-system.cpu1.l2cache.ReadSharedReq_hits::total        77072                       # number of ReadSharedReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         2455                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1470                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst       455478                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data        95168                       # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total         554571                       # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         2455                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1470                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst       455478                       # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data        95168                       # number of overall hits
-system.cpu1.l2cache.overall_hits::total        554571                       # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          345                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          297                       # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total          642                       # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28981                       # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total        28981                       # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23084                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total        23084                       # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.SCUpgradeFailReq_misses::total            1                       # number of SCUpgradeFailReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32217                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total        32217                       # number of ReadExReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst         8670                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadCleanReq_misses::total         8670                       # number of ReadCleanReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        63803                       # number of ReadSharedReq misses
-system.cpu1.l2cache.ReadSharedReq_misses::total        63803                       # number of ReadSharedReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          345                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker          297                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst         8670                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data        96020                       # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total       105332                       # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          345                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker          297                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst         8670                       # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data        96020                       # number of overall misses
-system.cpu1.l2cache.overall_misses::total       105332                       # number of overall misses
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      7035000                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      5940500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.ReadReq_miss_latency::total     12975500                       # number of ReadReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     66105500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.UpgradeReq_miss_latency::total     66105500                       # number of UpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     54747500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     54747500                       # number of SCUpgradeReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3677500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3677500                       # number of SCUpgradeFailReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1649546500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadExReq_miss_latency::total   1649546500                       # number of ReadExReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    528187000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadCleanReq_miss_latency::total    528187000                       # number of ReadCleanReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1437865000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1437865000                       # number of ReadSharedReq miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      7035000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      5940500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.inst    528187000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::cpu1.data   3087411500                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.demand_miss_latency::total   3628574000                       # number of demand (read+write) miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      7035000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      5940500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.inst    528187000                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::cpu1.data   3087411500                       # number of overall miss cycles
-system.cpu1.l2cache.overall_miss_latency::total   3628574000                       # number of overall miss cycles
-system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         2800                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1767                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.ReadReq_accesses::total         4567                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::writebacks        91545                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackDirty_accesses::total        91545                       # number of WritebackDirty accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::writebacks       509576                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.WritebackClean_accesses::total       509576                       # number of WritebackClean accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28981                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total        28981                       # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23084                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total        23084                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            1                       # number of SCUpgradeFailReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        50313                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadExReq_accesses::total        50313                       # number of ReadExReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       464148                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadCleanReq_accesses::total       464148                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       140875                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.ReadSharedReq_accesses::total       140875                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         2800                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1767                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.inst       464148                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::cpu1.data       191188                       # number of demand (read+write) accesses
-system.cpu1.l2cache.demand_accesses::total       659903                       # number of demand (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         2800                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1767                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.inst       464148                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::cpu1.data       191188                       # number of overall (read+write) accesses
-system.cpu1.l2cache.overall_accesses::total       659903                       # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.123214                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.168081                       # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total     0.140574                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           27                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          390                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         1365                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4        12304                       # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.059265                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001953                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.858093                       # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses        20957142                       # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses       20957142                       # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         2443                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1453                       # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total          3896                       # number of ReadReq hits
+system.cpu1.l2cache.WritebackDirty_hits::writebacks        89055                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackDirty_hits::total        89055                       # number of WritebackDirty hits
+system.cpu1.l2cache.WritebackClean_hits::writebacks       506752                       # number of WritebackClean hits
+system.cpu1.l2cache.WritebackClean_hits::total       506752                       # number of WritebackClean hits
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data        16650                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total        16650                       # number of ReadExReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       453968                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadCleanReq_hits::total       453968                       # number of ReadCleanReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        75407                       # number of ReadSharedReq hits
+system.cpu1.l2cache.ReadSharedReq_hits::total        75407                       # number of ReadSharedReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         2443                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1453                       # number of demand (read+write) hits
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+system.cpu1.l2cache.demand_hits::cpu1.data        92057                       # number of demand (read+write) hits
+system.cpu1.l2cache.demand_hits::total         549921                       # number of demand (read+write) hits
+system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         2443                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1453                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.inst       453968                       # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data        92057                       # number of overall hits
+system.cpu1.l2cache.overall_hits::total        549921                       # number of overall hits
+system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          349                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          301                       # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total          650                       # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28928                       # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total        28928                       # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        23076                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total        23076                       # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data        32043                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total        32043                       # number of ReadExReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst         8336                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadCleanReq_misses::total         8336                       # number of ReadCleanReq misses
+system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        63533                       # number of ReadSharedReq misses
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+system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          349                       # number of demand (read+write) misses
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+system.cpu1.l2cache.demand_misses::cpu1.data        95576                       # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total       104562                       # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          349                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.itb.walker          301                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.inst         8336                       # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data        95576                       # number of overall misses
+system.cpu1.l2cache.overall_misses::total       104562                       # number of overall misses
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker      7078500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker      6021500                       # number of ReadReq miss cycles
+system.cpu1.l2cache.ReadReq_miss_latency::total     13100000                       # number of ReadReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data     62132500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.UpgradeReq_miss_latency::total     62132500                       # number of UpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data     59033500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeReq_miss_latency::total     59033500                       # number of SCUpgradeReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      3231500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      3231500                       # number of SCUpgradeFailReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data   1646554500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadExReq_miss_latency::total   1646554500                       # number of ReadExReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst    475139500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadCleanReq_miss_latency::total    475139500                       # number of ReadCleanReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data   1418811000                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.ReadSharedReq_miss_latency::total   1418811000                       # number of ReadSharedReq miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker      7078500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker      6021500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.inst    475139500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::cpu1.data   3065365500                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.demand_miss_latency::total   3553605000                       # number of demand (read+write) miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker      7078500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker      6021500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.inst    475139500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::cpu1.data   3065365500                       # number of overall miss cycles
+system.cpu1.l2cache.overall_miss_latency::total   3553605000                       # number of overall miss cycles
+system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         2792                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1754                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.ReadReq_accesses::total         4546                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::writebacks        89055                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackDirty_accesses::total        89055                       # number of WritebackDirty accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::writebacks       506752                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.WritebackClean_accesses::total       506752                       # number of WritebackClean accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28928                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total        28928                       # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        23076                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total        23076                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        48693                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadExReq_accesses::total        48693                       # number of ReadExReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       462304                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadCleanReq_accesses::total       462304                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       138940                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.ReadSharedReq_accesses::total       138940                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         2792                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1754                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.inst       462304                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::cpu1.data       187633                       # number of demand (read+write) accesses
+system.cpu1.l2cache.demand_accesses::total       654483                       # number of demand (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         2792                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1754                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.inst       462304                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::cpu1.data       187633                       # number of overall (read+write) accesses
+system.cpu1.l2cache.overall_accesses::total       654483                       # number of overall (read+write) accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.171608                       # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total     0.142983                       # miss rate for ReadReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.640332                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total     0.640332                       # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.018679                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.018679                       # miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.452905                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.452905                       # miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.123214                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.168081                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.018679                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.502228                       # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total     0.159617                       # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.123214                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.168081                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.018679                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.502228                       # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total     0.159617                       # miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20391.304348                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20001.683502                       # average ReadReq miss latency
-system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20211.059190                       # average ReadReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2280.994445                       # average UpgradeReq miss latency
-system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2280.994445                       # average UpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2371.664356                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2371.664356                       # average SCUpgradeReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data      3677500                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total      3677500                       # average SCUpgradeFailReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51201.120526                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51201.120526                       # average ReadExReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60921.222607                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60921.222607                       # average ReadCleanReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22536.009279                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22536.009279                       # average ReadSharedReq miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20391.304348                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20001.683502                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60921.222607                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32153.837742                       # average overall miss latency
-system.cpu1.l2cache.demand_avg_miss_latency::total 34448.923404                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20391.304348                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20001.683502                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60921.222607                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32153.837742                       # average overall miss latency
-system.cpu1.l2cache.overall_avg_miss_latency::total 34448.923404                       # average overall miss latency
-system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.658062                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total     0.658062                       # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.018031                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.018031                       # miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.457269                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.457269                       # miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.171608                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.018031                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.509377                       # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total     0.159763                       # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.125000                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.171608                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.018031                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.509377                       # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total     0.159763                       # miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20282.234957                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20004.983389                       # average ReadReq miss latency
+system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20153.846154                       # average ReadReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  2147.832550                       # average UpgradeReq miss latency
+system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  2147.832550                       # average UpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  2558.220662                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  2558.220662                       # average SCUpgradeReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total          inf                       # average SCUpgradeFailReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51385.778485                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51385.778485                       # average ReadExReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 56998.500480                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 56998.500480                       # average ReadCleanReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22331.874774                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22331.874774                       # average ReadSharedReq miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20282.234957                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20004.983389                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 56998.500480                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32072.544363                       # average overall miss latency
+system.cpu1.l2cache.demand_avg_miss_latency::total 33985.625753                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20282.234957                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20004.983389                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 56998.500480                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32072.544363                       # average overall miss latency
+system.cpu1.l2cache.overall_avg_miss_latency::total 33985.625753                       # average overall miss latency
+system.cpu1.l2cache.blocked_cycles::no_mshrs           32                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
+system.cpu1.l2cache.blocked::no_mshrs               1                       # number of cycles access was blocked
 system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
-system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           32                       # average number of cycles each access was blocked
 system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
 system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks        25761                       # number of writebacks
-system.cpu1.l2cache.writebacks::total           25761                       # number of writebacks
-system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           70                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.ReadExReq_mshr_hits::total           70                       # number of ReadExReq MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::cpu1.data           70                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::cpu1.data           70                       # number of overall MSHR hits
-system.cpu1.l2cache.overall_mshr_hits::total           70                       # number of overall MSHR hits
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker          345                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker          297                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.ReadReq_mshr_misses::total          642                       # number of ReadReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        20837                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.HardPFReq_mshr_misses::total        20837                       # number of HardPFReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data        28981                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28981                       # number of UpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data        23084                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23084                       # number of SCUpgradeReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            1                       # number of SCUpgradeFailReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        32147                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadExReq_mshr_misses::total        32147                       # number of ReadExReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst         8670                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadCleanReq_mshr_misses::total         8670                       # number of ReadCleanReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        63803                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        63803                       # number of ReadSharedReq MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker          345                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          297                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.inst         8670                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::cpu1.data        95950                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.demand_mshr_misses::total       105262                       # number of demand (read+write) MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker          345                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker          297                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.inst         8670                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.data        95950                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher        20837                       # number of overall MSHR misses
-system.cpu1.l2cache.overall_mshr_misses::total       126099                       # number of overall MSHR misses
+system.cpu1.l2cache.writebacks::writebacks        25259                       # number of writebacks
+system.cpu1.l2cache.writebacks::total           25259                       # number of writebacks
+system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data           80                       # number of ReadExReq MSHR hits
+system.cpu1.l2cache.ReadExReq_mshr_hits::total           80                       # number of ReadExReq MSHR hits
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+system.cpu1.l2cache.ReadReq_mshr_misses::total          650                       # number of ReadReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher        18771                       # number of HardPFReq MSHR misses
+system.cpu1.l2cache.HardPFReq_mshr_misses::total        18771                       # number of HardPFReq MSHR misses
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+system.cpu1.l2cache.UpgradeReq_mshr_misses::total        28928                       # number of UpgradeReq MSHR misses
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+system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total        23076                       # number of SCUpgradeReq MSHR misses
+system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data        31963                       # number of ReadExReq MSHR misses
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+system.cpu1.l2cache.ReadCleanReq_mshr_misses::total         8336                       # number of ReadCleanReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data        63533                       # number of ReadSharedReq MSHR misses
+system.cpu1.l2cache.ReadSharedReq_mshr_misses::total        63533                       # number of ReadSharedReq MSHR misses
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+system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker          301                       # number of demand (read+write) MSHR misses
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+system.cpu1.l2cache.overall_mshr_misses::total       123253                       # number of overall MSHR misses
 system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst          177                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3081                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3258                       # number of ReadReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2423                       # number of WriteReq MSHR uncacheable
-system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2423                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data         3107                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.ReadReq_mshr_uncacheable::total         3284                       # number of ReadReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data         2430                       # number of WriteReq MSHR uncacheable
+system.cpu1.l2cache.WriteReq_mshr_uncacheable::total         2430                       # number of WriteReq MSHR uncacheable
 system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst          177                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5504                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5681                       # number of overall MSHR uncacheable misses
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4965000                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4158500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      9123500                       # number of ReadReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    915724625                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    915724625                       # number of HardPFReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    582445000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    582445000                       # number of UpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    432971000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    432971000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3473500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3473500                       # number of SCUpgradeFailReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1449025500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1449025500                       # number of ReadExReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    476167000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    476167000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1055047000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total   1055047000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4965000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4158500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst    476167000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2504072500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.demand_mshr_miss_latency::total   2989363000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4965000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4158500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst    476167000                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2504072500                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    915724625                       # number of overall MSHR miss cycles
-system.cpu1.l2cache.overall_mshr_miss_latency::total   3905087625                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data         5537                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.overall_mshr_uncacheable_misses::total         5714                       # number of overall MSHR uncacheable misses
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker      4984500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker      4215500                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_latency::total      9200000                       # number of ReadReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher    917123117                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total    917123117                       # number of HardPFReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data    588451500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total    588451500                       # number of UpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data    436537000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total    436537000                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      3051500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      3051500                       # number of SCUpgradeFailReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   1446140000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   1446140000                       # number of ReadExReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst    425123500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total    425123500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data   1037613000                       # number of ReadSharedReq MSHR miss cycles
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+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker      4984500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker      4215500                       # number of demand (read+write) MSHR miss cycles
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+system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data   2483753000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.demand_mshr_miss_latency::total   2918076500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker      4984500                       # number of overall MSHR miss cycles
+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker      4215500                       # number of overall MSHR miss cycles
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+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data   2483753000                       # number of overall MSHR miss cycles
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+system.cpu1.l2cache.overall_mshr_miss_latency::total   3835199617                       # number of overall MSHR miss cycles
 system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    414452000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    436671000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    284931500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    284931500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data    405408000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total    427627000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data    274409000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total    274409000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst     22219000                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    699383500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    721602500                       # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.123214                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.168081                       # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.140574                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data    679817000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total    702036000                       # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.171608                       # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.142983                       # mshr miss rate for ReadReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.638940                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.638940                       # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018679                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.018679                       # mshr miss rate for ReadCleanReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.452905                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.452905                       # mshr miss rate for ReadSharedReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.123214                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.168081                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.018679                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.501862                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total     0.159511                       # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.123214                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.168081                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.018679                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.501862                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.656419                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.656419                       # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018031                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.018031                       # mshr miss rate for ReadCleanReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.457269                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.457269                       # mshr miss rate for ReadSharedReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.171608                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.018031                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.508951                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total     0.159641                       # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.125000                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.171608                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.018031                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.508951                       # mshr miss rate for overall accesses
 system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total     0.191087                       # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14211.059190                       # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43947.047320                       # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20097.477658                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.477658                       # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18756.324727                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18756.324727                       # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data      3473500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total      3473500                       # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45074.983669                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45074.983669                       # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54921.222607                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54921.222607                       # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16536.009279                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16536.009279                       # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54921.222607                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26097.681084                       # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28399.260892                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54921.222607                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26097.681084                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320                       # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30968.426593                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total     0.188321                       # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14153.846154                       # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48858.511374                       # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.935149                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.935149                       # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.360028                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18917.360028                       # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total          inf                       # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45244.188593                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45244.188593                       # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50998.500480                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50998.500480                       # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16331.874774                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16331.874774                       # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 50998.500480                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26008.974198                       # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27928.987768                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 50998.500480                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26008.974198                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374                       # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31116.480873                       # average overall mshr miss latency
 system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134518.662772                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134030.386740                       # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117594.510937                       # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117594.510937                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130482.137110                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130215.286236                       # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112925.514403                       # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 112925.514403                       # average WriteReq mshr uncacheable latency
 system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127068.223110                       # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127020.330928                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 122777.135633                       # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 122862.443122                       # average overall mshr uncacheable latency
 system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests      1323663                       # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests       668360                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        10107                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops       169443                       # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       166760                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2683                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq         10105                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp       652363                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq         2423                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp         2423                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackDirty       118404                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WritebackClean       509576                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict        86260                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq        25020                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq        70278                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40907                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp        84739                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           51                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           84                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq        57602                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp        55059                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq       464148                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq       215012                       # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq           32                       # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1383984                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       718041                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         4385                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         7029                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total          2113439                       # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     58847556                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     24276952                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7068                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        11200                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total          83142776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops                     355785                       # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples       998697                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean       0.187513                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev      0.397146                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_filter.tot_requests      1312846                       # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests       662941                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        10057                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops       166384                       # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       164278                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2106                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq         10119                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp       648543                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq         2430                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp         2430                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackDirty       115438                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WritebackClean       506752                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict        85166                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq        22864                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq        70245                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        40855                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp        84598                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           42                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp           72                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq        55915                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp        53326                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq       462304                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq       211564                       # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq           31                       # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1378500                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       707096                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         4372                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side         7009                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total          2096977                       # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     58614596                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     23813135                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         7016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        11168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total          82445915                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops                     350196                       # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples       987919                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean       0.185835                       # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev      0.394416                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0            814111     81.52%     81.52% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1            181903     18.21%     99.73% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2              2683      0.27%    100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0            806435     81.63%     81.63% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1            179378     18.16%     99.79% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2              2106      0.21%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total        998697                       # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy    1278018500                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total        987919                       # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy    1267256999                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy     79432929                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy     79126203                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy    696399000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy    693633000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy    317143500                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy    311803500                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu1.toL2Bus.respLayer2.occupancy      2618000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy      4229000                       # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy      4217000                       # Layer occupancy (ticks)
 system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.iobus.trans_dist::ReadReq                31021                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               31021                       # Transaction distribution
+system.iobus.trans_dist::ReadReq                31009                       # Transaction distribution
+system.iobus.trans_dist::ReadResp               31009                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59425                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59425                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56620                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
@@ -2238,16 +2224,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       107934                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72958                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total        72958                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  180892                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72934                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total        72934                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  180868                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71564                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
@@ -2263,26 +2247,25 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       162814                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321272                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      2321272                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2484086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             48741500                       # Layer occupancy (ticks)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total      2321176                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total                  2483990                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy             48738000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               106500                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                32500                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               322000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                16000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                32500                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                93000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               609500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy                93500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer8.occupancy               610000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               23500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
@@ -2303,60 +2286,54 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6155500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6150500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              165000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            32045500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            32044000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           186301036                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              119500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186329030                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               37500                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            84733000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            36782000                       # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy            36758000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                36461                       # number of replacements
-system.iocache.tags.tagsinuse               14.380003                       # Cycle average of tags in use
+system.iocache.tags.replacements                36433                       # number of replacements
+system.iocache.tags.tagsinuse                1.018273                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                36477                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                36449                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         290757542000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide    14.380003                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.898750                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.898750                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         290654223000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.018273                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.063642                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.063642                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               328311                       # Number of tag accesses
-system.iocache.tags.data_accesses              328311                       # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide          255                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              255                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               328203                       # Number of tag accesses
+system.iocache.tags.data_accesses              328203                       # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide          243                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              243                       # number of ReadReq misses
 system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ide          255                       # number of demand (read+write) misses
-system.iocache.demand_misses::total               255                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide          255                       # number of overall misses
-system.iocache.overall_misses::total              255                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     32882376                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     32882376                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4738851654                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4738851654                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     32882376                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     32882376                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     32882376                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     32882376                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide          255                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            255                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide          243                       # number of demand (read+write) misses
+system.iocache.demand_misses::total               243                       # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide          243                       # number of overall misses
+system.iocache.overall_misses::total              243                       # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide     31405376                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     31405376                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4738596660                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4738596660                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     31405376                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     31405376                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     31405376                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     31405376                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::realview.ide          243                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            243                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ide          255                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total             255                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ide          255                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total            255                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::realview.ide          243                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total             243                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::realview.ide          243                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total            243                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
@@ -2365,40 +2342,40 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 128950.494118                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 128950.494118                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130820.772250                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130820.772250                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 128950.494118                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 128950.494118                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 128950.494118                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 128950.494118                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           818                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 129240.230453                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 129240.230453                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130813.732884                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130813.732884                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 129240.230453                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 129240.230453                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 129240.230453                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 129240.230453                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           816                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   99                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   79                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     8.262626                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.329114                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           36206                       # number of writebacks
-system.iocache.writebacks::total                36206                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          255                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          255                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           36190                       # number of writebacks
+system.iocache.writebacks::total                36190                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::realview.ide          243                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          243                       # number of ReadReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::realview.ide        36224                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total        36224                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide          255                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total          255                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide          255                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total          255                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     20132376                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     20132376                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2927651654                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2927651654                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     20132376                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     20132376                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     20132376                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     20132376                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::realview.ide          243                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total          243                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide          243                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total          243                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     19255376                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     19255376                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2927396660                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2927396660                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     19255376                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     19255376                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     19255376                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     19255376                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -2407,304 +2384,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78950.494118                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 78950.494118                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80820.772250                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80820.772250                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 78950.494118                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 78950.494118                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 78950.494118                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 78950.494118                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79240.230453                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 79240.230453                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80813.732884                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80813.732884                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 79240.230453                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 79240.230453                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 79240.230453                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 79240.230453                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                   123906                       # number of replacements
-system.l2c.tags.tagsinuse                62994.829806                       # Cycle average of tags in use
-system.l2c.tags.total_refs                     421817                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   187980                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.243946                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   123618                       # number of replacements
+system.l2c.tags.tagsinuse                63093.840837                       # Cycle average of tags in use
+system.l2c.tags.total_refs                     421259                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   187589                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.245649                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   13459.681359                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.946988                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.042686                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     7381.464495                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2783.395152                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35774.545550                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.954481                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1451.828957                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      405.858901                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1734.111238                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.205378                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000045                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000001                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.112632                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.042471                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.545876                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   13244.114990                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     3.878668                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.996497                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     7731.277102                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2849.874177                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36272.088123                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.954483                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1120.568935                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      367.321258                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  1502.766604                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.202089                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000059                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.117970                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.043486                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.553468                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.022153                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.006193                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.026460                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.961225                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022        31889                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        32181                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2          315                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3         5132                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4        26438                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
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 system.l2c.overall_miss_latency::cpu0.itb.walker       272000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   2300069500                       # number of overall miss cycles
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+system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  19570272761                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker       132500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    317997500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1142931500                       # number of overall miss cycles
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-system.l2c.overall_miss_latency::total    26969112308                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       257503                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       257503                       # number of WritebackDirty accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1.data         4191                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           45784                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data         2719                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data         2161                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          4880                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data        15249                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data         9160                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            24409                       # number of ReadExReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::cpu1.data         5777                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::total       308353                       # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.demand_accesses::total              332762                       # number of demand (read+write) accesses
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-system.l2c.overall_accesses::total             332762                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.225495                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.536387                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.253953                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.216624                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.590930                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.382377                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.733622                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.855459                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.779344                       # miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.066667                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.158446                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.136403                       # miss rate for ReadSharedReq accesses
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-system.l2c.ReadSharedReq_miss_rate::total     0.549844                       # miss rate for ReadSharedReq accesses
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-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.066667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.027397                       # miss rate for overall accesses
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-system.l2c.overall_miss_rate::total          0.566678                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3187.013541                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2643.905694                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  3082.007397                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7791.171477                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1386.452623                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  3408.092176                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145426.566550                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130947.932619                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 139462.492772                       # average ReadExReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker       135500                       # average ReadSharedReq miss latency
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+system.l2c.overall_accesses::total             331753                       # number of overall (read+write) accesses
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+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.571713                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.258497                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.236462                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.595227                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.396113                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.727011                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.854019                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.774680                       # miss rate for ReadExReq accesses
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+system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.739093                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.062500                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.242442                       # miss rate for ReadSharedReq accesses
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+system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.639818                       # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total     0.551798                       # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.068966                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.021277                       # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.062500                       # miss rate for demand accesses
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+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.068966                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.062500                       # miss rate for overall accesses
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+system.l2c.overall_miss_rate::cpu1.data      0.587155                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.639818                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.568254                       # miss rate for overall accesses
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3613.839750                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2180.652174                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  3337.069689                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6075.572519                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1904.689864                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  3286.545271                       # average SCUpgradeReq miss latency
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 system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker       136000                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131455.078013                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136214.027354                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172                       # average ReadSharedReq miss latency
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 system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker       132500                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134119.569802                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 148253.172589                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 143418.997251                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       135500                       # average overall miss latency
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+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139159.574468                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421                       # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 143633.857613                       # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       137250                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker       136000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 131455.078013                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 141358.315863                       # average overall miss latency
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 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
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-system.l2c.demand_avg_miss_latency::total 143019.861738                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker       136000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 131455.078013                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 141358.315863                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker       132500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 134119.569802                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 132529.162801                       # average overall miss latency
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-system.l2c.overall_avg_miss_latency::total 143019.861738                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::cpu1.data 131870.335929                       # average overall miss latency
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+system.l2c.overall_avg_miss_latency::total 143193.886001                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2713,271 +2690,274 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               96871                       # number of writebacks
-system.l2c.writebacks::total                    96871                       # number of writebacks
+system.l2c.writebacks::writebacks               97095                       # number of writebacks
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 system.l2c.ReadSharedReq_mshr_hits::cpu0.inst            5                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.inst           10                       # number of ReadSharedReq MSHR hits
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 system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             10                       # number of demand (read+write) MSHR hits
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 system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                15                       # number of overall MSHR hits
-system.l2c.CleanEvict_mshr_misses::writebacks         2791                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total         2791                       # number of CleanEvict MSHR misses
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+system.l2c.demand_mshr_miss_latency::total  25108288389                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       763500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       252000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   2124790500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   2631632500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  18188870293                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst   2171508000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   2622995500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  18223452761                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       122500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    293429500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1056691500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    785588015                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  25082255308                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    247283000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1048450500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher    793460628                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  25108288389                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5802133000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   5812758500                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    358998500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   7203979000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4702508000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    243698500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4946206500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    349483000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   7205089000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   4715021500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    233050000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4948071500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1023815000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10504641000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10527780000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst     19032500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    602697000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  12150185500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    582533000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  12153160500                       # number of overall MSHR uncacheable cycles
 system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.225495                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.536387                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.253953                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.216624                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.590930                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.382377                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.733622                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.855459                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.779344                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.066667                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.373242                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.158446                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738913                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.043478                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.272318                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.136403                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614893                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.549795                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.066667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.373242                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.281832                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738913                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.043478                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.272318                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.577358                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614893                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.566633                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.066667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.027397                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.373242                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.281832                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.738913                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.043478                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.272318                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.577358                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.614893                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.566633                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75375.839642                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75068.282918                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75316.375677                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77319.185059                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76712.999217                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76904.340836                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135426.566550                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120947.932619                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 129462.492772                       # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker       125500                       # average ReadSharedReq mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.228532                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.571713                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.258497                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.236462                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.595227                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.396113                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.727011                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.854019                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.774680                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.068966                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.021277                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.383909                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.158165                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739093                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.062500                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.241123                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.137754                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.639818                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.551743                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.068966                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.021277                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.383909                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.279927                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739093                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.062500                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.241123                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.587155                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.639818                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.568203                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.068966                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.021277                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.383909                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.279927                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.739093                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.062500                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.241123                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.587155                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.639818                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.568203                       # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75449.791883                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75156.956522                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75393.240974                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77364.885496                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76706.127080                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76924.380374                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134972.716649                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121172.143676                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 129262.661397                       # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker       127250                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121472.130117                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126214.027354                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121646.294325                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126216.407833                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745                       # average ReadSharedReq mshr miss latency
 system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124281.872088                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 138253.172589                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133423.918387                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       125500                       # average overall mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123026.368159                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129159.574468                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133638.864312                       # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       127250                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121472.130117                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131358.315863                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121646.294325                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131084.232884                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124281.872088                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122529.162801                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 133024.254633                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       125500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123026.368159                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121870.335929                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 133198.349040                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       127250                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       126000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121472.130117                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131358.315863                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121646.294325                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131084.232884                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker       122500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124281.872088                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122529.162801                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 133024.254633                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123026.368159                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121870.335929                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 133198.349040                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182348.062478                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182446.908349                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116633.690708                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163370.351052                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.070388                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100577.177053                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159957.522153                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112591.172680                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163147.634898                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165132.262810                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95905.349794                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159702.788626                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174154.332040                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174263.486336                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109561.352481                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 161963.602069                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 105264.365739                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 161727.310835                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq               44096                       # Transaction distribution
-system.membus.trans_dist::ReadResp             213882                       # Transaction distribution
-system.membus.trans_dist::WriteReq              30922                       # Transaction distribution
-system.membus.trans_dist::WriteResp             30922                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       133077                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            14603                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            73616                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          39905                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           13581                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq            8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             39514                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            18935                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        169786                       # Transaction distribution
+system.membus.trans_dist::ReadReq               44163                       # Transaction distribution
+system.membus.trans_dist::ReadResp             213934                       # Transaction distribution
+system.membus.trans_dist::WriteReq              30983                       # Transaction distribution
+system.membus.trans_dist::WriteResp             30983                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       133285                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            14406                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            73490                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          39839                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           13966                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq            3                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             39499                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            18896                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        169771                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107934                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13766                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       664049                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       785783                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108937                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       108937                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 894720                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        14022                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       664172                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       786162                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108909                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       108909                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 895071                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162814                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        27532                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18296972                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     18487386                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2318144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                20805530                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                           121102                       # Total snoops (count)
-system.membus.snoop_fanout::samples            582015                       # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        28044                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     18307596                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     18498522                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                20815642                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                           120564                       # Total snoops (count)
+system.membus.snoop_fanout::samples            581920                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  582015    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  581920    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              582015                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            88274000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              581920                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            88268000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               19000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11368000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11611500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           966740692                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           967762037                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1134075509                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1134685490                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64085297                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64105002                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -3020,52 +3000,52 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests       961177                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests       518872                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests       139554                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops          20662                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops        19793                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops          869                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              44099                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            468456                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             30922                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            30922                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       390602                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           84323                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq          107685                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         42919                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp         150604                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq           84                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp           84                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            50476                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           50476                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       424372                       # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests       959770                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests       518663                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests       138023                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops          20272                       # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops        19432                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops          840                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq              44166                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            467162                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             30983                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            30983                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       390842                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict           84262                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq          107575                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         42853                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp         150428                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq           72                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp           72                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            50605                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           50605                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       423011                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1224412                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       249093                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               1473505                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34296330                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3743120                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total               38039450                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          438983                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples           897187                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.337621                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.474943                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1226424                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       245800                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               1472224                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34332563                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      3643847                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total               37976410                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          437847                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples           895583                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.335708                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.474219                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                 595147     66.33%     66.33% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 301171     33.57%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                    869      0.10%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                 595769     66.52%     66.52% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                 298974     33.38%     99.91% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2                    840      0.09%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total             897187                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy          864296758                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total             895583                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy          863469481                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           360622                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           342622                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         647366860                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy         647119226                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         201908331                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy         200312901                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
index 263610058..03b467a01 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
@@ -158,8 +158,8 @@ ata1.00: 1048320 sectors, multi 0: LBA
 ata1.00: configured for UDMA/33

 scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5

 sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)

-sd 0:0:0:0: [sda] Write Protect is off

 sd 0:0:0:0: Attached scsi generic sg0 type 0

+sd 0:0:0:0: [sda] Write Protect is off

 sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00

 sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA

  sda: sda1

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 3ed11f6b1..535394f06 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -415,10 +415,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -445,7 +444,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -572,12 +571,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -670,16 +666,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -695,7 +690,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -858,13 +853,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -874,9 +869,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -918,7 +912,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -999,14 +993,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1023,7 +1016,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1038,7 +1031,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1161,17 +1154,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1223,7 +1218,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1238,7 +1233,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index f435b44af..adf07f76b 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 15:54:29
-gem5 executing on e104799-lin, pid 1785
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 12:27:38
+gem5 executing on e104799-lin, pid 4347
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2909603958500 because m5_exit instruction encountered
+Exiting @ tick 2909596171500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index ae445de86..e37d38e0e 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,66 +1,66 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.909604                       # Number of seconds simulated
-sim_ticks                                2909603958500                       # Number of ticks simulated
-final_tick                               2909603958500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.909596                       # Number of seconds simulated
+sim_ticks                                2909596171500                       # Number of ticks simulated
+final_tick                               2909596171500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 366627                       # Simulator instruction rate (inst/s)
-host_op_rate                                   442036                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9485837068                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 580620                       # Number of bytes of host memory used
-host_seconds                                   306.73                       # Real time elapsed on the host
-sim_insts                                   112455934                       # Number of instructions simulated
-sim_ops                                     135586369                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 612420                       # Simulator instruction rate (inst/s)
+host_op_rate                                   738388                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15845377688                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 579872                       # Number of bytes of host memory used
+host_seconds                                   183.62                       # Real time elapsed on the host
+sim_insts                                   112455206                       # Number of instructions simulated
+sim_ops                                     135585876                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker          448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1186596                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8901732                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1186404                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8901796                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10089864                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1186596                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1186596                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7512000                       # Number of bytes written to this memory
+system.physmem.bytes_read::total             10089736                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1186404                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1186404                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7511872                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7529524                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7529396                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker            7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              26994                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             139609                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              26991                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             139610                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166627                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117375                       # Number of write requests responded to by this memory
+system.physmem.num_reads::total                166625                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117373                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               121756                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               121754                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker            154                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             44                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               407820                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3059431                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               407756                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3059461                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3467779                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          407820                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             407820                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2581795                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3467744                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          407756                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             407756                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2581758                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data                6023                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2587817                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2581795                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2587780                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2581758                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           154                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            44                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              407820                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3065454                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              407756                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3065484                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6055597                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166627                       # Number of read requests accepted
-system.physmem.writeReqs                       121756                       # Number of write requests accepted
-system.physmem.readBursts                      166627                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     121756                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10656896                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7232                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7542080                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10089864                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7529524                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      113                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total                6055525                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166625                       # Number of read requests accepted
+system.physmem.writeReqs                       121754                       # Number of write requests accepted
+system.physmem.readBursts                      166625                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     121754                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10656448                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7552                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7541952                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10089736                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7529396                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      118                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs          47113                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               10077                       # Per bank write bursts
@@ -69,15 +69,15 @@ system.physmem.perBankRdBursts::2               10695                       # Pe
 system.physmem.perBankRdBursts::3               10661                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               18797                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                9659                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9665                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10488                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9663                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10485                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                9276                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                9973                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9230                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9232                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               8679                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9820                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9817                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              10379                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9723                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9722                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               9413                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7393                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7263                       # Per bank write bursts
@@ -86,35 +86,35 @@ system.physmem.perBankWrBursts::3                8171                       # Pe
 system.physmem.perBankWrBursts::4                7489                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7265                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                7108                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7662                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7659                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                7080                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                7523                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6693                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6695                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6470                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               7534                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7859                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7265                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7264                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               6788                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2909603601500                       # Total gap between requests
+system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2909595814500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  157055                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  157053                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117375                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    165631                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       614                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       257                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117373                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    165628                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       611                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       256                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -159,116 +159,117 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2472                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5973                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6277                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7372                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6828                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7824                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7975                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9304                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6630                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6710                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6026                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5995                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2431                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5974                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5923                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6296                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6381                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7297                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6883                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7756                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7889                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7774                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9310                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6648                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6775                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6094                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5950                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                      286                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      113                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      124                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       98                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      159                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       75                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      233                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       78                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       55                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                       51                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        58748                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      309.779261                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     182.856223                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.388013                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          21447     36.51%     36.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14643     24.93%     61.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6082     10.35%     71.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3222      5.48%     77.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2599      4.42%     81.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1493      2.54%     84.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1038      1.77%     86.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1067      1.82%     87.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7157     12.18%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          58748                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5762                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        28.896737                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      590.107660                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5761     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::56                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        4                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        58778                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      309.611351                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     182.749688                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.493771                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21450     36.49%     36.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14701     25.01%     61.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6086     10.35%     71.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3214      5.47%     77.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2550      4.34%     81.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1476      2.51%     84.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1054      1.79%     85.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1089      1.85%     87.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7158     12.18%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          58778                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5758                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        28.915596                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      590.311059                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5757     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::43008-45055            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5762                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5762                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.452100                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.700018                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.100411                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4964     86.15%     86.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              94      1.63%     87.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              35      0.61%     88.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             168      2.92%     91.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              22      0.38%     91.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             152      2.64%     94.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              51      0.89%     95.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               7      0.12%     95.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              11      0.19%     95.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              15      0.26%     95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               3      0.05%     95.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               4      0.07%     95.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             174      3.02%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               7      0.12%     99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               3      0.05%     99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              18      0.31%     99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               4      0.07%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.02%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.03%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.02%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.02%     99.57% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5758                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5758                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.465960                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.711564                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       13.116644                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4961     86.16%     86.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23              87      1.51%     87.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              33      0.57%     88.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             172      2.99%     91.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              23      0.40%     91.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             160      2.78%     94.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              50      0.87%     95.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               6      0.10%     95.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               7      0.12%     95.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              22      0.38%     95.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               2      0.03%     95.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.10%     96.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             163      2.83%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               3      0.05%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75              10      0.17%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              20      0.35%     99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.02%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87               1      0.02%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.02%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111             2      0.03%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115             1      0.02%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123             1      0.02%     99.57% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::124-127             1      0.02%     99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            15      0.26%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            16      0.28%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.88% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::140-143             2      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5762                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1626690000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4748827500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    832570000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9769.09                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::148-151             1      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             2      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5758                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1616458000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4738464250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    832535000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9708.05                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28519.09                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28458.05                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.66                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.59                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.47                       # Average system read bandwidth in MiByte/s
@@ -278,40 +279,40 @@ system.physmem.busUtil                           0.05                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        26.01                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     136108                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     89502                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.74                       # Row buffer hit rate for reads
+system.physmem.avgWrQLen                        25.45                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     136072                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     89499                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.72                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  75.93                       # Row buffer hit rate for writes
-system.physmem.avgGap                     10089372.82                       # Average gap between requests
-system.physmem.pageHitRate                      79.33                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  230496840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  125767125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 702163800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                392901840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           190040735040                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            90194010705                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1666640821500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1948326896850                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.620811                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2772423900000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     97157840000                       # Time in different power states
+system.physmem.avgGap                     10089485.76                       # Average gap between requests
+system.physmem.pageHitRate                      79.32                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  230958000                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  126018750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 702124800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                392882400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           190040226480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            90366604425                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1666484751750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1948343566605                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.628332                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2772164122000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     97157580000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     40015565000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     40267816750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  213638040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  116568375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 596637600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                370733760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           190040735040                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            88104913965                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1668473362500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1947916589280                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.479792                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2775503002250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     97157840000                       # Time in different power states
+system.physmem_1.actEnergy                  213403680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  116440500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 596622000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                370740240                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           190040226480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            88072375230                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1668497233500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1947907041630                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.478302                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2775541834250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     97157580000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     36942968250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     36896609250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -369,13 +370,12 @@ system.cpu.dtb.walker.walkWaitTime::samples         9546                       #
 system.cpu.dtb.walker.walkWaitTime::0            9546    100.00%    100.00% # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkWaitTime::total         9546                       # Table walker wait (enqueue to first request) latency
 system.cpu.dtb.walker.walkCompletionTime::samples         7382                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 13188.702249                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 10926.693941                       # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev  9189.684239                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 13161.947982                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 10924.263330                       # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev  8540.848722                       # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::0-32767         7377     99.93%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839            3      0.04%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-360447            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-163839            4      0.05%     99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::294912-327679            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walkCompletionTime::total         7382                       # Table walker service (enqueue to completion) latency
 system.cpu.dtb.walker.walksPending::samples   1638910500                       # Table walker pending requests distribution
 system.cpu.dtb.walker.walksPending::0      1638910500    100.00%    100.00% # Table walker pending requests distribution
@@ -392,9 +392,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7382
 system.cpu.dtb.walker.walkRequestOrigin::total        16928                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24520223                       # DTB read hits
+system.cpu.dtb.read_hits                     24520178                       # DTB read hits
 system.cpu.dtb.read_misses                       8124                       # DTB read misses
-system.cpu.dtb.write_hits                    19606444                       # DTB write hits
+system.cpu.dtb.write_hits                    19606457                       # DTB write hits
 system.cpu.dtb.write_misses                      1422                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
@@ -405,12 +405,12 @@ system.cpu.dtb.align_faults                         0                       # Nu
 system.cpu.dtb.prefetch_faults                   1650                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       445                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24528347                       # DTB read accesses
-system.cpu.dtb.write_accesses                19607866                       # DTB write accesses
+system.cpu.dtb.read_accesses                 24528302                       # DTB read accesses
+system.cpu.dtb.write_accesses                19607879                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44126667                       # DTB hits
+system.cpu.dtb.hits                          44126635                       # DTB hits
 system.cpu.dtb.misses                            9546                       # DTB misses
-system.cpu.dtb.accesses                      44136213                       # DTB accesses
+system.cpu.dtb.accesses                      44136181                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -468,7 +468,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0
 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3108                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Completed::total         3108                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin::total         7871                       # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits                    115553087                       # ITB inst hits
+system.cpu.itb.inst_hits                    115552414                       # ITB inst hits
 system.cpu.itb.inst_misses                       4763                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -485,40 +485,40 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                115557850                       # ITB inst accesses
-system.cpu.itb.hits                         115553087                       # DTB hits
+system.cpu.itb.inst_accesses                115557177                       # ITB inst accesses
+system.cpu.itb.hits                         115552414                       # DTB hits
 system.cpu.itb.misses                            4763                       # DTB misses
-system.cpu.itb.accesses                     115557850                       # DTB accesses
-system.cpu.numCycles                       5819207917                       # number of cpu cycles simulated
+system.cpu.itb.accesses                     115557177                       # DTB accesses
+system.cpu.numCycles                       5819192343                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     3033                       # number of quiesce instructions executed
-system.cpu.committedInsts                   112455934                       # Number of instructions committed
-system.cpu.committedOps                     135586369                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             119891885                       # Number of integer alu accesses
+system.cpu.committedInsts                   112455206                       # Number of instructions committed
+system.cpu.committedOps                     135585876                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             119891340                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11161                       # Number of float alu accesses
-system.cpu.num_func_calls                     9891908                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     15230427                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    119891885                       # number of integer instructions
+system.cpu.num_func_calls                     9892021                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     15230391                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    119891340                       # number of integer instructions
 system.cpu.num_fp_insts                         11161                       # number of float instructions
-system.cpu.num_int_register_reads           218060317                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           82644878                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           218059811                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           82644916                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 8449                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2716                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            489736143                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            51894204                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      45406948                       # number of memory refs
-system.cpu.num_load_insts                    24842511                       # Number of load instructions
+system.cpu.num_cc_register_reads            489735153                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            51893214                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      45407055                       # number of memory refs
+system.cpu.num_load_insts                    24842618                       # Number of load instructions
 system.cpu.num_store_insts                   20564437                       # Number of store instructions
-system.cpu.num_idle_cycles               5379072532.100152                       # Number of idle cycles
-system.cpu.num_busy_cycles               440135384.899849                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.075635                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.924365                       # Percentage of idle cycles
-system.cpu.Branches                          25916368                       # Number of branches fetched
+system.cpu.num_idle_cycles               5379072985.844151                       # Number of idle cycles
+system.cpu.num_busy_cycles               440119357.155849                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.075632                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.924368                       # Percentage of idle cycles
+system.cpu.Branches                          25916470                       # Number of branches fetched
 system.cpu.op_class::No_OpClass                  2337      0.00%      0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu                  93174225     67.17%     67.18% # Class of executed instruction
-system.cpu.op_class::IntMult                   114427      0.08%     67.26% # Class of executed instruction
+system.cpu.op_class::IntAlu                  93173703     67.17%     67.18% # Class of executed instruction
+system.cpu.op_class::IntMult                   114388      0.08%     67.26% # Class of executed instruction
 system.cpu.op_class::IntDiv                         0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     67.26% # Class of executed instruction
@@ -542,20 +542,20 @@ system.cpu.op_class::SimdFloatAlu                   0      0.00%     67.26% # Cl
 system.cpu.op_class::SimdFloatCmp                   0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatCvt                   0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatDiv                   0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc               8455      0.01%     67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc               8453      0.01%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatMult                  0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     67.26% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     67.26% # Class of executed instruction
-system.cpu.op_class::MemRead                 24842511     17.91%     85.17% # Class of executed instruction
+system.cpu.op_class::MemRead                 24842618     17.91%     85.17% # Class of executed instruction
 system.cpu.op_class::MemWrite                20564437     14.83%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  138706392                       # Class of executed instruction
-system.cpu.dcache.tags.replacements            819093                       # number of replacements
+system.cpu.op_class::total                  138705936                       # Class of executed instruction
+system.cpu.dcache.tags.replacements            819217                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.702336                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            43235572                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            819605                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             52.751718                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            43235406                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            819729                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             52.743536                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        1736147500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.702336                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999419                       # Average percentage of cache occupancy
@@ -566,188 +566,188 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          344
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         177109325                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        177109325                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23112645                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23112645                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18823942                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18823942                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data       392782                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total        392782                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       443235                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       443235                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       460203                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       460203                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41936587                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41936587                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42329369                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42329369                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       399856                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        399856                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       298641                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       298641                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data       118367                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total       118367                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22751                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22751                       # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses         177109321                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        177109321                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23112521                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23112521                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18823879                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18823879                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data       392783                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total        392783                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       443242                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       443242                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460216                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       460216                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41936400                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41936400                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42329183                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42329183                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       399911                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        399911                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       298704                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       298704                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data       118377                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total       118377                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22757                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22757                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data       698497                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         698497                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       816864                       # number of overall misses
-system.cpu.dcache.overall_misses::total        816864                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   6484051000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   6484051000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  19116145000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  19116145000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    294006500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    294006500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data       698615                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         698615                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       816992                       # number of overall misses
+system.cpu.dcache.overall_misses::total        816992                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   6486417000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   6486417000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  19109109000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  19109109000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    294489000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    294489000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       164000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  25600196000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  25600196000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  25600196000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  25600196000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23512501                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23512501                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  25595526000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  25595526000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  25595526000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  25595526000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23512432                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23512432                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19122583                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19122583                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       511149                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       511149                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465986                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       465986                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       460205                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       460205                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42635084                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42635084                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     43146233                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     43146233                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017006                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.017006                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015617                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015617                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.231570                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.231570                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048823                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048823                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       511160                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       511160                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       465999                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       465999                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460218                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       460218                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42635015                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42635015                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     43146175                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     43146175                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.017008                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.017008                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015620                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015620                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.231585                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.231585                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.048835                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.048835                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.016383                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.016383                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.018932                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.018932                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16215.965247                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16215.965247                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64010.450675                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64010.450675                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12922.794602                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12922.794602                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016386                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016386                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.018935                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.018935                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.651372                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.651372                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63973.395067                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 63973.395067                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12940.589709                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12940.589709                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 36650.402221                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 36650.402221                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31339.606103                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31339.606103                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          100                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 36637.527107                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 36637.527107                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31328.979966                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31328.979966                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                20                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                19                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs            5                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs            4                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       683726                       # number of writebacks
-system.cpu.dcache.writebacks::total            683726                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          924                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          924                       # number of ReadReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14242                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total        14242                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          924                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          924                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          924                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          924                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       398932                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       398932                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298641                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       298641                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       116310                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total       116310                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8509                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total         8509                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       683842                       # number of writebacks
+system.cpu.dcache.writebacks::total            683842                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          930                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          930                       # number of ReadReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        14247                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total        14247                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          930                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          930                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          930                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          930                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       398981                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       398981                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298704                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       298704                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       116321                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total       116321                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8510                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total         8510                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       697573                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       697573                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       813883                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       813883                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       697685                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       697685                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       814006                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       814006                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        27589                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6055510500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6055510500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18817504000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  18817504000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1617135000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1617135000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    115280000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    115280000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6058107000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6058107000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  18810405000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  18810405000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1614233500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1614233500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    115353500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    115353500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       162000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24873014500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  24873014500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26490149500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26490149500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6279074500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6279074500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5089978000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5089978000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11369052500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  11369052500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016967                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016967                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227546                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227546                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018260                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018260                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24868512000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  24868512000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26482745500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26482745500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6278172000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6278172000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   5089977500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   5089977500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  11368149500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  11368149500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016969                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016969                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015620                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015620                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.227563                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.227563                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018262                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.018262                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016361                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016361                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018863                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.018863                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15179.304994                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15179.304994                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63010.450675                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63010.450675                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13903.662626                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13903.662626                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13548.007992                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13548.007992                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016364                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016364                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.018866                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.018866                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15183.948609                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15183.948609                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62973.395067                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62973.395067                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.403908                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.403908                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13555.052879                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13555.052879                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35656.504050                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 35656.504050                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32547.859459                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 32547.859459                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201653.108742                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201653.108742                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.022581                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.022581                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193591.576277                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193591.576277                       # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35644.326594                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35644.326594                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32533.845574                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 32533.845574                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201624.124864                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201624.124864                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.004458                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.004458                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193576.200044                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193576.200044                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           1695571                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.436867                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           113856998                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1696083                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             67.129379                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements           1695565                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.436866                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           113856331                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1696077                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             67.129223                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle       29070355500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.436867                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.436866                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.996947                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.996947                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -756,44 +756,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          195
 system.cpu.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         117249176                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        117249176                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    113856998                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       113856998                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     113856998                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        113856998                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    113856998                       # number of overall hits
-system.cpu.icache.overall_hits::total       113856998                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1696089                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1696089                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1696089                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1696089                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1696089                       # number of overall misses
-system.cpu.icache.overall_misses::total       1696089                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  24269708000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  24269708000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  24269708000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  24269708000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  24269708000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  24269708000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    115553087                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    115553087                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    115553087                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    115553087                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    115553087                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    115553087                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         117248497                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        117248497                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    113856331                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       113856331                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     113856331                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        113856331                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    113856331                       # number of overall hits
+system.cpu.icache.overall_hits::total       113856331                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1696083                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1696083                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1696083                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1696083                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1696083                       # number of overall misses
+system.cpu.icache.overall_misses::total       1696083                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  24267960000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  24267960000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  24267960000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  24267960000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  24267960000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  24267960000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    115552414                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    115552414                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    115552414                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    115552414                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    115552414                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    115552414                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014678                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.014678                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.014678                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.014678                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.014678                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.014678                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.218443                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14309.218443                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.218443                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14309.218443                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.218443                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14309.218443                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14308.238453                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14308.238453                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14308.238453                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14308.238453                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14308.238453                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14308.238453                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -802,24 +802,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      1695571                       # number of writebacks
-system.cpu.icache.writebacks::total           1695571                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1696089                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1696089                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1696089                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1696089                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1696089                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1696089                       # number of overall MSHR misses
+system.cpu.icache.writebacks::writebacks      1695565                       # number of writebacks
+system.cpu.icache.writebacks::total           1695565                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1696083                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1696083                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1696083                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1696083                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1696083                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1696083                       # number of overall MSHR misses
 system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22573619000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  22573619000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22573619000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  22573619000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22573619000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  22573619000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  22571877000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  22571877000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  22571877000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  22571877000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  22571877000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  22571877000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   1142541000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   1142541000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   1142541000                       # number of overall MSHR uncacheable cycles
@@ -830,71 +830,71 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014678
 system.cpu.icache.demand_mshr_miss_rate::total     0.014678                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014678                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.014678                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.218443                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.218443                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.218443                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.218443                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.218443                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.218443                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13308.238453                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13308.238453                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13308.238453                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13308.238453                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13308.238453                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13308.238453                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            87564                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64865.227437                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4544047                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           152799                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            29.738722                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            87562                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64865.195753                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4544223                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           152797                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            29.740263                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50197.653066                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.799333                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.012653                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  9701.739092                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4962.023293                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.765955                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50196.671494                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.799338                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.012652                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  9701.731977                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4962.980293                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.765940                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000058                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.148037                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.075714                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.989765                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.075729                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.989764                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65230                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2129                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6852                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56198                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6849                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56201                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.995331                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         40507837                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        40507837                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7811                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses         40509810                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        40509810                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7810                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4039                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          11850                       # number of ReadReq hits
-system.cpu.l2cache.WritebackDirty_hits::writebacks       683726                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       683726                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1664804                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1664804                       # number of WritebackClean hits
+system.cpu.l2cache.ReadReq_hits::total          11849                       # number of ReadReq hits
+system.cpu.l2cache.WritebackDirty_hits::writebacks       683842                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       683842                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1664795                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1664795                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           23                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           23                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       166964                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       166964                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1678077                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      1678077                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       511579                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       511579                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         7811                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       167026                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       167026                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1678074                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1678074                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       511640                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       511640                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         7810                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         4039                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1678077                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       678543                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2368470                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         7811                       # number of overall hits
+system.cpu.l2cache.demand_hits::cpu.inst      1678074                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       678666                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2368589                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         7810                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         4039                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1678077                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       678543                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2368470                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      1678074                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       678666                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2368589                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            7                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total            9                       # number of ReadReq misses
@@ -902,72 +902,72 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data         2740
 system.cpu.l2cache.UpgradeReq_misses::total         2740                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       128914                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       128914                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        17979                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        17979                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       128915                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       128915                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        17976                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        17976                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data        12172                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total        12172                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker            7                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        17979                       # number of demand (read+write) misses
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-system.cpu.l2cache.demand_misses::total        159074                       # number of demand (read+write) misses
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+system.cpu.l2cache.demand_misses::total        159072                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker            7                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        17979                       # number of overall misses
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-system.cpu.l2cache.overall_misses::total       159074                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      1147500                       # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst        17976                       # number of overall misses
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+system.cpu.l2cache.overall_misses::total       159072                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       957500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       266000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total      1413500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total      1223500                       # number of ReadReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      1857500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total      1857500                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       159000                       # number of SCUpgradeReq miss cycles
 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16391193500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16391193500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2350840500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   2350840500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1613502500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1613502500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      1147500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16383348000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16383348000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2349142000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   2349142000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1612524000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1612524000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       957500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       266000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   2350840500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  18004696000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  20356950000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      1147500                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   2349142000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  17995872000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  20346237500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       957500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       266000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   2350840500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  18004696000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  20356950000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7818                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_miss_latency::cpu.inst   2349142000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  17995872000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  20346237500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         7817                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4041                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        11859                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       683726                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       683726                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1664804                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1664804                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        11858                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       683842                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       683842                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1664795                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1664795                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2763                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         2763                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       295878                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       295878                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1696056                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      1696056                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       523751                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       523751                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7818                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       295941                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       295941                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1696050                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1696050                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       523812                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       523812                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         7817                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         4041                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1696056                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       819629                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2527544                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7818                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst      1696050                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       819753                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2527661                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         7817                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.itb.walker         4041                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1696056                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       819629                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2527544                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1696050                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       819753                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2527661                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000895                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000495                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.000759                       # miss rate for ReadReq accesses
@@ -975,45 +975,45 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991676
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991676                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.435700                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.435700                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010600                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010600                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.023240                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.023240                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.435610                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.435610                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.010599                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.010599                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.023237                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.023237                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000895                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000495                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010600                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.172134                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.062936                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.010599                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.172109                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.062932                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000895                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000495                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010600                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.172134                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.062936                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 163928.571429                       # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.010599                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.172109                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.062932                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       133000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 157055.555556                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444                       # average ReadReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   677.919708                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   677.919708                       # average UpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        79500                       # average SCUpgradeReq miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127148.281025                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127148.281025                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130754.797263                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130754.797263                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132558.535984                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132558.535984                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 163928.571429                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127086.436799                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127086.436799                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130682.131731                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130682.131731                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132478.146566                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132478.146566                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130754.797263                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127615.043307                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 127971.572979                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 163928.571429                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130682.131731                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127551.595824                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 127905.838237                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130754.797263                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127615.043307                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 127971.572979                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130682.131731                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127551.595824                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 127905.838237                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1022,8 +1022,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        81185                       # number of writebacks
-system.cpu.l2cache.writebacks::total            81185                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        81183                       # number of writebacks
+system.cpu.l2cache.writebacks::total            81183                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            7                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total            9                       # number of ReadReq MSHR misses
@@ -1031,22 +1031,22 @@ system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2740
 system.cpu.l2cache.UpgradeReq_mshr_misses::total         2740                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       128914                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       128914                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        17979                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        17979                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       128915                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       128915                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        17976                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        17976                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        12172                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total        12172                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            7                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        17979                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       141086                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       159074                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        17976                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       141087                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       159072                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            7                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        17979                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       141086                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       159074                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        17976                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       141087                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       159072                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst         9022                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        31138                       # number of ReadReq MSHR uncacheable
 system.cpu.l2cache.ReadReq_mshr_uncacheable::total        40160                       # number of ReadReq MSHR uncacheable
@@ -1055,37 +1055,37 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total        27589
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst         9022                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        58727                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total        67749                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      1077500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       887500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       246000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      1323500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    194003000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    194003000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      1133500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    194003500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    194003500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       139000                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       139000                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15102053500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15102053500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2171050500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2171050500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1491782500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1491782500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      1077500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15094198000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15094198000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2169382000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2169382000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1490804000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1490804000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       887500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       246000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2171050500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16593836000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  18766210000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      1077500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2169382000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16585002000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  18755517500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       887500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       246000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2171050500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16593836000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  18766210000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2169382000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16585002000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  18755517500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   1029766000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5889729000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6919495000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4772574500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4772574500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5888826500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   6918592500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4772574000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4772574000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   1029766000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10662303500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11692069500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  10661400500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  11691166500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000895                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000759                       # mshr miss rate for ReadReq accesses
@@ -1093,104 +1093,104 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991676
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991676                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.435700                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.435700                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010600                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010600                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.023240                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.023240                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.435610                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.435610                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.010599                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.023237                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.023237                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000895                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010600                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172134                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.062936                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172109                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.062932                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000895                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000495                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010600                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172134                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.062936                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.010599                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172109                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.062932                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 147055.555556                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.014599                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.014599                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.197080                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.197080                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        69500                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.281025                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.281025                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120754.797263                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120754.797263                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122558.535984                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122558.535984                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117086.436799                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117086.436799                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120682.131731                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120682.131731                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122478.146566                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122478.146566                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120754.797263                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117615.043307                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117971.572979                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120682.131731                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117551.595824                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117905.838237                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120754.797263                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117615.043307                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117971.572979                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120682.131731                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117551.595824                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117905.838237                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189149.238872                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172298.182271                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.310559                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.310559                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.254994                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.709661                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.292435                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.292435                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181557.094692                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172579.218881                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.718460                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.890271                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5052300                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2536604                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        38129                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5052537                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2536723                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        38125                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops          581                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops          581                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq          67213                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2287266                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2287321                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         27589                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        27589                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       801101                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1664804                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       134612                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       801217                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1664795                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       134627                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2763                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2765                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       295878                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       295878                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      1696089                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       523979                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       295941                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       295941                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1696083                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       524040                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5074993                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2574186                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5074972                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2574565                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        13257                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        25655                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7688091                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    215131128                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96411485                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        25654                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7688448                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    215130168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     96426845                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        16164                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        31272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          311590049                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      175874                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2773719                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.020869                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.142946                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        31268                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          311604445                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      175875                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2773837                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.020867                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.142939                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2715834     97.91%     97.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              57885      2.09%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2715955     97.91%     97.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              57882      2.09%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2773719                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4957066000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2773837                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4957294000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       380377                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       380876                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    2553155500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    2553146500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1275758999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1275944500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer2.occupancy       9216000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
@@ -1202,6 +1202,7 @@ system.iobus.trans_dist::WriteReq               59014                       # Tr
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
@@ -1217,16 +1218,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  178382                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
@@ -1242,10 +1241,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321056                       # Cumulative packet size per connected master and slave (bytes)
@@ -1254,14 +1250,16 @@ system.iobus.reqLayer0.occupancy             46338000                       # La
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                97000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               338000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                16000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                94500                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               644500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy                94500                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer8.occupancy               644500                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
@@ -1282,29 +1280,23 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6288500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6287500                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              174000                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36469500                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            36469500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           186221548                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              127000                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186222546                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               37000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36728000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36418                       # number of replacements
-system.iocache.tags.tagsinuse                1.084136                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.084130                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36434                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         313818895000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.084136                       # Average occupied blocks per requestor
+system.iocache.tags.warmup_cycle         313812613000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide     1.084130                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::realview.ide     0.067758                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.067758                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
@@ -1320,14 +1312,14 @@ system.iocache.demand_misses::realview.ide          228                       #
 system.iocache.demand_misses::total               228                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          228                       # number of overall misses
 system.iocache.overall_misses::total              228                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28180377                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28180377                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4715427169                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4715427169                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28180377                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28180377                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28180377                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28180377                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     28228376                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28228376                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4717653172                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4717653172                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28228376                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28228376                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28228376                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28228376                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1344,19 +1336,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 123598.144737                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130174.115752                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130174.115752                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 123598.144737                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 123598.144737                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 123598.144737                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 123598.144737                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           753                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 123808.666667                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 123808.666667                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130235.566807                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130235.566807                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 123808.666667                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 123808.666667                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 123808.666667                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 123808.666667                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           910                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                   81                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.296296                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.234568                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1370,14 +1362,14 @@ system.iocache.demand_mshr_misses::realview.ide          228
 system.iocache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          228                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          228                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16780377                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16780377                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2904227169                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2904227169                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16780377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16780377                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16780377                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16780377                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     16828376                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     16828376                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2906453172                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2906453172                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     16828376                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     16828376                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     16828376                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     16828376                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1386,68 +1378,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80174.115752                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80174.115752                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 73598.144737                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 73598.144737                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73808.666667                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 73808.666667                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.566807                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.566807                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 73808.666667                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 73808.666667                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 73808.666667                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 73808.666667                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
-system.membus.trans_dist::ReadResp              70548                       # Transaction distribution
+system.membus.trans_dist::ReadResp              70545                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       117375                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       117373                       # Transaction distribution
 system.membus.trans_dist::CleanEvict             6392                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4497                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4499                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            127157                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           127157                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         30388                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            127158                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           127158                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         30385                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       438823                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       546415                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       438817                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       546409                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108894                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108894                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 655309                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 655303                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15302268                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15465621                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15302012                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     15465365                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17782741                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17782485                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              492                       # Total snoops (count)
-system.membus.snoop_fanout::samples            389999                       # Request fanout histogram
+system.membus.snoop_fanout::samples            389997                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  389999    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  389997    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              389999                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            90471000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              389997                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            90470000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy             1726000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           823075656                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           823068661                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          952261248                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          952238748                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64129261                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64113741                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index c18617da5..14ca44c08 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -511,10 +511,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -541,7 +540,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -641,12 +640,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -739,16 +735,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -764,7 +759,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -927,13 +922,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -943,9 +938,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -987,7 +981,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1068,14 +1062,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1092,7 +1085,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1107,7 +1100,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1230,17 +1223,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1292,7 +1287,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1307,7 +1302,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
index a9e51249c..65b8c5d0a 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 15:55:07
-gem5 executing on e104799-lin, pid 1838
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 11:36:43
+gem5 executing on e104799-lin, pid 31310
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
 
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index bf5be371b..9720a4a26 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.783867                       # Nu
 sim_ticks                                2783867052000                       # Number of ticks simulated
 final_tick                               2783867052000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 544117                       # Simulator instruction rate (inst/s)
-host_op_rate                                   662376                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            10609508545                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 578316                       # Number of bytes of host memory used
-host_seconds                                   262.39                       # Real time elapsed on the host
+host_inst_rate                                 949157                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1155446                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18507193552                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 578592                       # Number of bytes of host memory used
+host_seconds                                   150.42                       # Real time elapsed on the host
 sim_insts                                   142772879                       # Number of instructions simulated
 sim_ops                                     173803124                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -666,6 +666,7 @@ system.iobus.trans_dist::WriteReq               59002                       # Tr
 system.iobus.trans_dist::WriteResp              59002                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54116                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
@@ -681,16 +682,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105404                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72928                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72928                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  178332                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67833                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
@@ -706,10 +705,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159061                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321152                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321152                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
index 79996f19b..a24fe1dd0 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -503,10 +503,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=system.realview.pciconfig.pio
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
+master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
 
 [system.iocache]
@@ -533,7 +532,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[27]
+cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[3]
 
 [system.iocache.tags]
@@ -697,12 +696,9 @@ port=system.membus.master[5]
 
 [system.realview]
 type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
+children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
 eventq_index=0
 intrctrl=system.intrctrl
-pci_cfg_base=805306368
-pci_cfg_gen_offsets=false
-pci_io_base=0
 system=system
 
 [system.realview.aaci_fake]
@@ -795,16 +791,15 @@ config_latency=20000
 ctrl_offset=2
 disks=
 eventq_index=0
+host=system.realview.pci_host
 io_shift=2
 pci_bus=2
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[9]
 dma=system.iobus.slave[2]
-pio=system.iobus.master[8]
+pio=system.iobus.master[9]
 
 [system.realview.clcd]
 type=Pl111
@@ -820,7 +815,7 @@ pixel_clock=41667
 system=system
 vnc=system.vncserver
 dma=system.iobus.slave[1]
-pio=system.iobus.master[4]
+pio=system.iobus.master[5]
 
 [system.realview.dcc]
 type=SubSystem
@@ -983,13 +978,13 @@ eventq_index=0
 fetch_comp_delay=10000
 fetch_delay=10000
 hardware_address=00:90:00:00:00:01
+host=system.realview.pci_host
 pci_bus=0
 pci_dev=0
 pci_func=0
 phy_epid=896
 phy_pid=680
 pio_latency=30000
-platform=system.realview
 rx_desc_cache_size=64
 rx_fifo_size=393216
 rx_write_delay=0
@@ -999,9 +994,8 @@ tx_fifo_size=393216
 tx_read_delay=0
 wb_comp_delay=10000
 wb_delay=10000
-config=system.iobus.master[26]
 dma=system.iobus.slave[4]
-pio=system.iobus.master[25]
+pio=system.iobus.master[24]
 
 [system.realview.generic_timer]
 type=GenericTimer
@@ -1043,7 +1037,7 @@ vnc=system.vncserver
 workaround_dma_line_count=true
 workaround_swap_rb=true
 dma=system.membus.slave[0]
-pio=system.iobus.master[5]
+pio=system.iobus.master[6]
 
 [system.realview.ide]
 type=IdeController
@@ -1124,14 +1118,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.cf0
 eventq_index=0
+host=system.realview.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=system.realview
 system=system
-config=system.iobus.master[24]
 dma=system.iobus.slave[3]
 pio=system.iobus.master[23]
 
@@ -1148,7 +1141,7 @@ pio_addr=470155264
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[6]
+pio=system.iobus.master[7]
 
 [system.realview.kmi1]
 type=Pl050
@@ -1163,7 +1156,7 @@ pio_addr=470220800
 pio_latency=100000
 system=system
 vnc=system.vncserver
-pio=system.iobus.master[7]
+pio=system.iobus.master[8]
 
 [system.realview.l2x0_fake]
 type=IsaFake
@@ -1286,17 +1279,19 @@ null=false
 range=0:67108863
 port=system.membus.master[1]
 
-[system.realview.pciconfig]
-type=PciConfigAll
-bus=0
+[system.realview.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=805306368
+conf_device_bits=16
+conf_size=268435456
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=0
 platform=system.realview
-size=268435456
 system=system
-pio=system.iobus.default
+pio=system.iobus.master[2]
 
 [system.realview.realview_io]
 type=RealViewCtrl
@@ -1348,7 +1343,7 @@ int_num1=34
 pio_addr=470876160
 pio_latency=100000
 system=system
-pio=system.iobus.master[2]
+pio=system.iobus.master[3]
 
 [system.realview.timer1]
 type=Sp804
@@ -1363,7 +1358,7 @@ int_num1=35
 pio_addr=470941696
 pio_latency=100000
 system=system
-pio=system.iobus.master[3]
+pio=system.iobus.master[4]
 
 [system.realview.uart]
 type=Pl011
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
index 48d941748..d2f2052ec 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
@@ -63,3 +63,19 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
index 1355ee684..d795d81a2 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Dec  3 2015 15:48:05
-gem5 started Dec  3 2015 15:55:08
-gem5 executing on e104799-lin, pid 1845
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
+gem5 compiled Dec  4 2015 11:13:17
+gem5 started Dec  4 2015 11:29:52
+gem5 executing on e104799-lin, pid 30613
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
 
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
index acd379650..5b2713b0e 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.909654                       # Number of seconds simulated
-sim_ticks                                2909653700500                       # Number of ticks simulated
-final_tick                               2909653700500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.909671                       # Number of seconds simulated
+sim_ticks                                2909670971500                       # Number of ticks simulated
+final_tick                               2909670971500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 367664                       # Simulator instruction rate (inst/s)
-host_op_rate                                   443285                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9513271691                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 578564                       # Number of bytes of host memory used
-host_seconds                                   305.85                       # Real time elapsed on the host
-sim_insts                                   112450652                       # Number of instructions simulated
-sim_ops                                     135579653                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 618646                       # Simulator instruction rate (inst/s)
+host_op_rate                                   745891                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            16006919548                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 578852                       # Number of bytes of host memory used
+host_seconds                                   181.78                       # Real time elapsed on the host
+sim_insts                                   112454909                       # Number of instructions simulated
+sim_ops                                     135585028                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           521248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4656256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           523360                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4648320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          192                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           665348                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4245540                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           663236                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4253220                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10089864                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       521248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       665348                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total             10089608                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       523360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       663236                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total         1186596                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      7511936                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data          8852                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data          8672                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           7529460                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             13432                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73257                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             13465                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73133                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            3                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             13562                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             66353                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst             13529                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             66473                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166627                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                166623                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          117374                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             2213                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data             2168                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               121755                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu0.dtb.walker            88                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              179144                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1600278                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              179869                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1597541                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            66                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              228669                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1459122                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              227942                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1461753                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              330                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3467720                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         179144                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         228669                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             407813                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2581729                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3467611                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         179869                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         227942                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             407811                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2581713                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               3042                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data               2980                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2587751                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2581729                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total                2587736                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2581713                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           88                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             179144                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1603321                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             179869                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1600584                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           66                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             228669                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1462103                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             227942                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1464733                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             330                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6055471                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166627                       # Number of read requests accepted
+system.physmem.bw_total::total                6055347                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166623                       # Number of read requests accepted
 system.physmem.writeReqs                       121755                       # Number of write requests accepted
-system.physmem.readBursts                      166627                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      166623                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                     121755                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10658432                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      5696                       # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM                 10657728                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6144                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                   7541440                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10089864                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                  10089608                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                7529460                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       89                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                       96                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                    3888                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          47114                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs          47111                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               10080                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                9979                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10697                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10658                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10654                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               18793                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9660                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9676                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10492                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9662                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9670                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10489                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                9276                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                9982                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               9231                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8678                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               8676                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               9823                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              10380                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               9720                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9722                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               9413                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7393                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7263                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                8284                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8168                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                8167                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7485                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                7265                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                7108                       # Per bank write bursts
@@ -107,21 +107,21 @@ system.physmem.perBankWrBursts::7                7667                       # Pe
 system.physmem.perBankWrBursts::8                7080                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                7523                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               6694                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6470                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6468                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               7527                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7859                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7261                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7264                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               6788                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2909653343500                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    2909670614500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    9558                       # Read request sizes (log2)
 system.physmem.readPktSize::3                      14                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  157055                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  157051                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                   4381                       # Write request sizes (log2)
@@ -129,8 +129,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                 117374                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    165652                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       617                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    165647                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       611                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                       257                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
@@ -161,137 +161,131 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                       202                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                       199                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                       188                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::3                       185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       181                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                       180                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                       176                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::8                       174                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                       172                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                      170                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      169                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::12                      166                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                      165                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2197                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2515                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5891                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5740                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6773                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     9126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7042                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     6452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     6467                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     6039                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      152                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      148                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      101                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      106                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      120                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        58556                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      310.810301                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     183.232220                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.272692                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          21388     36.53%     36.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        14563     24.87%     61.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6001     10.25%     71.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3238      5.53%     77.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2533      4.33%     81.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1526      2.61%     84.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1009      1.72%     85.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1158      1.98%     87.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7140     12.19%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          58556                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5712                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        29.151786                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      545.492775                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           5709     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            2      0.04%     99.98% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15                     2202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5854                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5793                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6776                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7632                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7829                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     9135                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7022                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6502                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5806                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      144                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       89                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       68                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       12                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        58603                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      310.549016                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     183.176876                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.004841                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          21372     36.47%     36.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        14638     24.98%     61.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6011     10.26%     71.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3214      5.48%     77.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2514      4.29%     81.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1548      2.64%     84.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1052      1.80%     85.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1122      1.91%     87.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7132     12.17%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          58603                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5730                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.058290                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      544.635756                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           5727     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            2      0.03%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::40960-43007            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5712                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5712                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.629377                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.719500                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.211627                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                18      0.32%      0.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 9      0.16%      0.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                8      0.14%      0.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15              11      0.19%      0.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            4765     83.42%     84.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             125      2.19%     86.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              59      1.03%     87.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             204      3.57%     91.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35              32      0.56%     91.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             148      2.59%     94.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              51      0.89%     95.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               8      0.14%     95.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               9      0.16%     95.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              17      0.30%     95.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               5      0.09%     95.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               8      0.14%     95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             167      2.92%     98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               5      0.09%     98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               6      0.11%     99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              19      0.33%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               4      0.07%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.04%     99.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.02%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               3      0.05%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.02%     99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.02%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.02%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             2      0.04%     99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.04%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            15      0.26%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139             1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155             2      0.04%     99.98% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5730                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5730                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        20.564572                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.725438                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.838937                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3                17      0.30%      0.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7                 9      0.16%      0.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11                8      0.14%      0.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15              11      0.19%      0.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19            4763     83.12%     83.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             132      2.30%     86.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              73      1.27%     87.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31             203      3.54%     91.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35              27      0.47%     91.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39             153      2.67%     94.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43              54      0.94%     95.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               2      0.03%     95.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              13      0.23%     95.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55              23      0.40%     95.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               5      0.09%     95.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               7      0.12%     95.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67             171      2.98%     98.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71               5      0.09%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75               6      0.10%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79              24      0.42%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               3      0.05%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             1      0.02%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.02%     99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131            11      0.19%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135             1      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143             1      0.02%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155             3      0.05%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159             2      0.03%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::164-167             1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5712                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1608810750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4731398250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    832690000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9660.32                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total            5730                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1612014000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4734395250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    832635000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9680.20                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28410.32                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28430.20                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.66                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           2.59                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.47                       # Average system read bandwidth in MiByte/s
@@ -301,40 +295,40 @@ system.physmem.busUtil                           0.05                       # Da
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        12.25                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     136274                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     89542                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.83                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.97                       # Row buffer hit rate for writes
-system.physmem.avgGap                     10089580.29                       # Average gap between requests
-system.physmem.pageHitRate                      79.40                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  230519520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  125779500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 702273000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                392901840                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           190044294960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            90285662430                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           1666593127500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             1948374558750                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.624648                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   2772342347250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     97159660000                       # Time in different power states
+system.physmem.avgWrQLen                        12.26                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     136241                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     89517                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.81                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.95                       # Row buffer hit rate for writes
+system.physmem.avgGap                     10089780.13                       # Average gap between requests
+system.physmem.pageHitRate                      79.38                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  230746320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  125903250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 702187200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                392895360                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy           190045312080                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            90312406830                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           1666579011000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             1948388462040                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.625842                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   2772320056250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     97160180000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     40149801500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     40187145000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  212163840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  115764000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  212292360                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  115834125                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                 596715600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                370668960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           190044294960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            88503009660                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           1668156858000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             1947999475020                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.495738                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   2774969217000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     97159660000                       # Time in different power states
+system.physmem_1.writeEnergy                370675440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy           190045312080                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            88507788255                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           1668162009750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             1948010627610                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.495988                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   2774979616000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     97160180000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     37524675500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     37531027500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
@@ -384,58 +378,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.walks                     6385                       # Table walker walks requested
-system.cpu0.dtb.walker.walksShort                6385                       # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1824                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4559                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore            2                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples         6383                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0           6383    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total         6383                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples         5318                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 13413.689357                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 11614.000174                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev  7416.349168                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383         3990     75.03%     75.03% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1324     24.90%     99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks                     6370                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                6370                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1         1827                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2         4542                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore            1                       # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples         6369                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           6369    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         6369                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples         5319                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 13473.303252                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 11679.114902                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev  7408.984019                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383         3974     74.71%     74.71% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767         1341     25.21%     99.92% # Table walker service (enqueue to completion) latency
 system.cpu0.dtb.walker.walkCompletionTime::131072-147455            4      0.08%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total         5318                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples   1993677436                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean    -0.003389                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     2000434000    100.34%    100.34% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1       -6756564     -0.34%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total   1993677436                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K         3519     66.20%     66.20% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M         1797     33.80%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total         5316                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6385                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total         5319                       # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples   2989035968                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean     0.330748                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev     0.470482                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0     2000419000     66.93%     66.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1      988616968     33.07%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total   2989035968                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3517     66.13%     66.13% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1801     33.87%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         5318                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         6370                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6385                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5316                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         6370                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         5318                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5316                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total        11701                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         5318                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        11688                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    12043498                       # DTB read hits
-system.cpu0.dtb.read_misses                      5581                       # DTB read misses
-system.cpu0.dtb.write_hits                    9607194                       # DTB write hits
-system.cpu0.dtb.write_misses                      804                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        2940                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
+system.cpu0.dtb.read_hits                    12041748                       # DTB read hits
+system.cpu0.dtb.read_misses                      5569                       # DTB read misses
+system.cpu0.dtb.write_hits                    9609883                       # DTB write hits
+system.cpu0.dtb.write_misses                      801                       # DTB write misses
+system.cpu0.dtb.flush_tlb                        2941                       # Number of times complete TLB was flushed
+system.cpu0.dtb.flush_tlb_mva                     437                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    3980                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    3992                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   867                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   859                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      217                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                12049079                       # DTB read accesses
-system.cpu0.dtb.write_accesses                9607998                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      214                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                12047317                       # DTB read accesses
+system.cpu0.dtb.write_accesses                9610684                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         21650692                       # DTB hits
-system.cpu0.dtb.misses                           6385                       # DTB misses
-system.cpu0.dtb.accesses                     21657077                       # DTB accesses
+system.cpu0.dtb.hits                         21651631                       # DTB hits
+system.cpu0.dtb.misses                           6370                       # DTB misses
+system.cpu0.dtb.accesses                     21658001                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -465,131 +460,131 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.walks                     3199                       # Table walker walks requested
-system.cpu0.itb.walker.walksShort                3199                       # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1          683                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2516                       # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples         3199                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0           3199    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total         3199                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples         2347                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 13274.818918                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 11551.422255                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev  6527.623179                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::4096-6143          600     25.56%     25.56% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::10240-12287          656     27.95%     53.52% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::12288-14335          193      8.22%     61.74% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::14336-16383          387     16.49%     78.23% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-18431            3      0.13%     78.36% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::22528-24575          500     21.30%     99.66% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-26623            8      0.34%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total         2347                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks                     3218                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3218                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1          687                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2         2531                       # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples         3218                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3218    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3218                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples         2361                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 13277.424820                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 11544.822386                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev  6544.721859                       # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::4096-6143          607     25.71%     25.71% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::10240-12287          660     27.95%     53.66% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::12288-14335          188      7.96%     61.63% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::14336-16383          387     16.39%     78.02% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-18431            3      0.13%     78.14% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::22528-24575          510     21.60%     99.75% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-26623            6      0.25%    100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total         2361                       # Table walker service (enqueue to completion) latency
 system.cpu0.itb.walker.walksPending::samples   2000380500                       # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::0     2000380500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu0.itb.walker.walksPending::total   2000380500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K         1664     70.90%     70.90% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M          683     29.10%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total         2347                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K         1674     70.90%     70.90% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          687     29.10%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2361                       # Table walker page sizes translated
 system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3199                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3199                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3218                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3218                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2347                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2347                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total         5546                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    56739503                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3199                       # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2361                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2361                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         5579                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits                    56731893                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3218                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        2940                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                     441                       # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb                        2941                       # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb_mva                     437                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2369                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2380                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                56742702                       # ITB inst accesses
-system.cpu0.itb.hits                         56739503                       # DTB hits
-system.cpu0.itb.misses                           3199                       # DTB misses
-system.cpu0.itb.accesses                     56742702                       # DTB accesses
-system.cpu0.numCycles                      2910044532                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                56735111                       # ITB inst accesses
+system.cpu0.itb.hits                         56731893                       # DTB hits
+system.cpu0.itb.misses                           3218                       # DTB misses
+system.cpu0.itb.accesses                     56735111                       # DTB accesses
+system.cpu0.numCycles                      2910044257                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    3033                       # number of quiesce instructions executed
-system.cpu0.committedInsts                   55201459                       # Number of instructions committed
-system.cpu0.committedOps                     66609946                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             58847772                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  5145                       # Number of float alu accesses
-system.cpu0.num_func_calls                    4820077                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      7555989                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    58847772                       # number of integer instructions
-system.cpu0.num_fp_insts                         5145                       # number of float instructions
-system.cpu0.num_int_register_reads          106933475                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          40499308                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3730                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1418                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           240486031                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           25664833                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     22274491                       # number of memory refs
-system.cpu0.num_load_insts                   12198391                       # Number of load instructions
-system.cpu0.num_store_insts                  10076100                       # Number of store instructions
-system.cpu0.num_idle_cycles              2694628360.005429                       # Number of idle cycles
-system.cpu0.num_busy_cycles              215416171.994570                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.074025                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.925975                       # Percentage of idle cycles
-system.cpu0.Branches                         12743161                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                  131      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 45792912     67.22%     67.22% # Class of executed instruction
-system.cpu0.op_class::IntMult                   56104      0.08%     67.30% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc              3963      0.01%     67.30% # Class of executed instruction
+system.cpu0.kern.inst.quiesce                    3034                       # number of quiesce instructions executed
+system.cpu0.committedInsts                   55192175                       # Number of instructions committed
+system.cpu0.committedOps                     66601030                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             58838667                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  5226                       # Number of float alu accesses
+system.cpu0.num_func_calls                    4816070                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      7555391                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    58838667                       # number of integer instructions
+system.cpu0.num_fp_insts                         5226                       # number of float instructions
+system.cpu0.num_int_register_reads          106920418                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          40489001                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3747                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1482                       # number of times the floating registers were written
+system.cpu0.num_cc_register_reads           240444662                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           25665883                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     22275144                       # number of memory refs
+system.cpu0.num_load_insts                   12196401                       # Number of load instructions
+system.cpu0.num_store_insts                  10078743                       # Number of store instructions
+system.cpu0.num_idle_cycles              2694612539.353109                       # Number of idle cycles
+system.cpu0.num_busy_cycles              215431717.646891                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.074030                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.925970                       # Percentage of idle cycles
+system.cpu0.Branches                         12738975                       # Number of branches fetched
+system.cpu0.op_class::No_OpClass                  134      0.00%      0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu                 45781986     67.21%     67.21% # Class of executed instruction
+system.cpu0.op_class::IntMult                   56167      0.08%     67.29% # Class of executed instruction
+system.cpu0.op_class::IntDiv                        0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::FloatAdd                      0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::FloatCmp                      0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::FloatCvt                      0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::FloatMult                     0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::FloatDiv                      0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt                     0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdAdd                       0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdAlu                       0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdCmp                       0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdCvt                       0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdMisc                      0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdMult                      0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdShift                     0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt                      0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.29% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc              3968      0.01%     67.30% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.30% # Class of executed instruction
 system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.30% # Class of executed instruction
 system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.30% # Class of executed instruction
-system.cpu0.op_class::MemRead                12198391     17.91%     85.21% # Class of executed instruction
-system.cpu0.op_class::MemWrite               10076100     14.79%    100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead                12196401     17.90%     85.20% # Class of executed instruction
+system.cpu0.op_class::MemWrite               10078743     14.80%    100.00% # Class of executed instruction
 system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  68127601                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements           819018                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.702192                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           43232909                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           819530                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            52.753296                       # Average number of references to valid blocks.
+system.cpu0.op_class::total                  68117399                       # Class of executed instruction
+system.cpu0.dcache.tags.replacements           819062                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.702235                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           43234880                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           819574                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            52.752869                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle       1736913500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data    43.309115                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   468.393077                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data    43.309006                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   468.393230                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.084588                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.914830                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.914831                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999418                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
@@ -597,124 +592,124 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1          344
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2          107                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        177098246                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       177098246                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data     11355856                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     11755360                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       23111216                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      9224406                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      9598440                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total      18822846                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190279                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       202400                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       392679                       # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       213881                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       229331                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       443212                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       221919                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       238270                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       460189                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     20580262                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     21353800                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        41934062                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     20770541                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     21556200                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       42326741                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       199428                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       200396                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       399824                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       149476                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       149150                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       298626                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data        58742                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        59581                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       118323                       # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10843                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        11913                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        22756                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        177106290                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       177106290                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data     11353905                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data     11758208                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       23112113                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      9226963                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      9596855                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total      18823818                       # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190234                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data       202489                       # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total       392723                       # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       213697                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       229550                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       443247                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       221754                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       238460                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       460214                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     20580868                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     21355063                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        41935931                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     20771102                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     21557552                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       42328654                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       199783                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       200066                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       399849                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       149794                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data       148846                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       298640                       # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data        58818                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data        59499                       # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total       118317                       # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10855                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        11895                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        22750                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu1.data            2                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       348904                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       349546                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        698450                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       407646                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       409127                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       816773                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3300764500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3177768500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   6478533000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9862313500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9244759000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  19107072500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    137644000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    156454000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    294098000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data       349577                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       348912                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        698489                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       408395                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       408411                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       816806                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3309369500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3172445000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6481814500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9848447000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9257158000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  19105605000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    137223000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    156952000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    294175000                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       164000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  13163078000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  12422527500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  25585605500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  13163078000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  12422527500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  25585605500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     11555284                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     11955756                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     23511040                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      9373882                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      9747590                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     19121472                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       249021                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       261981                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       511002                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       224724                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       241244                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       465968                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       221919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       238272                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       460191                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     20929166                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     21703346                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     42632512                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     21178187                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     21965327                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     43143514                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.017259                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.016761                       # miss rate for ReadReq accesses
+system.cpu0.dcache.demand_miss_latency::cpu0.data  13157816500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  12429603000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  25587419500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  13157816500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  12429603000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  25587419500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data     11553688                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data     11958274                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     23511962                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      9376757                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      9745701                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     19122458                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       249052                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       261988                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total       511040                       # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       224552                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       241445                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       465997                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       221754                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       238462                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       460216                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     20930445                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     21703975                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     42634420                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     21179497                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     21965963                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     43145460                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.017292                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.016730                       # miss rate for ReadReq accesses
 system.cpu0.dcache.ReadReq_miss_rate::total     0.017006                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015946                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015301                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015975                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015273                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.015617                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.235892                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227425                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.231551                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048250                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049382                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048836                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.236168                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.227106                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total     0.231522                       # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048341                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.049266                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048820                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000008                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016671                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016106                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.016702                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.016076                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     0.016383                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019248                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.018626                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.018932                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16551.158814                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15857.444759                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 16203.462023                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65979.244160                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 61982.963460                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 63983.285112                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12694.272803                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13133.047931                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12923.976094                       # average LoadLockedReq miss latency
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.019283                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.018593                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.018931                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16564.820330                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15856.992193                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 16210.655773                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65746.605338                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 62192.857047                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 63975.371685                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12641.455550                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13194.787726                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12930.769231                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37726.933483                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35539.034920                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 36631.978667                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32290.462804                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30363.499598                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 31325.234184                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37639.251152                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35623.890838                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 36632.530362                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32218.358452                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30434.055400                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 31326.189450                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs           76                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
@@ -723,201 +718,201 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs            4
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       683842                       # number of writebacks
-system.cpu0.dcache.writebacks::total           683842                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          485                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          439                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          924                       # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7005                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7232                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14237                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          485                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data          439                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          924                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          485                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data          439                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          924                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       198943                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       199957                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       398900                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       149476                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       149150                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       298626                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        57623                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58651                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       116274                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3838                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4681                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8519                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       683867                       # number of writebacks
+system.cpu0.dcache.writebacks::total           683867                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          471                       # number of ReadReq MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_hits::total          925                       # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         7013                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         7211                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total        14224                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          471                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data          454                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          925                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          471                       # number of overall MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total          925                       # number of overall MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       149794                       # number of WriteReq MSHR misses
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+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data        57717                       # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        58554                       # number of SoftPFReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         3842                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         4684                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8526                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            2                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       348419                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       349107                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       697526                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       406042                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       407758                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       813800                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15006                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16132                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       349106                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       348458                       # number of demand (read+write) MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        14993                       # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16145                       # number of ReadReq MSHR uncacheable
 system.cpu0.dcache.ReadReq_mshr_uncacheable::total        31138                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        13389                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14200                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        13371                       # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14218                       # number of WriteReq MSHR uncacheable
 system.cpu0.dcache.WriteReq_mshr_uncacheable::total        27589                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        28395                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        30332                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        28364                       # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        30363                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.overall_mshr_uncacheable_misses::total        58727                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3085102500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2965375000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6050477500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9712837500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9095609000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18808446500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    798019000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    816464500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1614483500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     52409500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62952500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    115362000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3093759000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2959743000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6053502000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9698653000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9108312000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  18806965000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data    795616000                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    818334500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   1613950500                       # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     52173500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     63283500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    115457000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       162000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       162000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12797940000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  12060984000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  24858924000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13595959000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  12877448500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  26473407500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3049211500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3229832500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6279044000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2494979500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2594954500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5089934000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5544191000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5824787000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11368978000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017217                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016725                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016966                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015946                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015301                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  12792412000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  12068055000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  24860467000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  13588028000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  12886389500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  26474417500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3047137000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3231000000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6278137000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2491876500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2598064000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5089940500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5539013500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5829064000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11368077500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.017251                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.016692                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.016967                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015975                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015273                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.015617                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231398                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.223875                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227541                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017079                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019404                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018282                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.231747                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.223499                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.227518                       # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.017110                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.019400                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.018296                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000008                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016648                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016085                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.016361                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019173                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.018564                       # mshr miss rate for overall accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.016679                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.016055                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.016362                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.019208                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.018529                       # mshr miss rate for overall accesses
 system.cpu0.dcache.overall_mshr_miss_rate::total     0.018863                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15507.469476                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14830.063464                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15167.905490                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64979.244160                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60982.963460                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62983.285112                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13848.966558                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13920.725989                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13885.163493                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13655.419489                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13448.515275                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.730250                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.191338                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14827.480312                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15174.574606                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64746.605338                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61192.857047                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62975.371685                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13784.777449                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13975.723264                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13880.937637                       # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13579.776158                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13510.567891                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.754633                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36731.464128                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34548.101298                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.705941                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33484.119869                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31581.105705                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.606414                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203199.486872                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200212.775849                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201652.129231                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186345.470162                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182743.274648                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.427743                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195252.368375                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192034.386127                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193590.307695                       # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36643.346147                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34632.739096                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.976495                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33400.343638                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31660.957171                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.448432                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203237.310745                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200123.877361                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.000835                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186364.258470                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182730.623154                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.663344                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195283.228741                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191979.185193                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.974032                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements          1695285                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.436603                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          113852008                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs          1695797                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.137758                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements          1695832                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.436658                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          113855734                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs          1696344                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            67.118305                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      29075840500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst    59.971705                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   450.464899                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.117132                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.879814                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.996946                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst    60.007721                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   450.428938                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.117203                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.879744                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.996947                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          262                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        117243614                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       117243614                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     55899037                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     57952971                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      113852008                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     55899037                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     57952971                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       113852008                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     55899037                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     57952971                       # number of overall hits
-system.cpu0.icache.overall_hits::total      113852008                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       840466                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       855337                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1695803                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       840466                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       855337                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1695803                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       840466                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       855337                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1695803                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11890019000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  12374432000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  24264451000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  11890019000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  12374432000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  24264451000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  11890019000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  12374432000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  24264451000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     56739503                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     58808308                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    115547811                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     56739503                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     58808308                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    115547811                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     56739503                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     58808308                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    115547811                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014813                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014544                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014676                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014813                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014544                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014676                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014813                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014544                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014676                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14146.936342                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.317560                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14308.531710                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14146.936342                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14467.317560                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14308.531710                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14146.936342                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14467.317560                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14308.531710                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses        117248434                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       117248434                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     55890585                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     57965149                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      113855734                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     55890585                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     57965149                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       113855734                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     55890585                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     57965149                       # number of overall hits
+system.cpu0.icache.overall_hits::total      113855734                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       841308                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       855042                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1696350                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       841308                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       855042                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1696350                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       841308                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       855042                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1696350                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11907607000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  12366012000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  24273619000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  11907607000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst  12366012000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  24273619000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  11907607000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst  12366012000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  24273619000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     56731893                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     58820191                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    115552084                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     56731893                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     58820191                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    115552084                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     56731893                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     58820191                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    115552084                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014830                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014537                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014680                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014830                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014537                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014680                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014830                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014537                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014680                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14153.683312                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14462.461493                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.322369                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14153.683312                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14462.461493                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14309.322369                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14153.683312                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14462.461493                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14309.322369                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -926,56 +921,56 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks      1695285                       # number of writebacks
-system.cpu0.icache.writebacks::total          1695285                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       840466                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       855337                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total      1695803                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       840466                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       855337                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total      1695803                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       840466                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       855337                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total      1695803                       # number of overall MSHR misses
+system.cpu0.icache.writebacks::writebacks      1695832                       # number of writebacks
+system.cpu0.icache.writebacks::total          1695832                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       841308                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       855042                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total      1696350                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       841308                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       855042                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total      1696350                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       841308                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       855042                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total      1696350                       # number of overall MSHR misses
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst         5645                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         3377                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.ReadReq_mshr_uncacheable::total         9022                       # number of ReadReq MSHR uncacheable
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst         5645                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         3377                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.overall_mshr_uncacheable_misses::total         9022                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11049553000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11519095000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  22568648000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11049553000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11519095000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  22568648000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11049553000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11519095000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  22568648000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11066299000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  11510970000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  22577269000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11066299000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  11510970000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  22577269000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11066299000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  11510970000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  22577269000                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    713903000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    428990000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1142893000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    713903000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    428990000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total   1142893000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014813                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014544                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014676                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014813                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014544                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014676                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014813                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014544                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014676                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13146.936342                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13467.317560                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13308.531710                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13146.936342                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13467.317560                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13308.531710                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13146.936342                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13467.317560                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13308.531710                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014830                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014537                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014680                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014830                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014537                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014680                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014830                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014537                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014680                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13153.683312                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13462.461493                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.322369                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13153.683312                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13462.461493                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.322369                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13153.683312                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13462.461493                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.322369                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671                       # average ReadReq mshr uncacheable latency
@@ -1012,54 +1007,54 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.walks                     6953                       # Table walker walks requested
-system.cpu1.dtb.walker.walksShort                6953                       # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         2226                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4727                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples         6953                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0           6953    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total         6953                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples         5856                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 13269.296448                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 11561.565854                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev  7342.287931                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767         5855     99.98%     99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks                     6967                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                6967                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1         2209                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         4758                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples         6967                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           6967    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         6967                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples         5854                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 13310.386061                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11595.564813                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev  7355.876792                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767         5853     99.98%     99.98% # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walkCompletionTime::262144-294911            1      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total         5856                       # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total         5854                       # Table walker service (enqueue to completion) latency
 system.cpu1.dtb.walker.walksPending::samples   1639416500                       # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::0     1639416500    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.dtb.walker.walksPending::total   1639416500                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K         3650     62.33%     62.33% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M         2206     37.67%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total         5856                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6953                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K         3666     62.62%     62.62% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         2188     37.38%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5854                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6967                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6953                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5856                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6967                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5854                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5856                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        12809                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5854                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        12821                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    12475099                       # DTB read hits
-system.cpu1.dtb.read_misses                      5924                       # DTB read misses
-system.cpu1.dtb.write_hits                    9998125                       # DTB write hits
-system.cpu1.dtb.write_misses                     1029                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        2942                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
+system.cpu1.dtb.read_hits                    12477838                       # DTB read hits
+system.cpu1.dtb.read_misses                      5947                       # DTB read misses
+system.cpu1.dtb.write_hits                    9996447                       # DTB write hits
+system.cpu1.dtb.write_misses                     1020                       # DTB write misses
+system.cpu1.dtb.flush_tlb                        2941                       # Number of times complete TLB was flushed
+system.cpu1.dtb.flush_tlb_mva                     480                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    4683                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    4688                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   921                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   911                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      228                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                12481023                       # DTB read accesses
-system.cpu1.dtb.write_accesses                9999154                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      231                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                12483785                       # DTB read accesses
+system.cpu1.dtb.write_accesses                9997467                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         22473224                       # DTB hits
-system.cpu1.dtb.misses                           6953                       # DTB misses
-system.cpu1.dtb.accesses                     22480177                       # DTB accesses
+system.cpu1.dtb.hits                         22474285                       # DTB hits
+system.cpu1.dtb.misses                           6967                       # DTB misses
+system.cpu1.dtb.accesses                     22481252                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -1089,85 +1084,85 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.walks                     3510                       # Table walker walks requested
-system.cpu1.itb.walker.walksShort                3510                       # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1          846                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2664                       # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples         3510                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0           3510    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total         3510                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples         2707                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 13960.103436                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 12104.099399                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev  7184.126564                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-16383         1964     72.55%     72.55% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-32767          742     27.41%     99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks                     3507                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                3507                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1          840                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2         2667                       # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples         3507                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           3507    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         3507                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples         2709                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 13994.462901                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 12131.377414                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev  7198.145608                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-16383         1959     72.31%     72.31% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-32767          749     27.65%     99.96% # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walkCompletionTime::131072-147455            1      0.04%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total         2707                       # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total         2709                       # Table walker service (enqueue to completion) latency
 system.cpu1.itb.walker.walksPending::samples   1638889000                       # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::0     1638889000    100.00%    100.00% # Table walker pending requests distribution
 system.cpu1.itb.walker.walksPending::total   1638889000                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K         1861     68.75%     68.75% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M          846     31.25%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total         2707                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K         1869     68.99%     68.99% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          840     31.01%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2709                       # Table walker page sizes translated
 system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3510                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3510                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3507                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3507                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2707                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2707                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total         6217                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    58808308                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3510                       # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2709                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2709                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         6216                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits                    58820191                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3507                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        2942                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                     476                       # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb                        2941                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb_mva                     480                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2708                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2713                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                58811818                       # ITB inst accesses
-system.cpu1.itb.hits                         58808308                       # DTB hits
-system.cpu1.itb.misses                           3510                       # DTB misses
-system.cpu1.itb.accesses                     58811818                       # DTB accesses
-system.cpu1.numCycles                      2909262869                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                58823698                       # ITB inst accesses
+system.cpu1.itb.hits                         58820191                       # DTB hits
+system.cpu1.itb.misses                           3507                       # DTB misses
+system.cpu1.itb.accesses                     58823698                       # DTB accesses
+system.cpu1.numCycles                      2909297686                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   57249193                       # Number of instructions committed
-system.cpu1.committedOps                     68969707                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             61038090                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5951                       # Number of float alu accesses
-system.cpu1.num_func_calls                    5071147                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      7673896                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    61038090                       # number of integer instructions
-system.cpu1.num_fp_insts                         5951                       # number of float instructions
-system.cpu1.num_int_register_reads          111115264                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          42140927                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                4654                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1298                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           249224724                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           26227815                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     23129732                       # number of memory refs
-system.cpu1.num_load_insts                   12642519                       # Number of load instructions
-system.cpu1.num_store_insts                  10487213                       # Number of store instructions
-system.cpu1.num_idle_cycles              2689871255.481362                       # Number of idle cycles
-system.cpu1.num_busy_cycles              219391613.518638                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.075411                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.924589                       # Percentage of idle cycles
-system.cpu1.Branches                         13171953                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                 2206      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 47377307     67.13%     67.14% # Class of executed instruction
-system.cpu1.op_class::IntMult                   58319      0.08%     67.22% # Class of executed instruction
+system.cpu1.committedInsts                   57262734                       # Number of instructions committed
+system.cpu1.committedOps                     68983998                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             61052130                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  5870                       # Number of float alu accesses
+system.cpu1.num_func_calls                    5075478                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      7674901                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    61052130                       # number of integer instructions
+system.cpu1.num_fp_insts                         5870                       # number of float instructions
+system.cpu1.num_int_register_reads          111137302                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          42154976                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4637                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1234                       # number of times the floating registers were written
+system.cpu1.num_cc_register_reads           249286409                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           26228170                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                     23131429                       # number of memory refs
+system.cpu1.num_load_insts                   12645834                       # Number of load instructions
+system.cpu1.num_store_insts                  10485595                       # Number of store instructions
+system.cpu1.num_idle_cycles              2689887383.006891                       # Number of idle cycles
+system.cpu1.num_busy_cycles              219410302.993109                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.075417                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.924583                       # Percentage of idle cycles
+system.cpu1.Branches                         13176890                       # Number of branches fetched
+system.cpu1.op_class::No_OpClass                 2203      0.00%      0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu                 47391308     67.14%     67.14% # Class of executed instruction
+system.cpu1.op_class::IntMult                   58256      0.08%     67.22% # Class of executed instruction
 system.cpu1.op_class::IntDiv                        0      0.00%     67.22% # Class of executed instruction
 system.cpu1.op_class::FloatAdd                      0      0.00%     67.22% # Class of executed instruction
 system.cpu1.op_class::FloatCmp                      0      0.00%     67.22% # Class of executed instruction
@@ -1191,21 +1186,22 @@ system.cpu1.op_class::SimdFloatAlu                  0      0.00%     67.22% # Cl
 system.cpu1.op_class::SimdFloatCmp                  0      0.00%     67.22% # Class of executed instruction
 system.cpu1.op_class::SimdFloatCvt                  0      0.00%     67.22% # Class of executed instruction
 system.cpu1.op_class::SimdFloatDiv                  0      0.00%     67.22% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc              4478      0.01%     67.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc              4483      0.01%     67.23% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMult                 0      0.00%     67.23% # Class of executed instruction
 system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     67.23% # Class of executed instruction
 system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     67.23% # Class of executed instruction
-system.cpu1.op_class::MemRead                12642519     17.91%     85.14% # Class of executed instruction
-system.cpu1.op_class::MemWrite               10487213     14.86%    100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead                12645834     17.92%     85.15% # Class of executed instruction
+system.cpu1.op_class::MemWrite               10485595     14.85%    100.00% # Class of executed instruction
 system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
 system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  70572042                       # Class of executed instruction
+system.cpu1.op_class::total                  70587679                       # Class of executed instruction
 system.iobus.trans_dist::ReadReq                30177                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30177                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               59014                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              59014                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54170                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          124                       # Packet count per connected master and slave (bytes)
@@ -1221,16 +1217,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       105478                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.ide.dma::total        72904                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count::total                  178382                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67887                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           86                       # Cumulative packet size per connected master and slave (bytes)
@@ -1246,26 +1240,25 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
 system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.realview.ide.dma::total      2321056                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size::total                  2480181                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             46335000                       # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy             46334000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                98000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                30000                       # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy               336000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                16000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy                30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                95000                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy               644000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy                16000                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer7.occupancy                95000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
+system.iobus.reqLayer8.occupancy               644000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer10.occupancy               21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer13.occupancy               12000                       # Layer occupancy (ticks)
@@ -1286,31 +1279,25 @@ system.iobus.reqLayer20.occupancy                9000                       # La
 system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer21.occupancy               12000                       # Layer occupancy (ticks)
 system.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6286500                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6288000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy              172500                       # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy            36457000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy            36458500                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy           186225545                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer26.occupancy              126500                       # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy           186202055                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer28.occupancy               37000                       # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            82688000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer3.occupancy            36728000                       # Layer occupancy (ticks)
 system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                36418                       # number of replacements
-system.iocache.tags.tagsinuse                1.084308                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.084397                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                36434                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle         313834390000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide     1.084308                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide     0.067769                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.067769                       # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide     1.084397                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide     0.067775                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.067775                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -1324,14 +1311,14 @@ system.iocache.demand_misses::realview.ide          228                       #
 system.iocache.demand_misses::total               228                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ide          228                       # number of overall misses
 system.iocache.overall_misses::total              228                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     28182877                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     28182877                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   4712497178                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   4712497178                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide     28182877                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total     28182877                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide     28182877                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total     28182877                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide     28184876                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     28184876                       # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide   4715128669                       # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total   4715128669                       # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide     28184876                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total     28184876                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide     28184876                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total     28184876                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ide          228                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            228                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
@@ -1348,19 +1335,19 @@ system.iocache.demand_miss_rate::realview.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 123609.109649                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 123609.109649                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130093.230400                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 130093.230400                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 123609.109649                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 123609.109649                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 123609.109649                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 123609.109649                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           617                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 123617.877193                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 123617.877193                       # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130165.875359                       # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 130165.875359                       # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 123617.877193                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 123617.877193                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 123617.877193                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 123617.877193                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs           572                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                   60                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.283333                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs     9.533333                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -1374,14 +1361,14 @@ system.iocache.demand_mshr_misses::realview.ide          228
 system.iocache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ide          228                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total          228                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     16782877                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     16782877                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2901297178                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2901297178                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide     16782877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total     16782877                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide     16782877                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total     16782877                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide     16784876                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     16784876                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2903928669                       # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total   2903928669                       # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide     16784876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total     16784876                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide     16784876                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total     16784876                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
@@ -1390,37 +1377,37 @@ system.iocache.demand_mshr_miss_rate::realview.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73609.109649                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 73609.109649                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80093.230400                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80093.230400                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 73609.109649                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 73609.109649                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 73609.109649                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 73609.109649                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73617.877193                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 73617.877193                       # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80165.875359                       # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80165.875359                       # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 73617.877193                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 73617.877193                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 73617.877193                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 73617.877193                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                    87564                       # number of replacements
-system.l2c.tags.tagsinuse                64865.205876                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4550112                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   152799                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    29.778415                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    87560                       # number of replacements
+system.l2c.tags.tagsinuse                64865.201521                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    4551354                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   152795                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    29.787323                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   50199.141301                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.905024                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4090.389058                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2504.726247                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.838093                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks   50199.128097                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.905025                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4090.007642                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2504.647366                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.838092                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.itb.walker     0.000605                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     5610.428826                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2455.776722                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     5610.818089                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2455.856604                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.765978                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000029                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.062414                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.038219                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.062409                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.038218                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000043                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.085608                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.037472                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.085614                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.037473                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.989764                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_blocks::1024        65231                       # Occupied blocks per task id
@@ -1428,228 +1415,228 @@ system.l2c.tags.age_task_id_blocks_1023::4            4                       #
 system.l2c.tags.age_task_id_blocks_1024::0           13                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::2         2129                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6848                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        56203                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6852                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        56199                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
 system.l2c.tags.occ_task_id_percent::1024     0.995346                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 40556804                       # Number of tag accesses
-system.l2c.tags.data_accesses                40556804                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         5806                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         3022                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         6360                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         3498                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  18686                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks       683842                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          683842                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks      1664516                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total         1664516                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data              14                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data               9                       # number of UpgradeReq hits
+system.l2c.tags.tag_accesses                 40566832                       # Number of tag accesses
+system.l2c.tags.data_accesses                40566832                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         5848                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         3044                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         6379                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         3501                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  18772                       # number of ReadReq hits
+system.l2c.WritebackDirty_hits::writebacks       683867                       # number of WritebackDirty hits
+system.l2c.WritebackDirty_hits::total          683867                       # number of WritebackDirty hits
+system.l2c.WritebackClean_hits::writebacks      1665046                       # number of WritebackClean hits
+system.l2c.WritebackClean_hits::total         1665046                       # number of WritebackClean hits
+system.l2c.UpgradeReq_hits::cpu0.data              13                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              10                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  23                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            80852                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            86095                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               166947                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        832656                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        845134                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total           1677790                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       253841                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       257681                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           511522                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          5806                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          3022                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              832656                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              334693                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          6360                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          3498                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              845134                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              343776                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2374945                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         5806                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         3022                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             832656                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             334693                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         6360                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         3498                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             845134                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             343776                       # number of overall hits
-system.l2c.overall_hits::total                2374945                       # number of overall hits
+system.l2c.ReadExReq_hits::cpu0.data            81302                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            85662                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               166964                       # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst        833466                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst        844870                       # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total           1678336                       # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data       254311                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data       257239                       # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total           511550                       # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          5848                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu0.inst              833466                       # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.dtb.walker          6379                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          3501                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              844870                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              342901                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2375622                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         5848                       # number of overall hits
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 system.l2c.demand_miss_rate::cpu1.itb.walker     0.000286                       # miss rate for demand accesses
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 system.l2c.overall_miss_rate::cpu1.itb.walker     0.000286                       # miss rate for overall accesses
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 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker       132625                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker       133000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::total       132750                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   757.586705                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   595.729013                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   677.425237                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   766.447368                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   589.285714                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   677.737226                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
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 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       132625                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 130547.099589                       # average overall miss latency
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 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 130769.755571                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       132625                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132833.333333                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.itb.walker       133000                       # average overall miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1664,231 +1651,231 @@ system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            4
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            3                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::total               8                       # number of ReadReq MSHR misses
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 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
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 system.l2c.ReadCleanReq_mshr_misses::total        17979                       # number of ReadCleanReq MSHR misses
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 system.l2c.ReadSharedReq_mshr_misses::total        12171                       # number of ReadSharedReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker            4                       # number of demand (read+write) MSHR misses
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-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2431594500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   4772530500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3029132000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   6918926500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2338041000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2434495500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   4772536500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    643340500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5202524500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5197717500                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    386777500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5459722500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  11692365000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000688                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for ReadReq accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5463627500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  11691463000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000684                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000470                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000286                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.000428                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.989986                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.993416                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.991682                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.000426                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.990587                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.992764                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.991676                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.453990                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.417423                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.435725                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.009271                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011910                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010602                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.025203                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.021300                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023241                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000688                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009271                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.180642                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for demand accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.452191                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.419099                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.435698                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.009301                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011876                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total     0.010599                       # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.025147                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.021347                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total     0.023239                       # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000684                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009301                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.180000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000470                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000286                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011910                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.163709                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.062775                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000688                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009271                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.180642                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000471                       # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011876                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.164296                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.062758                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000684                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009301                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.180000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000470                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000286                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011910                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.163709                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.062775                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011876                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.164296                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.062758                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::total       122750                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70812.861272                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70803.387334                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70808.169220                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70814.692982                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70806.122449                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70810.401460                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116824.829679                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117354.534107                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 117078.304141                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120547.099589                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120769.755571                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120673.257690                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122722.763980                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121158.612696                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122002.054063                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116772.667670                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117387.576454                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 117067.460225                       # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120882.108626                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120713.314950                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120786.779020                       # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122840.091463                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121422.651934                       # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122186.632158                       # average ReadSharedReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120547.099589                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117349.408448                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120882.108626                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117312.938605                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120769.755571                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117671.540656                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 117861.634983                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120713.314950                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117723.428716                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 117879.805244                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker       122625                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120547.099589                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117349.408448                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120882.108626                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117312.938605                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker       123000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120769.755571                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117671.540656                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 117861.634983                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120713.314950                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117723.428716                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 117879.805244                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190696.288151                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190734.109251                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187709.397471                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172306.635956                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174840.241990                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171239.049296                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.715720                       # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187620.439765                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172284.026394                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174859.098048                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171226.297651                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.933198                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183219.739391                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183250.511211                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179998.763682                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 172583.580569                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179943.599117                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 172570.266720                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.membus.trans_dist::ReadReq               40160                       # Transaction distribution
 system.membus.trans_dist::ReadResp              70546                       # Transaction distribution
 system.membus.trans_dist::WriteReq              27589                       # Transaction distribution
 system.membus.trans_dist::WriteResp             27589                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty       117374                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             6393                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4497                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             6389                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4498                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4499                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            127159                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           127159                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4500                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            127155                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           127155                       # Transaction distribution
 system.membus.trans_dist::ReadSharedReq         30386                       # Transaction distribution
 system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
 system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105478                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2104                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       438823                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       546415                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       438813                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       546405                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       108894                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       108894                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 655309                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 655299                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159125                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15302204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     15465557                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     15301948                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total     15465301                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2317120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.pkt_size_system.iocache.mem_side::total      2317120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17782677                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17782421                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                              492                       # Total snoops (count)
-system.membus.snoop_fanout::samples            390002                       # Request fanout histogram
+system.membus.snoop_fanout::samples            389996                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
 system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                  390002    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                  389996    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              390002                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            90453500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              389996                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            90452500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                7500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1722000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1723000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy           823113783                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy           823109916                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          952221498                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          952195249                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           64071640                       # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy           64063181                       # Layer occupancy (ticks)
 system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
 system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
@@ -1931,60 +1918,60 @@ system.realview.mcc.osc_clcd.clock              42105                       # Cl
 system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
 system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
 system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests      5052869                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2537534                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests        38120                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_requests      5053996                       # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests      2538070                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests        38133                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.toL2Bus.snoop_filter.tot_snoops            581                       # Total number of snoops made to the snoop filter.
 system.toL2Bus.snoop_filter.hit_single_snoops          581                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq              74671                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2294380                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq              74719                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2295003                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq             27589                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp            27589                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       801219                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean      1664516                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          134433                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2765                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackDirty       801245                       # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean      1665046                       # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict          134452                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2763                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2767                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           295861                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          295861                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq       1695803                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq       523921                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2765                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           295877                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          295877                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq       1696350                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq       523949                       # Transaction distribution
 system.toL2Bus.trans_dist::InvalidateReq        36224                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5074132                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2573976                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18410                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34795                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7701313                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    215094328                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96414109                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26084                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        48692                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              311583213                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          176501                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          2780821                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.021276                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.144303                       # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5075755                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2574108                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18469                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        34870                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7703202                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    215163192                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     96418525                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        26184                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        48936                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total              311656837                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops                          176461                       # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples          2781455                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean            0.021257                       # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev           0.144239                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                2721656     97.87%     97.87% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  59165      2.13%    100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0                2722330     97.87%     97.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1                  59125      2.13%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
 system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
 system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            2780821                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         4960265000                       # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total            2781455                       # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy         4961451000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           380377                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           380876                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2552726500                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2553547000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1275647499                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1275712000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          11889000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          11923000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          22622000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          22636000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 89c5a64dd..5c3616770 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
@@ -30,7 +30,7 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -841,8 +841,8 @@ frontend_latency=2
 response_latency=2
 use_default_range=false
 width=16
-default=system.pc.pciconfig.pio
-master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+default=system.pc.pci_host.pio
+master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
@@ -869,7 +869,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[19]
+cpu_side=system.iobus.master[18]
 mem_side=system.membus.slave[4]
 
 [system.iocache.tags]
@@ -919,7 +919,7 @@ pio=system.membus.default
 
 [system.pc]
 type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -940,7 +940,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[13]
+pio=system.iobus.master[12]
 
 [system.pc.com_1]
 type=Uart8250
@@ -952,7 +952,7 @@ pio_latency=100000
 platform=system.pc
 system=system
 terminal=system.pc.com_1.terminal
-pio=system.iobus.master[14]
+pio=system.iobus.master[13]
 
 [system.pc.com_1.terminal]
 type=Terminal
@@ -978,7 +978,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[15]
+pio=system.iobus.master[14]
 
 [system.pc.fake_com_3]
 type=IsaFake
@@ -996,7 +996,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[16]
+pio=system.iobus.master[15]
 
 [system.pc.fake_com_4]
 type=IsaFake
@@ -1014,7 +1014,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[17]
+pio=system.iobus.master[16]
 
 [system.pc.fake_floppy]
 type=IsaFake
@@ -1032,7 +1032,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[18]
+pio=system.iobus.master[17]
 
 [system.pc.i_dont_exist1]
 type=IsaFake
@@ -1050,7 +1050,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[11]
+pio=system.iobus.master[10]
 
 [system.pc.i_dont_exist2]
 type=IsaFake
@@ -1068,17 +1068,19 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[12]
+pio=system.iobus.master[11]
 
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
+[system.pc.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=13835058055282163712
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=9223372036854775808
 platform=system.pc
-size=16777216
 system=system
 pio=system.iobus.default
 
@@ -1201,14 +1203,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
 eventq_index=0
+host=system.pc.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=4
 pci_func=0
 pio_latency=30000
-platform=system.pc
 system=system
-config=system.iobus.master[4]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[3]
 
@@ -1232,7 +1233,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/work/gem5/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1255,7 +1256,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1360,7 +1361,7 @@ pio_addr=4273995776
 pio_latency=100000
 system=system
 int_master=system.iobus.slave[2]
-pio=system.iobus.master[10]
+pio=system.iobus.master[9]
 
 [system.pc.south_bridge.keyboard]
 type=I8042
@@ -1374,7 +1375,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
 pio_addr=0
 pio_latency=100000
 system=system
-pio=system.iobus.master[5]
+pio=system.iobus.master[4]
 
 [system.pc.south_bridge.keyboard.keyboard_int_pin]
 type=X86IntSourcePin
@@ -1395,7 +1396,7 @@ pio_addr=9223372036854775840
 pio_latency=100000
 slave=system.pc.south_bridge.pic2
 system=system
-pio=system.iobus.master[6]
+pio=system.iobus.master[5]
 
 [system.pc.south_bridge.pic1.output]
 type=X86IntSourcePin
@@ -1412,7 +1413,7 @@ pio_addr=9223372036854775968
 pio_latency=100000
 slave=Null
 system=system
-pio=system.iobus.master[7]
+pio=system.iobus.master[6]
 
 [system.pc.south_bridge.pic2.output]
 type=X86IntSourcePin
@@ -1427,7 +1428,7 @@ int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=100000
 system=system
-pio=system.iobus.master[8]
+pio=system.iobus.master[7]
 
 [system.pc.south_bridge.pit.int_pin]
 type=X86IntSourcePin
@@ -1441,7 +1442,7 @@ i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=100000
 system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[8]
 
 [system.physmem]
 type=SimpleMemory
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index 3e11aa2b8..ed7b11845 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simout
-Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:27
-gem5 executing on ribera.cs.wisc.edu, pid 9888
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
+gem5 compiled Dec  4 2015 15:10:31
+gem5 started Dec  4 2015 15:38:36
+gem5 executing on e104799-lin, pid 32389
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5112152301500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 51bcfd8ae..85513c27b 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  5.112152                       # Nu
 sim_ticks                                5112152301500                       # Number of ticks simulated
 final_tick                               5112152301500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 934572                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1913274                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            23880410274                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 654088                       # Number of bytes of host memory used
-host_seconds                                   214.07                       # Real time elapsed on the host
+host_inst_rate                                 973581                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1993134                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24877176621                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 614804                       # Number of bytes of host memory used
+host_seconds                                   205.50                       # Real time elapsed on the host
 sim_insts                                   200066731                       # Number of instructions simulated
 sim_ops                                     409580371                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -514,7 +514,6 @@ system.iobus.trans_dist::MessageResp             1696                       # Tr
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
@@ -528,7 +527,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio         2308                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total     20044316                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95246                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95246                       # Packet count per connected master and slave (bytes)
@@ -538,7 +537,6 @@ system.iobus.pkt_count::total                20142954                       # Pa
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
@@ -552,7 +550,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio         4477                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total     10028276                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027768                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027768                       # Cumulative packet size per connected master and slave (bytes)
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 61d43af95..3cac96d35 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
@@ -30,7 +30,7 @@ memories=system.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -837,8 +837,8 @@ frontend_latency=2
 response_latency=2
 use_default_range=false
 width=16
-default=system.pc.pciconfig.pio
-master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+default=system.pc.pci_host.pio
+master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
 
 [system.iocache]
@@ -865,7 +865,7 @@ tags=system.iocache.tags
 tgts_per_mshr=12
 write_buffers=8
 writeback_clean=false
-cpu_side=system.iobus.master[19]
+cpu_side=system.iobus.master[18]
 mem_side=system.membus.slave[4]
 
 [system.iocache.tags]
@@ -915,7 +915,7 @@ pio=system.membus.default
 
 [system.pc]
 type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
 eventq_index=0
 intrctrl=system.intrctrl
 system=system
@@ -936,7 +936,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[13]
+pio=system.iobus.master[12]
 
 [system.pc.com_1]
 type=Uart8250
@@ -948,7 +948,7 @@ pio_latency=100000
 platform=system.pc
 system=system
 terminal=system.pc.com_1.terminal
-pio=system.iobus.master[14]
+pio=system.iobus.master[13]
 
 [system.pc.com_1.terminal]
 type=Terminal
@@ -974,7 +974,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[15]
+pio=system.iobus.master[14]
 
 [system.pc.fake_com_3]
 type=IsaFake
@@ -992,7 +992,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[16]
+pio=system.iobus.master[15]
 
 [system.pc.fake_com_4]
 type=IsaFake
@@ -1010,7 +1010,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[17]
+pio=system.iobus.master[16]
 
 [system.pc.fake_floppy]
 type=IsaFake
@@ -1028,7 +1028,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[18]
+pio=system.iobus.master[17]
 
 [system.pc.i_dont_exist1]
 type=IsaFake
@@ -1046,7 +1046,7 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[11]
+pio=system.iobus.master[10]
 
 [system.pc.i_dont_exist2]
 type=IsaFake
@@ -1064,17 +1064,19 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.iobus.master[12]
+pio=system.iobus.master[11]
 
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
+[system.pc.pci_host]
+type=GenericPciHost
 clk_domain=system.clk_domain
+conf_base=13835058055282163712
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
-pio_addr=0
-pio_latency=30000
+pci_dma_base=0
+pci_mem_base=0
+pci_pio_base=9223372036854775808
 platform=system.pc
-size=16777216
 system=system
 pio=system.iobus.default
 
@@ -1197,14 +1199,13 @@ config_latency=20000
 ctrl_offset=0
 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
 eventq_index=0
+host=system.pc.pci_host
 io_shift=0
 pci_bus=0
 pci_dev=4
 pci_func=0
 pio_latency=30000
-platform=system.pc
 system=system
-config=system.iobus.master[4]
 dma=system.iobus.slave[1]
 pio=system.iobus.master[3]
 
@@ -1228,7 +1229,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/work/gem5/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1251,7 +1252,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1356,7 +1357,7 @@ pio_addr=4273995776
 pio_latency=100000
 system=system
 int_master=system.iobus.slave[2]
-pio=system.iobus.master[10]
+pio=system.iobus.master[9]
 
 [system.pc.south_bridge.keyboard]
 type=I8042
@@ -1370,7 +1371,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
 pio_addr=0
 pio_latency=100000
 system=system
-pio=system.iobus.master[5]
+pio=system.iobus.master[4]
 
 [system.pc.south_bridge.keyboard.keyboard_int_pin]
 type=X86IntSourcePin
@@ -1391,7 +1392,7 @@ pio_addr=9223372036854775840
 pio_latency=100000
 slave=system.pc.south_bridge.pic2
 system=system
-pio=system.iobus.master[6]
+pio=system.iobus.master[5]
 
 [system.pc.south_bridge.pic1.output]
 type=X86IntSourcePin
@@ -1408,7 +1409,7 @@ pio_addr=9223372036854775968
 pio_latency=100000
 slave=Null
 system=system
-pio=system.iobus.master[7]
+pio=system.iobus.master[6]
 
 [system.pc.south_bridge.pic2.output]
 type=X86IntSourcePin
@@ -1423,7 +1424,7 @@ int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=100000
 system=system
-pio=system.iobus.master[8]
+pio=system.iobus.master[7]
 
 [system.pc.south_bridge.pit.int_pin]
 type=X86IntSourcePin
@@ -1437,7 +1438,7 @@ i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=100000
 system=system
-pio=system.iobus.master[9]
+pio=system.iobus.master[8]
 
 [system.physmem]
 type=DRAMCtrl
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index eaa04330e..1ecfaaabf 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simout
-Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 15 2015 15:16:56
-gem5 started Nov 15 2015 15:17:25
-gem5 executing on ribera.cs.wisc.edu, pid 9883
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
+gem5 compiled Dec  4 2015 15:10:31
+gem5 started Dec  4 2015 15:10:45
+gem5 executing on e104799-lin, pid 29579
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5194978362500 because m5_exit instruction encountered
+Exiting @ tick 5194947216500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index efb97e559..714c6f363 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.194978                       # Number of seconds simulated
-sim_ticks                                5194978362500                       # Number of ticks simulated
-final_tick                               5194978362500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.194947                       # Number of seconds simulated
+sim_ticks                                5194947216500                       # Number of ticks simulated
+final_tick                               5194947216500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 576808                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1111789                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            23330637170                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 654084                       # Number of bytes of host memory used
-host_seconds                                   222.67                       # Real time elapsed on the host
+host_inst_rate                                 724563                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1396583                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            29306793052                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 614800                       # Number of bytes of host memory used
+host_seconds                                   177.26                       # Real time elapsed on the host
 sim_insts                                   128436556                       # Number of instructions simulated
-sim_ops                                     247559471                       # Number of ops (including micro ops) simulated
+sim_ops                                     247559476                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
@@ -33,21 +33,21 @@ system.physmem.num_writes::writebacks          127367                       # Nu
 system.physmem.num_writes::total               127367                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker             12                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               158073                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1738430                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               158074                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1738440                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::pc.south_bridge.ide         5458                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1902034                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          158073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             158073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1569109                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1569109                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1569109                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total                 1902045                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          158074                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             158074                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1569119                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1569119                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1569119                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker            12                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              158073                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1738430                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              158074                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1738440                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::pc.south_bridge.ide         5458                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3471143                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3471164                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        154391                       # Number of read requests accepted
 system.physmem.writeReqs                       127367                       # Number of write requests accepted
 system.physmem.readBursts                      154391                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -94,7 +94,7 @@ system.physmem.perBankWrBursts::14               8023                       # Pe
 system.physmem.perBankWrBursts::15               7877                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5194978301500                       # Total gap between requests
+system.physmem.totGap                    5194947155500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -109,8 +109,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                 127367                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    151033                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2781                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    151032                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2782                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        60                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        55                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        39                       # What read queue length does an incoming req see
@@ -207,17 +207,17 @@ system.physmem.wrQLenPdf::62                        8                       # Wh
 system.physmem.wrQLenPdf::63                        3                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples        56850                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::mean      316.988566                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     188.998481                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.316521                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          20120     35.39%     35.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        13756     24.20%     59.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     189.004327                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     329.313677                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          20115     35.38%     35.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        13762     24.21%     59.59% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::256-383         6339     11.15%     70.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3490      6.14%     76.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2421      4.26%     81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1596      2.81%     83.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3489      6.14%     76.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2420      4.26%     81.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1597      2.81%     83.94% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::768-895         1162      2.04%     85.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          976      1.72%     87.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6990     12.30%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          977      1.72%     87.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6989     12.29%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total          56850                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          5891                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::mean        26.179766                       # Reads before turning the bus around for writes
@@ -259,12 +259,12 @@ system.physmem.wrPerTurnAround::152-155             1      0.02%     99.92% # Wr
 system.physmem.wrPerTurnAround::156-159             2      0.03%     99.95% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::164-167             3      0.05%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            5891                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1582264251                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4474283001                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     1583291001                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4475309751                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                    771205000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10258.39                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       10265.05                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29008.39                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29015.05                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.90                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.57                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.90                       # Average system read bandwidth in MiByte/s
@@ -279,69 +279,69 @@ system.physmem.readRowHits                     125535                       # Nu
 system.physmem.writeRowHits                     99190                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   81.39                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  77.88                       # Row buffer hit rate for writes
-system.physmem.avgGap                     18437731.32                       # Average gap between requests
+system.physmem.avgGap                     18437620.78                       # Average gap between requests
 system.physmem.pageHitRate                      79.80                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  210712320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  114972000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy                  210727440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  114980250                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                 605896200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                410112720                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           339310723440                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           137072385045                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2996748141750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             3474472943475                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.813734                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   4985245725974                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    173471480000                       # Time in different power states
+system.physmem_0.refreshEnergy           339308689200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           137072684295                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           2996729192250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             3474452282355                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.813767                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   4985214188974                       # Time in different power states
+system.physmem_0.memoryStateTime::REF    173470440000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     36261007776                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     36262439776                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  219073680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  119534250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  219058560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  119526000                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                 597183600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                415011600                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           339310723440                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           137522699865                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2996353144500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             3474537370935                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.826133                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   4984581893484                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    173471480000                       # Time in different power states
+system.physmem_1.refreshEnergy           339308689200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           137519874945                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           2996336934750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             3474516278655                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.826083                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   4984554950984                       # Time in different power states
+system.physmem_1.memoryStateTime::REF    173470440000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     36924866266                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     36921702766                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10389956725                       # number of cpu cycles simulated
+system.cpu.numCycles                      10389894433                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
 system.cpu.committedInsts                   128436556                       # Number of instructions committed
-system.cpu.committedOps                     247559471                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             232158304                       # Number of integer alu accesses
+system.cpu.committedOps                     247559476                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             232158308                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
 system.cpu.num_func_calls                     2315823                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     23152915                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    232158304                       # number of integer instructions
+system.cpu.num_conditional_control_insts     23152916                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    232158308                       # number of integer instructions
 system.cpu.num_fp_insts                            48                       # number of float instructions
-system.cpu.num_int_register_reads           434959162                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          197962951                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           434959182                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          197962963                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   48                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            132872909                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            95460932                       # number of times the CC registers were written
+system.cpu.num_cc_register_reads            132872914                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            95460933                       # number of times the CC registers were written
 system.cpu.num_mem_refs                      22321110                       # number of memory refs
 system.cpu.num_load_insts                    13911495                       # Number of load instructions
 system.cpu.num_store_insts                    8409615                       # Number of store instructions
 system.cpu.num_idle_cycles               9773995534.086119                       # Number of idle cycles
-system.cpu.num_busy_cycles               615961190.913881                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.059284                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.940716                       # Percentage of idle cycles
-system.cpu.Branches                          26327381                       # Number of branches fetched
-system.cpu.op_class::No_OpClass                172225      0.07%      0.07% # Class of executed instruction
+system.cpu.num_busy_cycles               615898898.913881                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.059279                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.940721                       # Percentage of idle cycles
+system.cpu.Branches                          26327382                       # Number of branches fetched
+system.cpu.op_class::No_OpClass                172226      0.07%      0.07% # Class of executed instruction
 system.cpu.op_class::IntAlu                 224809718     90.81%     90.88% # Class of executed instruction
 system.cpu.op_class::IntMult                   140099      0.06%     90.94% # Class of executed instruction
-system.cpu.op_class::IntDiv                    122811      0.05%     90.99% # Class of executed instruction
+system.cpu.op_class::IntDiv                    122815      0.05%     90.99% # Class of executed instruction
 system.cpu.op_class::FloatAdd                       0      0.00%     90.99% # Class of executed instruction
 system.cpu.op_class::FloatCmp                       0      0.00%     90.99% # Class of executed instruction
 system.cpu.op_class::FloatCvt                      16      0.00%     90.99% # Class of executed instruction
@@ -372,12 +372,12 @@ system.cpu.op_class::MemRead                 13906523      5.62%     96.60% # Cl
 system.cpu.op_class::MemWrite                 8409615      3.40%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
-system.cpu.op_class::total                  247561007                       # Class of executed instruction
-system.cpu.dcache.tags.replacements           1623701                       # number of replacements
+system.cpu.op_class::total                  247561012                       # Class of executed instruction
+system.cpu.dcache.tags.replacements           1623700                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.995481                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20139430                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1624213                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.399501                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            20139431                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1624212                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.399509                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle          81561500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.995481                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999991                       # Average percentage of cache occupancy
@@ -388,36 +388,36 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          353
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88718098                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88718098                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     12002647                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12002647                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8075474                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8075474                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          88718097                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88718097                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     12002646                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        12002646                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8075476                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8075476                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data        59092                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total         59092                       # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data      20078121                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20078121                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20137213                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20137213                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       907310                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        907310                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       326145                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       326145                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      20078122                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20078122                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20137214                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20137214                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       907311                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        907311                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       326143                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       326143                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data       402797                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total       402797                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1233455                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1233455                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1636252                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1636252                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  13562374500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  13562374500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18447994471                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18447994471                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  32010368971                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  32010368971                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  32010368971                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  32010368971                       # number of overall miss cycles
+system.cpu.dcache.demand_misses::cpu.data      1233454                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1233454                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1636251                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1636251                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  13562069000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13562069000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18448528971                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18448528971                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  32010597971                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  32010597971                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  32010597971                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  32010597971                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     12909957                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     12909957                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      8401619                       # number of WriteReq accesses(hits+misses)
@@ -438,14 +438,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.057877
 system.cpu.dcache.demand_miss_rate::total     0.057877                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.075149                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.075149                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14947.894876                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14947.894876                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56563.781358                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 56563.781358                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25951.793110                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25951.793110                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19563.226796                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19563.226796                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14947.541692                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14947.541692                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56565.767075                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 56565.767075                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25951.999808                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25951.999808                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19563.378706                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19563.378706                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs        18014                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs               511                       # number of cycles access was blocked
@@ -454,8 +454,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs    35.252446
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1540806                       # number of writebacks
-system.cpu.dcache.writebacks::total           1540806                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      1540805                       # number of writebacks
+system.cpu.dcache.writebacks::total           1540805                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          287                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          287                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9476                       # number of WriteReq MSHR hits
@@ -464,38 +464,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data         9763
 system.cpu.dcache.demand_mshr_hits::total         9763                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.overall_mshr_hits::cpu.data         9763                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total         9763                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       907023                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       907023                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       316669                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       316669                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       907024                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       907024                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       316667                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       316667                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402763                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total       402763                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1223692                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1223692                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1626455                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1626455                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1223691                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1223691                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1626454                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1626454                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       546346                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total       546346                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13920                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::total        13920                       # number of WriteReq MSHR uncacheable
 system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       560266                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.overall_mshr_uncacheable_misses::total       560266                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12653263500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12653263500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17148578471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17148578471                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6516458500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6516458500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29801841971                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29801841971                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36318300471                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  36318300471                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  95164003500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  95164003500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12652957000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12652957000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17148864471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  17148864471                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6516948000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6516948000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29801821471                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29801821471                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36318769471                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  36318769471                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  95132083500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  95132083500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2786304500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2786304500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  97950308000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  97950308000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  97918388000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  97918388000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.070258                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.070258                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037691                       # mshr miss rate for WriteReq accesses
@@ -506,29 +506,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057419
 system.cpu.dcache.demand_mshr_miss_rate::total     0.057419                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074699                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.074699                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13950.322649                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13950.322649                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54153.006676                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54153.006676                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16179.387133                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16179.387133                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24354.038411                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24354.038411                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22329.729670                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22329.729670                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174182.667211                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174182.667211                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13949.969350                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13949.969350                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54154.251851                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54154.251851                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.602488                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.602488                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24354.041560                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24354.041560                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22330.031757                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22330.031757                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.242696                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.242696                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200165.553161                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200165.553161                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174828.220881                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174828.220881                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.247943                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.247943                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.tags.replacements         7583                       # number of replacements
 system.cpu.dtb_walker_cache.tags.tagsinuse     5.052194                       # Cycle average of tags in use
 system.cpu.dtb_walker_cache.tags.total_refs        13349                       # Total number of references to valid blocks.
 system.cpu.dtb_walker_cache.tags.sampled_refs         7599                       # Sample count of references to valid blocks.
 system.cpu.dtb_walker_cache.tags.avg_refs     1.756679                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5163389935000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5163358790000                       # Cycle when the warmup percentage was hit.
 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.052194                       # Average occupied blocks per requestor
 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315762                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315762                       # Average percentage of cache occupancy
@@ -612,58 +612,58 @@ system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  9973.
 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  9973.842830                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            790533                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.212427                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           144635656                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           510.213577                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           144635652                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs            791045                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            182.841249                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      164582664500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.212427                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996509                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996509                       # Average percentage of cache occupancy
+system.cpu.icache.tags.avg_refs            182.841244                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      164551519500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.213577                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996511                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996511                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          292                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146217760                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146217760                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    144635656                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       144635656                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     144635656                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        144635656                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    144635656                       # number of overall hits
-system.cpu.icache.overall_hits::total       144635656                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         146217756                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146217756                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    144635652                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       144635652                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     144635652                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        144635652                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    144635652                       # number of overall hits
+system.cpu.icache.overall_hits::total       144635652                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst       791052                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        791052                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst       791052                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total         791052                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst       791052                       # number of overall misses
 system.cpu.icache.overall_misses::total        791052                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11850841500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11850841500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11850841500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11850841500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11850841500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11850841500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    145426708                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    145426708                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    145426708                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    145426708                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    145426708                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    145426708                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11851389500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11851389500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11851389500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11851389500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11851389500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11851389500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    145426704                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    145426704                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    145426704                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    145426704                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    145426704                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    145426704                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005440                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.005440                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.005440                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.005440                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.005440                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.005440                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14981.115654                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14981.115654                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14981.115654                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14981.115654                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14981.115654                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14981.115654                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14981.808402                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14981.808402                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14981.808402                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14981.808402                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14981.808402                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14981.808402                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -680,32 +680,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst       791052
 system.cpu.icache.demand_mshr_misses::total       791052                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst       791052                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total       791052                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11059789500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11059789500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11059789500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11059789500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11059789500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11059789500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11060337500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11060337500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11060337500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11060337500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11060337500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11060337500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005440                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005440                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005440                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.005440                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005440                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.005440                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13981.115654                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13981.115654                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13981.115654                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13981.115654                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13981.115654                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13981.115654                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13981.808402                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13981.808402                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13981.808402                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13981.808402                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13981.808402                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13981.808402                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.tags.replacements         3383                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.069439                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.tagsinuse     3.069434                       # Cycle average of tags in use
 system.cpu.itb_walker_cache.tags.total_refs         7971                       # Total number of references to valid blocks.
 system.cpu.itb_walker_cache.tags.sampled_refs         3396                       # Sample count of references to valid blocks.
 system.cpu.itb_walker_cache.tags.avg_refs     2.347173                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5168995728500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.069439                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.warmup_cycle 5168964583500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.069434                       # Average occupied blocks per requestor
 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191840                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_percent::total     0.191840                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
@@ -792,22 +792,22 @@ system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9568.
 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9568.872145                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements            87285                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64590.293077                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        64590.437600                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4366421                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           151981                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs            28.730045                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50117.072106                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 50117.146585                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.006346                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.146905                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3409.574017                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.493703                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.764726                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.146882                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3409.592137                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.545650                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.764727                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052026                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.168816                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.985570                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.985572                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        64696                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
@@ -815,32 +815,32 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2800
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5473                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56265                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987183                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         39229745                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        39229745                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      1544563                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      1544563                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.tag_accesses         39229727                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        39229727                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      1544562                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      1544562                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks       790520                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total       790520                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data          320                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total          320                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       200934                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       200934                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       200932                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       200932                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       778207                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total       778207                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker         6472                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker         2856                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1280544                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1289872                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1280545                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1289873                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker         6472                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         2856                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.inst       778207                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1481478                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2269013                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1481477                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2269012                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker         6472                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         2856                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.inst       778207                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1481478                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2269013                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1481477                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2269012                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data         1406                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total         1406                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data       113512                       # number of ReadExReq misses
@@ -863,52 +863,52 @@ system.cpu.l2cache.overall_misses::cpu.data       142006                       #
 system.cpu.l2cache.overall_misses::total       154844                       # number of overall misses
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     53960000                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total     53960000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14442230500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  14442230500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1691982000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total   1691982000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14442540500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14442540500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1692530000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total   1692530000                       # number of ReadCleanReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker       147000                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       637500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3748921500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   3749706000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3749093000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   3749877500                       # number of ReadSharedReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       147000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       637500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1691982000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  18191152000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  19883918500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1692530000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  18191633500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  19884948000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       147000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       637500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1691982000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  18191152000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  19883918500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      1544563                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      1544563                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1692530000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  18191633500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  19884948000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      1544562                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      1544562                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks       790520                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total       790520                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1726                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         1726                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       314446                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       314446                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       791039                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadCleanReq_accesses::total       791039                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker         6473                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker         2861                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1309038                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1318372                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1309039                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1318373                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6473                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         2861                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.inst       791039                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1623484                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2423857                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1623483                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2423856                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6473                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.itb.walker         2861                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst       791039                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1623484                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2423857                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1623483                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2423856                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.814600                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.814600                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.360990                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.360990                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.360993                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.360993                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016222                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016222                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000154                       # miss rate for ReadSharedReq accesses
@@ -927,24 +927,24 @@ system.cpu.l2cache.overall_miss_rate::cpu.data     0.087470
 system.cpu.l2cache.overall_miss_rate::total     0.063883                       # miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38378.378378                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38378.378378                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127230.869864                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127230.869864                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131856.452618                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131856.452618                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127233.600853                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127233.600853                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131899.158354                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131899.158354                       # average ReadCleanReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker       147000                       # average ReadSharedReq miss latency
 system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker       127500                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131568.803959                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131568.631579                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131574.822770                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131574.649123                       # average ReadSharedReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker       147000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       127500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131856.452618                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128101.291495                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 128412.586216                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131899.158354                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128104.682197                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 128419.234843                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker       147000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       127500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131856.452618                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128101.291495                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 128412.586216                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131899.158354                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128104.682197                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 128419.234843                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -985,36 +985,36 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       560266
 system.cpu.l2cache.overall_mshr_uncacheable_misses::total       560266                       # number of overall MSHR uncacheable misses
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    100407500                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    100407500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13307110500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13307110500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1563662000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1563662000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13307420500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13307420500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1564210000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1564210000                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker       137000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       587500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   3463981500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   3464706000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   3464153000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   3464877500                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       137000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       587500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1563662000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16771092000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  18335478500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1564210000                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::total  18336508000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       137000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       587500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1563662000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16771092000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  18335478500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  88334673500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  88334673500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1564210000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16771573500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  18336508000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  88302753500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  88302753500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2626222500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2626222500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  90960896000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  90960896000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  90928976000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  90928976000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.814600                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.814600                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.360990                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.360990                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.360993                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.360993                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016222                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016222                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000154                       # mshr miss rate for ReadSharedReq accesses
@@ -1033,68 +1033,68 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087470
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.063883                       # mshr miss rate for overall accesses
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71413.584637                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71413.584637                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117230.869864                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117230.869864                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121856.452618                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121856.452618                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117233.600853                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117233.600853                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121899.158354                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121899.158354                       # average ReadCleanReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker       137000                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121568.803959                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121568.631579                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121574.822770                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121574.649123                       # average ReadSharedReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker       137000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121856.452618                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118101.291495                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118412.586216                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121899.158354                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118104.682197                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118419.234843                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker       137000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       117500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121856.452618                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118101.291495                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118412.586216                       # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161682.658059                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161682.658059                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121899.158354                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118104.682197                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118419.234843                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.233544                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.233544                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188665.409483                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188665.409483                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162353.053728                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162353.053728                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.080790                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.080790                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4855760                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2425141                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      4855758                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2425140                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        11068                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1020                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1020                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadReq         546346                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2660535                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2660536                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq         13920                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp        13920                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      1671932                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      1671931                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean       790520                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict        91754                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq         2230                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp         2230                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       314452                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       314452                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       314450                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       314450                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadCleanReq       791052                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1323668                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1323669                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::MessageReq         1654                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2372611                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5995602                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5995599                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         8612                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        19573                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8396398                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8396395                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    101219776                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    204103208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    204103080                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       232576                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       605248                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          306160808                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          306160680                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                      189298                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3174836                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples      3174835                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.004492                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.077863                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3163102     99.63%     99.63% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3163101     99.63%     99.63% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1               9208      0.29%     99.92% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2               2526      0.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
@@ -1102,14 +1102,14 @@ system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Re
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3174836                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5050069000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3174835                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5050067000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       571290                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy    1186578000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2990781992                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2990780492                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer2.occupancy       6370500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
@@ -1124,7 +1124,6 @@ system.iobus.trans_dist::MessageResp             1654                       # Tr
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
@@ -1138,7 +1137,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio         2308                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       452398                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95124                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95124                       # Packet count per connected master and slave (bytes)
@@ -1148,7 +1147,6 @@ system.iobus.pkt_count::total                  550830                       # Pa
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
@@ -1162,7 +1160,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio         4477                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.bridge.master::total       232479                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027280                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027280                       # Cumulative packet size per connected master and slave (bytes)
@@ -1177,38 +1175,36 @@ system.iobus.reqLayer2.occupancy                 6000                       # La
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer3.occupancy             10045000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy               149500                       # Layer occupancy (ticks)
+system.iobus.reqLayer4.occupancy              1094500                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy              1094500                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy                79000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                79000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                50500                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                50500                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                26000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
+system.iobus.reqLayer8.occupancy            306124500                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            306124500                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy              1113000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy             1113000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              177500                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer11.occupancy              177500                       # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
+system.iobus.reqLayer13.occupancy            24284500                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy            24284500                       # Layer occupancy (ticks)
+system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer16.occupancy               10500                       # Layer occupancy (ticks)
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
+system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           240815899                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy           240815899                       # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy             1216500                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer20.occupancy             1067000                       # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy           441392000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy            50036000                       # Layer occupancy (ticks)
@@ -1220,7 +1216,7 @@ system.iocache.tags.tagsinuse                0.108263                       # Cy
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                47523                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5048362105000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.warmup_cycle         5048330960000                       # Cycle when the warmup percentage was hit.
 system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.108263                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006766                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.006766                       # Average percentage of cache occupancy
@@ -1363,11 +1359,11 @@ system.membus.reqLayer1.occupancy           503567500                       # La
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer2.occupancy             4013184                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           852595093                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           852595593                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer0.occupancy            2359184                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1928197366                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1928199616                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.membus.respLayer4.occupancy           85638132                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 1a50e3aec..208c3a429 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -5,10 +5,10 @@ boot_cpu_frequency=250
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=drivesys.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/work/gem5/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/work/gem5/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -18,8 +18,8 @@ memories=drivesys.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-server.rcS
+pal=/work/gem5/dist/binaries/ts_osfpal
+readfile=/work/gem5/outgoing/gem5_2/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -139,7 +139,7 @@ table_size=65536
 [drivesys.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [drivesys.disk2]
@@ -162,7 +162,7 @@ table_size=65536
 [drivesys.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [drivesys.dvfs_handler]
@@ -187,7 +187,7 @@ ranges=0:134217727
 req_size=16
 resp_size=16
 master=drivesys.membus.slave[3]
-slave=drivesys.iobus.master[29]
+slave=drivesys.iobus.master[27]
 
 [drivesys.iobus]
 type=NoncoherentXBar
@@ -196,10 +196,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=drivesys.tsunami.pciconfig.pio
-master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ide.config drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.iobridge.slave
+master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ethernet.pio drivesys.iobridge.slave
 slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma
 
 [drivesys.membus]
@@ -260,7 +259,7 @@ system=drivesys
 [drivesys.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [drivesys.terminal]
@@ -273,7 +272,7 @@ port=3456
 
 [drivesys.tsunami]
 type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 eventq_index=0
 intrctrl=drivesys.intrctrl
 system=drivesys
@@ -387,12 +386,12 @@ dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
 hardware_address=00:90:00:00:00:01
+host=drivesys.tsunami.pchip
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=drivesys.tsunami
 rss=false
 rx_delay=1000000
 rx_fifo_size=524288
@@ -402,10 +401,9 @@ system=drivesys
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=drivesys.iobus.master[28]
 dma=drivesys.iobus.slave[2]
 interface=etherlink.int1
-pio=drivesys.iobus.master[27]
+pio=drivesys.iobus.master[26]
 
 [drivesys.tsunami.ethernet.clk_domain]
 type=SrcClockDomain
@@ -846,14 +844,13 @@ config_latency=20000
 ctrl_offset=0
 disks=drivesys.disk0 drivesys.disk2
 eventq_index=0
+host=drivesys.tsunami.pchip
 io_shift=0
 pci_bus=0
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=drivesys.tsunami
 system=drivesys
-config=drivesys.iobus.master[26]
 dma=drivesys.iobus.slave[1]
 pio=drivesys.iobus.master[25]
 
@@ -873,25 +870,20 @@ pio=drivesys.iobus.master[22]
 [drivesys.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=drivesys.clk_domain
+conf_base=8804649402368
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
+pci_dma_base=0
+pci_mem_base=8796093022208
+pci_pio_base=8804615847936
 pio_addr=8802535473152
 pio_latency=100000
+platform=drivesys.tsunami
 system=drivesys
 tsunami=drivesys.tsunami
 pio=drivesys.iobus.master[1]
 
-[drivesys.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=drivesys.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=drivesys.tsunami
-size=16777216
-system=drivesys
-pio=drivesys.iobus.default
-
 [drivesys.tsunami.uart]
 type=Uart8250
 clk_domain=drivesys.clk_domain
@@ -941,10 +933,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=testsys.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/work/gem5/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/work/gem5/dist/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -954,8 +946,8 @@ memories=testsys.physmem
 mmap_using_noreserve=false
 multi_thread=false
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-stream-client.rcS
+pal=/work/gem5/dist/binaries/ts_osfpal
+readfile=/work/gem5/outgoing/gem5_2/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -1075,7 +1067,7 @@ table_size=65536
 [testsys.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [testsys.disk2]
@@ -1098,7 +1090,7 @@ table_size=65536
 [testsys.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/work/gem5/dist/disks/linux-bigswap2.img
 read_only=true
 
 [testsys.dvfs_handler]
@@ -1123,7 +1115,7 @@ ranges=0:134217727
 req_size=16
 resp_size=16
 master=testsys.membus.slave[3]
-slave=testsys.iobus.master[29]
+slave=testsys.iobus.master[27]
 
 [testsys.iobus]
 type=NoncoherentXBar
@@ -1132,10 +1124,9 @@ eventq_index=0
 forward_latency=1
 frontend_latency=2
 response_latency=2
-use_default_range=true
+use_default_range=false
 width=16
-default=testsys.tsunami.pciconfig.pio
-master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ide.config testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.iobridge.slave
+master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ethernet.pio testsys.iobridge.slave
 slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
 
 [testsys.membus]
@@ -1196,7 +1187,7 @@ system=testsys
 [testsys.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/work/gem5/dist/disks/linux-latest.img
 read_only=true
 
 [testsys.terminal]
@@ -1209,7 +1200,7 @@ port=3456
 
 [testsys.tsunami]
 type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
 eventq_index=0
 intrctrl=testsys.intrctrl
 system=testsys
@@ -1323,12 +1314,12 @@ dma_write_delay=0
 dma_write_factor=0
 eventq_index=0
 hardware_address=00:90:00:00:00:02
+host=testsys.tsunami.pchip
 intr_delay=10000000
 pci_bus=0
 pci_dev=1
 pci_func=0
 pio_latency=30000
-platform=testsys.tsunami
 rss=false
 rx_delay=1000000
 rx_fifo_size=524288
@@ -1338,10 +1329,9 @@ system=testsys
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=testsys.iobus.master[28]
 dma=testsys.iobus.slave[2]
 interface=etherlink.int0
-pio=testsys.iobus.master[27]
+pio=testsys.iobus.master[26]
 
 [testsys.tsunami.ethernet.clk_domain]
 type=SrcClockDomain
@@ -1782,14 +1772,13 @@ config_latency=20000
 ctrl_offset=0
 disks=testsys.disk0 testsys.disk2
 eventq_index=0
+host=testsys.tsunami.pchip
 io_shift=0
 pci_bus=0
 pci_dev=0
 pci_func=0
 pio_latency=30000
-platform=testsys.tsunami
 system=testsys
-config=testsys.iobus.master[26]
 dma=testsys.iobus.slave[1]
 pio=testsys.iobus.master[25]
 
@@ -1809,25 +1798,20 @@ pio=testsys.iobus.master[22]
 [testsys.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=testsys.clk_domain
+conf_base=8804649402368
+conf_device_bits=8
+conf_size=16777216
 eventq_index=0
+pci_dma_base=0
+pci_mem_base=8796093022208
+pci_pio_base=8804615847936
 pio_addr=8802535473152
 pio_latency=100000
+platform=testsys.tsunami
 system=testsys
 tsunami=testsys.tsunami
 pio=testsys.iobus.master[1]
 
-[testsys.tsunami.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=testsys.clk_domain
-eventq_index=0
-pio_addr=0
-pio_latency=30000
-platform=testsys.tsunami
-size=16777216
-system=testsys
-pio=testsys.iobus.default
-
 [testsys.tsunami.uart]
 type=Uart8250
 clk_domain=testsys.clk_domain
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index 511eb15bc..2589e1cef 100755
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
@@ -1,17 +1,15 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Nov 15 2015 14:28:00
-gem5 started Nov 15 2015 14:29:50
-gem5 executing on ribera.cs.wisc.edu, pid 29123
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+gem5 compiled Dec  4 2015 10:28:58
+gem5 started Dec  4 2015 10:42:31
+gem5 executing on e104799-lin, pid 22915
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /work/gem5/dist/binaries/vmlinux
       0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /work/gem5/dist/binaries/vmlinux
       0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 4321620817500 because checkpoint
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 7d0bc2ece..868609296 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.200409                       # Nu
 sim_ticks                                200409271000                       # Number of ticks simulated
 final_tick                               4321213476000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                               20752053                       # Simulator instruction rate (inst/s)
-host_op_rate                                 20752044                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7940152278                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 485568                       # Number of bytes of host memory used
-host_seconds                                    25.24                       # Real time elapsed on the host
+host_inst_rate                               12150896                       # Simulator instruction rate (inst/s)
+host_op_rate                                 12150892                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4649177813                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 500080                       # Number of bytes of host memory used
+host_seconds                                    43.11                       # Real time elapsed on the host
 sim_insts                                   523780905                       # Number of instructions simulated
 sim_ops                                     523780905                       # Number of ops (including micro ops) simulated
 drivesys.voltage_domain.voltage                     1                       # Voltage in Volts
@@ -78,61 +78,6 @@ drivesys.cpu.itb.data_accesses                      0                       # DT
 drivesys.cpu.numCycles                      801651324                       # number of cpu cycles simulated
 drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
 drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.committedInsts                  19050784                       # Number of instructions committed
-drivesys.cpu.committedOps                    19050784                       # Number of ops (including micro ops) committed
-drivesys.cpu.num_int_alu_accesses            17740632                       # Number of integer alu accesses
-drivesys.cpu.num_fp_alu_accesses                 1412                       # Number of float alu accesses
-drivesys.cpu.num_func_calls                   1265024                       # number of times a function call or return occured
-drivesys.cpu.num_conditional_control_insts      1264985                       # number of instructions that are conditional controls
-drivesys.cpu.num_int_insts                   17740632                       # number of integer instructions
-drivesys.cpu.num_fp_insts                        1412                       # number of float instructions
-drivesys.cpu.num_int_register_reads          23072330                       # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes         13981107                       # number of times the integer registers were written
-drivesys.cpu.num_fp_register_reads                760                       # number of times the floating registers were read
-drivesys.cpu.num_fp_register_writes               766                       # number of times the floating registers were written
-drivesys.cpu.num_mem_refs                     5830788                       # number of memory refs
-drivesys.cpu.num_load_insts                   3746196                       # Number of load instructions
-drivesys.cpu.num_store_insts                  2084592                       # Number of store instructions
-drivesys.cpu.num_idle_cycles             782619252.927065                       # Number of idle cycles
-drivesys.cpu.num_busy_cycles             19032071.072935                       # Number of busy cycles
-drivesys.cpu.not_idle_fraction               0.023741                       # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction                   0.976259                       # Percentage of idle cycles
-drivesys.cpu.Branches                         2793313                       # Number of branches fetched
-drivesys.cpu.op_class::No_OpClass              623554      3.27%      3.27% # Class of executed instruction
-drivesys.cpu.op_class::IntAlu                11538627     60.57%     63.84% # Class of executed instruction
-drivesys.cpu.op_class::IntMult                  20663      0.11%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::IntDiv                       0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatAdd                   141      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatCmp                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatCvt                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatMult                    0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatDiv                    23      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::FloatSqrt                    0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdAdd                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdAddAcc                   0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdAlu                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdCmp                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdCvt                      0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdMisc                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdMult                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdMultAcc                  0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdShift                    0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdShiftAcc                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdSqrt                     0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatAdd                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatAlu                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatCmp                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatCvt                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatDiv                 0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMisc                0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMult                0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatMultAcc             0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::SimdFloatSqrt                0      0.00%     63.95% # Class of executed instruction
-drivesys.cpu.op_class::MemRead                4026028     21.13%     85.08% # Class of executed instruction
-drivesys.cpu.op_class::MemWrite               2085021     10.94%     96.02% # Class of executed instruction
-drivesys.cpu.op_class::IprAccess               757336      3.98%    100.00% # Class of executed instruction
-drivesys.cpu.op_class::InstPrefetch                 0      0.00%    100.00% # Class of executed instruction
-drivesys.cpu.op_class::total                 19051393                       # Class of executed instruction
 drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
 drivesys.cpu.kern.inst.quiesce                  19876                       # number of quiesce instructions executed
 drivesys.cpu.kern.inst.hwrei                   143591                       # number of hwrei instructions executed
@@ -192,6 +137,61 @@ drivesys.cpu.kern.mode_ticks::kernel         78134250      2.63%      2.63% # nu
 drivesys.cpu.kern.mode_ticks::user          319668250     10.78%     13.41% # number of ticks spent at the given mode
 drivesys.cpu.kern.mode_ticks::idle         2567942000     86.59%    100.00% # number of ticks spent at the given mode
 drivesys.cpu.kern.swap_context                     72                       # number of times the context was actually changed
+drivesys.cpu.committedInsts                  19050784                       # Number of instructions committed
+drivesys.cpu.committedOps                    19050784                       # Number of ops (including micro ops) committed
+drivesys.cpu.num_int_alu_accesses            17740632                       # Number of integer alu accesses
+drivesys.cpu.num_fp_alu_accesses                 1412                       # Number of float alu accesses
+drivesys.cpu.num_func_calls                   1265024                       # number of times a function call or return occured
+drivesys.cpu.num_conditional_control_insts      1264985                       # number of instructions that are conditional controls
+drivesys.cpu.num_int_insts                   17740632                       # number of integer instructions
+drivesys.cpu.num_fp_insts                        1412                       # number of float instructions
+drivesys.cpu.num_int_register_reads          23072330                       # number of times the integer registers were read
+drivesys.cpu.num_int_register_writes         13981107                       # number of times the integer registers were written
+drivesys.cpu.num_fp_register_reads                760                       # number of times the floating registers were read
+drivesys.cpu.num_fp_register_writes               766                       # number of times the floating registers were written
+drivesys.cpu.num_mem_refs                     5830788                       # number of memory refs
+drivesys.cpu.num_load_insts                   3746196                       # Number of load instructions
+drivesys.cpu.num_store_insts                  2084592                       # Number of store instructions
+drivesys.cpu.num_idle_cycles             782619252.927065                       # Number of idle cycles
+drivesys.cpu.num_busy_cycles             19032071.072935                       # Number of busy cycles
+drivesys.cpu.not_idle_fraction               0.023741                       # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction                   0.976259                       # Percentage of idle cycles
+drivesys.cpu.Branches                         2793313                       # Number of branches fetched
+drivesys.cpu.op_class::No_OpClass              623554      3.27%      3.27% # Class of executed instruction
+drivesys.cpu.op_class::IntAlu                11538627     60.57%     63.84% # Class of executed instruction
+drivesys.cpu.op_class::IntMult                  20663      0.11%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::IntDiv                       0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatAdd                   141      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatCmp                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatCvt                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatMult                    0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatDiv                    23      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::FloatSqrt                    0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdAdd                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdAddAcc                   0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdAlu                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdCmp                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdCvt                      0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdMisc                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdMult                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdMultAcc                  0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdShift                    0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdShiftAcc                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdSqrt                     0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatAdd                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatAlu                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatCmp                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatCvt                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatDiv                 0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMisc                0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMult                0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatMultAcc             0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::SimdFloatSqrt                0      0.00%     63.95% # Class of executed instruction
+drivesys.cpu.op_class::MemRead                4026028     21.13%     85.08% # Class of executed instruction
+drivesys.cpu.op_class::MemWrite               2085021     10.94%     96.02% # Class of executed instruction
+drivesys.cpu.op_class::IprAccess               757336      3.98%    100.00% # Class of executed instruction
+drivesys.cpu.op_class::InstPrefetch                 0      0.00%    100.00% # Class of executed instruction
+drivesys.cpu.op_class::total                 19051393                       # Class of executed instruction
 drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
 drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
 drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
@@ -371,61 +371,6 @@ testsys.cpu.itb.data_accesses                       0                       # DT
 testsys.cpu.numCycles                       400825859                       # number of cpu cycles simulated
 testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
 testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.committedInsts                   20257044                       # Number of instructions committed
-testsys.cpu.committedOps                     20257044                       # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses             18836392                       # Number of integer alu accesses
-testsys.cpu.num_fp_alu_accesses                 17380                       # Number of float alu accesses
-testsys.cpu.num_func_calls                    1221158                       # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts      1442105                       # number of instructions that are conditional controls
-testsys.cpu.num_int_insts                    18836392                       # number of integer instructions
-testsys.cpu.num_fp_insts                        17380                       # number of float instructions
-testsys.cpu.num_int_register_reads           24786330                       # number of times the integer registers were read
-testsys.cpu.num_int_register_writes          14693469                       # number of times the integer registers were written
-testsys.cpu.num_fp_register_reads               11166                       # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes              10823                       # number of times the floating registers were written
-testsys.cpu.num_mem_refs                      6262732                       # number of memory refs
-testsys.cpu.num_load_insts                    3943883                       # Number of load instructions
-testsys.cpu.num_store_insts                   2318849                       # Number of store instructions
-testsys.cpu.num_idle_cycles              380582482.461103                       # Number of idle cycles
-testsys.cpu.num_busy_cycles              20243376.538897                       # Number of busy cycles
-testsys.cpu.not_idle_fraction                0.050504                       # Percentage of non-idle cycles
-testsys.cpu.idle_fraction                    0.949496                       # Percentage of idle cycles
-testsys.cpu.Branches                          2929782                       # Number of branches fetched
-testsys.cpu.op_class::No_OpClass               712785      3.52%      3.52% # Class of executed instruction
-testsys.cpu.op_class::IntAlu                 12147004     59.95%     63.47% # Class of executed instruction
-testsys.cpu.op_class::IntMult                   21654      0.11%     63.58% # Class of executed instruction
-testsys.cpu.op_class::IntDiv                        0      0.00%     63.58% # Class of executed instruction
-testsys.cpu.op_class::FloatAdd                   4655      0.02%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatCmp                      1      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatCvt                      0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatMult                     0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatDiv                    922      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::FloatSqrt                     0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdAdd                       0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdAddAcc                    0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdAlu                       0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdCmp                       0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdCvt                       0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdMisc                      0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdMult                      0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdMultAcc                   0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdShift                     0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdShiftAcc                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdSqrt                      0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAdd                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatAlu                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCmp                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatCvt                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatDiv                  0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMisc                 0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMult                 0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatMultAcc              0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::SimdFloatSqrt                 0      0.00%     63.60% # Class of executed instruction
-testsys.cpu.op_class::MemRead                 4230485     20.88%     84.48% # Class of executed instruction
-testsys.cpu.op_class::MemWrite                2319388     11.45%     95.93% # Class of executed instruction
-testsys.cpu.op_class::IprAccess                824126      4.07%    100.00% # Class of executed instruction
-testsys.cpu.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-testsys.cpu.op_class::total                  20261020                       # Class of executed instruction
 testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
 testsys.cpu.kern.inst.quiesce                   19580                       # number of quiesce instructions executed
 testsys.cpu.kern.inst.hwrei                    153669                       # number of hwrei instructions executed
@@ -495,6 +440,61 @@ testsys.cpu.kern.mode_ticks::kernel         994253000     59.96%     59.96% # nu
 testsys.cpu.kern.mode_ticks::user           533088000     32.15%     92.11% # number of ticks spent at the given mode
 testsys.cpu.kern.mode_ticks::idle           130749000      7.89%    100.00% # number of ticks spent at the given mode
 testsys.cpu.kern.swap_context                     438                       # number of times the context was actually changed
+testsys.cpu.committedInsts                   20257044                       # Number of instructions committed
+testsys.cpu.committedOps                     20257044                       # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses             18836392                       # Number of integer alu accesses
+testsys.cpu.num_fp_alu_accesses                 17380                       # Number of float alu accesses
+testsys.cpu.num_func_calls                    1221158                       # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts      1442105                       # number of instructions that are conditional controls
+testsys.cpu.num_int_insts                    18836392                       # number of integer instructions
+testsys.cpu.num_fp_insts                        17380                       # number of float instructions
+testsys.cpu.num_int_register_reads           24786330                       # number of times the integer registers were read
+testsys.cpu.num_int_register_writes          14693469                       # number of times the integer registers were written
+testsys.cpu.num_fp_register_reads               11166                       # number of times the floating registers were read
+testsys.cpu.num_fp_register_writes              10823                       # number of times the floating registers were written
+testsys.cpu.num_mem_refs                      6262732                       # number of memory refs
+testsys.cpu.num_load_insts                    3943883                       # Number of load instructions
+testsys.cpu.num_store_insts                   2318849                       # Number of store instructions
+testsys.cpu.num_idle_cycles              380582482.461103                       # Number of idle cycles
+testsys.cpu.num_busy_cycles              20243376.538897                       # Number of busy cycles
+testsys.cpu.not_idle_fraction                0.050504                       # Percentage of non-idle cycles
+testsys.cpu.idle_fraction                    0.949496                       # Percentage of idle cycles
+testsys.cpu.Branches                          2929782                       # Number of branches fetched
+testsys.cpu.op_class::No_OpClass               712785      3.52%      3.52% # Class of executed instruction
+testsys.cpu.op_class::IntAlu                 12147004     59.95%     63.47% # Class of executed instruction
+testsys.cpu.op_class::IntMult                   21654      0.11%     63.58% # Class of executed instruction
+testsys.cpu.op_class::IntDiv                        0      0.00%     63.58% # Class of executed instruction
+testsys.cpu.op_class::FloatAdd                   4655      0.02%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatCmp                      1      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatCvt                      0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatMult                     0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatDiv                    922      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::FloatSqrt                     0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdAdd                       0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdAddAcc                    0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdAlu                       0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdCmp                       0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdCvt                       0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdMisc                      0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdMult                      0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdMultAcc                   0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdShift                     0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdShiftAcc                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdSqrt                      0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAdd                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatAlu                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCmp                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatCvt                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatDiv                  0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMisc                 0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMult                 0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatMultAcc              0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::SimdFloatSqrt                 0      0.00%     63.60% # Class of executed instruction
+testsys.cpu.op_class::MemRead                 4230485     20.88%     84.48% # Class of executed instruction
+testsys.cpu.op_class::MemWrite                2319388     11.45%     95.93% # Class of executed instruction
+testsys.cpu.op_class::IprAccess                824126      4.07%    100.00% # Class of executed instruction
+testsys.cpu.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
+testsys.cpu.op_class::total                  20261020                       # Class of executed instruction
 testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
 testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
 testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
@@ -619,11 +619,11 @@ sim_seconds                                  0.000407                       # Nu
 sim_ticks                                   407341500                       # Number of ticks simulated
 final_tick                               4321620817500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                            10415397218                       # Simulator instruction rate (inst/s)
-host_op_rate                              10413013630                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8095289719                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 485568                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                             5761027657                       # Simulator instruction rate (inst/s)
+host_op_rate                               5760057644                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4478236963                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 500080                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                   523853183                       # Number of instructions simulated
 sim_ops                                     523853183                       # Number of ops (including micro ops) simulated
 drivesys.voltage_domain.voltage                     1                       # Voltage in Volts
@@ -690,6 +690,47 @@ drivesys.cpu.itb.data_accesses                      0                       # DT
 drivesys.cpu.numCycles                        1626281                       # number of cpu cycles simulated
 drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
 drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
+drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
+drivesys.cpu.kern.inst.quiesce                     41                       # number of quiesce instructions executed
+drivesys.cpu.kern.inst.hwrei                      295                       # number of hwrei instructions executed
+drivesys.cpu.kern.ipl_count::0                    123     41.84%     41.84% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::21                    40     13.61%     55.44% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::22                     1      0.34%     55.78% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::31                   130     44.22%    100.00% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::total                294                       # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_good::0                     123     42.86%     42.86% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::21                     40     13.94%     56.79% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::22                      1      0.35%     57.14% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::31                    123     42.86%    100.00% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::total                 287                       # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_ticks::0              400289000     98.46%     98.46% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::21               1620000      0.40%     98.86% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::22                 21500      0.01%     98.86% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::31               4629500      1.14%    100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::total          406560000                       # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_used::0                       1                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::21                      1                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::22                      1                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::31               0.946154                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::total            0.976190                       # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.callpal::swpipl                 212     83.46%     83.46% # number of callpals executed
+drivesys.cpu.kern.callpal::rdps                     1      0.39%     83.86% # number of callpals executed
+drivesys.cpu.kern.callpal::rti                     41     16.14%    100.00% # number of callpals executed
+drivesys.cpu.kern.callpal::total                  254                       # number of callpals executed
+drivesys.cpu.kern.mode_switch::kernel               0                       # number of protection mode switches
+drivesys.cpu.kern.mode_switch::user                 0                       # number of protection mode switches
+drivesys.cpu.kern.mode_switch::idle                41                       # number of protection mode switches
+drivesys.cpu.kern.mode_good::kernel                 0                      
+drivesys.cpu.kern.mode_good::user                   0                      
+drivesys.cpu.kern.mode_good::idle                   0                      
+drivesys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::user          nan                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::idle            0                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::total            0                       # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_ticks::kernel                0                       # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::user                  0                       # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::idle                  0                       # number of ticks spent at the given mode
+drivesys.cpu.kern.swap_context                      0                       # number of times the context was actually changed
 drivesys.cpu.committedInsts                     36152                       # Number of instructions committed
 drivesys.cpu.committedOps                       36152                       # Number of ops (including micro ops) committed
 drivesys.cpu.num_int_alu_accesses               33516                       # Number of integer alu accesses
@@ -745,47 +786,6 @@ drivesys.cpu.op_class::MemWrite                  3936     10.89%     95.73% # Cl
 drivesys.cpu.op_class::IprAccess                 1545      4.27%    100.00% # Class of executed instruction
 drivesys.cpu.op_class::InstPrefetch                 0      0.00%    100.00% # Class of executed instruction
 drivesys.cpu.op_class::total                    36152                       # Class of executed instruction
-drivesys.cpu.kern.inst.arm                          0                       # number of arm instructions executed
-drivesys.cpu.kern.inst.quiesce                     41                       # number of quiesce instructions executed
-drivesys.cpu.kern.inst.hwrei                      295                       # number of hwrei instructions executed
-drivesys.cpu.kern.ipl_count::0                    123     41.84%     41.84% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::21                    40     13.61%     55.44% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::22                     1      0.34%     55.78% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31                   130     44.22%    100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total                294                       # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0                     123     42.86%     42.86% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::21                     40     13.94%     56.79% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::22                      1      0.35%     57.14% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31                    123     42.86%    100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total                 287                       # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0              400289000     98.46%     98.46% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21               1620000      0.40%     98.86% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::22                 21500      0.01%     98.86% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31               4629500      1.14%    100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total          406560000                       # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_used::0                       1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::21                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::22                      1                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31               0.946154                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::total            0.976190                       # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.callpal::swpipl                 212     83.46%     83.46% # number of callpals executed
-drivesys.cpu.kern.callpal::rdps                     1      0.39%     83.86% # number of callpals executed
-drivesys.cpu.kern.callpal::rti                     41     16.14%    100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total                  254                       # number of callpals executed
-drivesys.cpu.kern.mode_switch::kernel               0                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::user                 0                       # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle                41                       # number of protection mode switches
-drivesys.cpu.kern.mode_good::kernel                 0                      
-drivesys.cpu.kern.mode_good::user                   0                      
-drivesys.cpu.kern.mode_good::idle                   0                      
-drivesys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::user          nan                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::idle            0                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total            0                       # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks::kernel                0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user                  0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle                  0                       # number of ticks spent at the given mode
-drivesys.cpu.kern.swap_context                      0                       # number of times the context was actually changed
 drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
 drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
 drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
@@ -944,6 +944,47 @@ testsys.cpu.itb.data_accesses                       0                       # DT
 testsys.cpu.numCycles                          821056                       # number of cpu cycles simulated
 testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
 testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
+testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
+testsys.cpu.kern.inst.quiesce                      40                       # number of quiesce instructions executed
+testsys.cpu.kern.inst.hwrei                       295                       # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0                     123     41.84%     41.84% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21                     40     13.61%     55.44% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::22                      1      0.34%     55.78% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::31                    130     44.22%    100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total                 294                       # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good::0                      123     42.86%     42.86% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::21                      40     13.94%     56.79% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::22                       1      0.35%     57.14% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::31                     123     42.86%    100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::total                  287                       # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks::0               397967000     96.95%     96.95% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::21                3240000      0.79%     97.73% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::22                  43000      0.01%     97.74% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31                9258000      2.26%    100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total           410508000                       # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_used::0                        1                       # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::31                0.946154                       # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total             0.976190                       # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.callpal::swpipl                  212     83.46%     83.46% # number of callpals executed
+testsys.cpu.kern.callpal::rdps                      1      0.39%     83.86% # number of callpals executed
+testsys.cpu.kern.callpal::rti                      41     16.14%    100.00% # number of callpals executed
+testsys.cpu.kern.callpal::total                   254                       # number of callpals executed
+testsys.cpu.kern.mode_switch::kernel                0                       # number of protection mode switches
+testsys.cpu.kern.mode_switch::user                  0                       # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle                 41                       # number of protection mode switches
+testsys.cpu.kern.mode_good::kernel                  0                      
+testsys.cpu.kern.mode_good::user                    0                      
+testsys.cpu.kern.mode_good::idle                    0                      
+testsys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::idle             0                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::total            0                       # fraction of useful protection mode switches
+testsys.cpu.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
+testsys.cpu.kern.swap_context                       0                       # number of times the context was actually changed
 testsys.cpu.committedInsts                      36126                       # Number of instructions committed
 testsys.cpu.committedOps                        36126                       # Number of ops (including micro ops) committed
 testsys.cpu.num_int_alu_accesses                33492                       # Number of integer alu accesses
@@ -999,47 +1040,6 @@ testsys.cpu.op_class::MemWrite                   3938     10.90%     95.72% # Cl
 testsys.cpu.op_class::IprAccess                  1545      4.28%    100.00% # Class of executed instruction
 testsys.cpu.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
 testsys.cpu.op_class::total                     36126                       # Class of executed instruction
-testsys.cpu.kern.inst.arm                           0                       # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce                      40                       # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei                       295                       # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0                     123     41.84%     41.84% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21                     40     13.61%     55.44% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22                      1      0.34%     55.78% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31                    130     44.22%    100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total                 294                       # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0                      123     42.86%     42.86% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21                      40     13.94%     56.79% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22                       1      0.35%     57.14% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31                     123     42.86%    100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total                  287                       # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0               397967000     96.95%     96.95% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21                3240000      0.79%     97.73% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::22                  43000      0.01%     97.74% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31                9258000      2.26%    100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total           410508000                       # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_used::0                        1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31                0.946154                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total             0.976190                       # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.callpal::swpipl                  212     83.46%     83.46% # number of callpals executed
-testsys.cpu.kern.callpal::rdps                      1      0.39%     83.86% # number of callpals executed
-testsys.cpu.kern.callpal::rti                      41     16.14%    100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total                   254                       # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel                0                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::user                  0                       # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle                 41                       # number of protection mode switches
-testsys.cpu.kern.mode_good::kernel                  0                      
-testsys.cpu.kern.mode_good::user                    0                      
-testsys.cpu.kern.mode_good::idle                    0                      
-testsys.cpu.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle             0                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::total            0                       # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context                       0                       # number of times the context was actually changed
 testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
 testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
 testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).